16 Introduc on to Embedded Systems

The Typical Embedded

2 System

LEARNING OBJECTIVES

LO 1 Iden fy the building blocks of a typical Embedded System

Learn about GPPs, ASIPs, Microprocessors, Microcontrollers, Digital Signal
Processors, RISC & CISC processors, Harvard and Von-Neumann Processor
Architecture, Big-endian v/s Li le endian processors, Load Store opera on and
Instruc on pipelining
Understand different PLDs like CPLDs, FPGAs, etc.
LO 2 Explain different memory technologies and memory types used in embedded system
development
Learn about MROM, PROM, OTP, EPROM, EEPROM and FLASH memory
Describe SAM, SRAM, DRAM, and NVRAM
List the factors to be considered in the memory selec on
LO 3 Analyse the role of sensors, actuators, and their interfacing with the I/O subsystems of
an embedded system
Learn about the interfacing of LEDs, 7-segment LED Displays, Piezo Buzzer,
Stepper Motor, Relays, Optocouplers, Matrix keyboard, Push bu on switches,
Programmable Peripheral Interface Device (e.g. 8255 PPI), etc. with the I/O
subsystem of the embedded system
LO 4 Examine the different communica on interfaces of an embedded system
Understand the various chip level communica on interfaces like I2C, SPI, UART,
1-wire, parallel bus, etc.
Know the different wired and wireless external communica on interfaces like
RS-232C, RS-485, Parallel Port, USB, IEEE 1394, Infrared (IrDA), Bluetooth, Wi-Fi,
ZigBee, GPRS, etc.
LO 5 Describe what embedded firmware is and its role in embedded systems
LO 6 Know the different system components like Reset Circuit, Brown-out protec on circuit,
Oscillator Unit, Real-Time Clock (RTC) and Watchdog Timer unit
LO 7 Discuss the role of PCB in embedded systems
 The Typical Embedded System 17

A typical embedded system (Fig. 2.1) contains a single chip controller, which acts as the master brain of the
system. The controller can be a Microprocessor (e.g. Intel 8085) or a microcontroller (e.g. Atmel AT89C51)
or a Field Programmable Gate Array (FPGA) device (e.g. Xilinx Spartan) or a Digital Signal Processor (DSP)
(e.g. Blackfin® Processors from Analog Devices) or an Application Specific Integrated Circuit (ASIC)/
Application Specific Standard Product (ASSP) (e.g. ADE7760 Single Phase Energy Metreing IC from)
Analog Devices for energy metering applications).

Fig. 2.1 Elements of an embedded system

Embedded hardware/software systems are basically designed to regulate a physical variable or to

manipulate the state of some devices by sending some control signals to the Actuators or devices connected
to the O/p ports of the system, in response to the input signals provided by the end users or Sensors which are
connected to the input ports. Hence an embedded system can be viewed as a reactive system. The control is
achieved by processing the information coming from the sensors and user interfaces, and controlling some
actuators that regulate the physical variable.
Key boards, push button switches, etc. are examples for common user interface input devices whereas
LEDs, liquid crystal displays, piezoelectric buzzers, etc. are examples for common user interface output
devices for a typical embedded system. It should be noted that it is not necessary that all embedded systems
should incorporate these I/O user interfaces. It solely depends on the type of the application for which the
embedded system is designed. For example, if the embedded system is designed for any handheld application,
such as a mobile handset application, then the system should contain user interfaces like a keyboard for
performing input operations and display unit for providing users the status of various activities in progress.
18 Introduc on to Embedded Systems

Some embedded systems do not require any manual intervention for their operation. They automatically
sense the variations in the input parameters in accordance with the changes in the real world, to which
they are interacting through the sensors which are connected to the input port of the system. The sensor
information is passed to the processor after signal conditioning and digitisation. Upon receiving the sensor
data the processor or brain of the embedded system performs some predefined operations with the help of the
firmware embedded in the system and sends some actuating signals to the actuator connected to the output
port of the embedded system, which in turn acts on the controlling variable to bring the controlled variable to
the desired level to make the embedded system work in the desired manner.
The Memory of the system is responsible for holding the control algorithm and other important
configuration details. For most of embedded systems, the memory for storing the algorithm or configuration
data is of fixed type, which is a kind of Read Only Memory (ROM) and it is not available for the end user for
modifications, which means the memory is protected from unwanted user interaction by implementing some
kind of memory protection mechanism. The most common types of memories used in embedded systems for
control algorithm storage are OTP, PROM, UVEPROM, EEPROM and FLASH. Depending on the control
application, the memory size may vary from a few bytes to megabytes. We will discuss them in detail in the
coming sections. Sometimes the system requires temporary memory for performing arithmetic operations
or control algorithm execution and this type of memory is known as “working memory”. Random Access
Memory (RAM) is used in most of the systems as the working memory. Various types of RAM like SRAM,
DRAM, and NVRAM are used for this purpose. The size of the RAM also varies from a few bytes to
kilobytes or megabytes depending on the application. The details given under the section “Memory” will give
you a more detailed description of the working memory.
An embedded system without a control algorithm implemented memory is just like a new born baby. It is
having all the peripherals but is not capable of making any decision depending on the situational as well as
real world changes. The only difference is that the memory of a new born baby is self-adaptive, meaning that
the baby will try to learn from the surroundings and from the mistakes committed. For embedded systems it
is the responsibility of the designer to impart intelligence to the system.
In a controller-based embedded system, the controller may contain internal memory for storing the control
algorithm and it may be an EEPROM or FLASH memory varying from a few kilobytes to megabytes. Such
controllers are called controllers with on-chip ROM, e.g. Atmel AT89C51. Some controllers may not contain
on-chip memory and they require an external (off-chip) memory for holding the control algorithm, e.g. Intel
8031AH.

2.1 CORE OF THE EMBEDDED SYSTEM

Embedded systems are domain and application specific and are built around a LO 1 Identify
central core. The core of the embedded system falls into any one of the following the building
categories: blocks of a typical
(1) General Purpose and Domain Specific Processors Embedded System
1.1 Microprocessors
1.2 Microcontrollers
1.3 Digital Signal Processors
(2) Application Specific Integrated Circuits (ASICs)
(3) Programmable Logic Devices (PLDs)
(4) Commercial off-the-shelf Components (COTS)
If you examine any embedded system you will find that it is built around any of the core units mentioned
above.
 The Typical Embedded System 19

2.1.1 General Purpose and Domain Specific Processors

Almost 80% of the embedded systems are processor/controller based. The processor may be a microprocessor
or a microcontroller or a digital signal processor, depending on the domain and application. Most of the
embedded systems in the industrial control and monitoring applications make use of the commonly available
microprocessors or microcontrollers whereas domains which require signal processing such as speech coding,
speech recognition, etc. make use of special kind of digital signal processors supplied by manufacturers like,
Analog Devices, Texas Instruments, etc.
2.1.1.1 Microprocessors A Microprocessor is a silicon chip representing a central processing unit
(CPU), which is capable of performing arithmetic as well as logical operations according to a pre-defined set
of instructions, which is specific to the manufacturer. In general, the CPU contains the Arithmetic and Logic
Unit (ALU), control unit and working registers. A microprocessor is a dependent unit and it requires the
combination of other hardware like memory, timer unit, and interrupt controller, etc. for proper functioning.
Intel claims the credit for developing the first microprocessor unit Intel 4004, a 4bit processor which was
released in November 1971. It featured 1K data memory, a 12bit program counter and 4K program memory,
sixteen 4bit general purpose registers and 46 instructions. It ran at a clock speed of 740 kHz. It was designed
for olden day’s calculators. In 1972, 14 more instructions were added to the 4004 instruction set and the
program space is upgraded to 8K. Also interrupt capabilities were added to it and it is renamed as Intel 4040.
It was quickly replaced in April 1972 by Intel 8008 which was similar to Intel 4040, the only difference was
that its program counter was 14 bits wide and the 8008 served as a terminal controller. In April 1974 Intel
launched the first 8 bit processor, the Intel 8080, with 16bit address bus and program counter, and seven
8bit registers (A-E,H,L: BC, DE, and HL pairs formed the 16bit register for this processor). Intel 8080 was
the most commonly used processors for industrial control and other embedded applications in the 1975s.
Since the processor required other hardware components as mentioned earlier for its proper functioning, the
systems made out of it were bulky and were lacking compactness.
Immediately after the release of Intel 8080, Motorola also entered the market with their processor,
Motorola 6800 with a different architecture and instruction set compared to 8080.
In 1976 Intel came up with the upgraded version of 8080 – Intel 8085, with two newly added instructions,
three interrupt pins and serial I/O. Clock generator and bus controller circuits were built-in and the power
supply part was modified to a single +5 V supply.
In July 1976 Zilog entered the microprocessor market with its Z80 processor as competitor to Intel.
Actually it was designed by an ex-Intel designer, Frederico Faggin and it was an improved version of Intel’s
8080 processor, maintaining the original 8080 architecture and instruction set with an 8bit data bus and a
16bit address bus and was capable of executing all instructions of 8080. It included 80 more new instructions
and it brought out the concept of register banking by doubling the register set. Z80 also included two sets of
index registers for flexible design.
Technical advances in the field of semiconductor industry brought a new dimension to the microprocessor
market and twentieth century witnessed a fast growth in processor technology. 16, 32 and 64 bit processors came
into the place of conventional 8bit processors. The initial 2 MHz clock is now an old story. Today processors
with clock speeds over 3.0 GHz are available in the market. More and more competitors entered into the
processor market offering high speed, high performance and low cost processors for customer design needs.
Intel, AMD, Freescale, GLOBALFOUNDRIES, TI, Cyrix, NVIDIA, Qualcomm, MediaTek, etc. are
the key players in the processor market. Intel still leads the market with cutting edge technologies in the
processor industry.
Different instruction set and system architecture are available for the design of a microprocessor. Harvard
and Von-Neumann are the two common system architectures for processor design. Processors based on
20 Introduc on to Embedded Systems

Harvard architecture contains separate buses for program memory and data memory, whereas processors
based on Von-Neumann architecture shares a single system bus for program and data memory. We will
discuss more about these architectures later, under a separate topic. Reduced Instruction Set Computing
(RISC) and Complex Instruction Set Computing (CISC) are the two common Instruction Set Architectures
(ISA) available for processor design. We will discuss the same under a separate topic in this section.
2.1.1.2 General Purpose Processor (GPP) vs. Applica on-Specific Instruc on Set Processor (ASIP)
A General Purpose Processor or GPP is a processor designed for general computational tasks. The processor
running inside your laptop or desktop (Pentium 4/AMD Athlon, etc.) is a typical example for general purpose
processor. They are produced in large volumes and targeting the general market. Due to the high volume
production, the per unit cost for a chip is low compared to ASIC or other specific ICs. A typical general
purpose processor contains an Arithmetic and Logic Unit (ALU) and Control Unit (CU). On the other hand,
Application Specific Instruction Set Processors (ASIPs) are processors with architecture and instruction
set optimised to specific-domain/application requirements like network processing, automotive, telecom,
media applications, digital signal processing, control applications, etc. ASIPs fill the architectural spectrum
between general purpose processors and Application Specific Integrated Circuits (ASICs). The need for an
ASIP arises when the traditional general purpose processor are unable to meet the increasing application
needs. Most of the embedded systems are built around application specific instruction set processors. Some
microcontrollers (like Automotive AVR, megaAV from Atmel), system on chips, digital signal processors,
etc. are examples for application specific instruction set processors (ASIPs). ASIPs incorporate a processor
and on-chip peripherals, demanded by the application requirement, program and data memory.
2.1.1.3 Microcontrollers A Microcontroller is a highly integrated chip that contains a CPU, scratch
pad RAM, special and general purpose register arrays, on chip ROM/FLASH memory for program storage,
timer and interrupt control units and dedicated I/O ports. Microcontrollers can be considered as a super set
of microprocessors. Since a microcontroller contains all the necessary functional blocks for independent
working, they found greater place in the embedded domain in place of microprocessors. Apart from this, they
are cheap, cost effective and are readily available in the market.
Texas Instrument’s TMS 1000 is considered as the world’s first microcontroller. We cannot say it as a fully
functional microcontroller when we compare it with modern microcontrollers. TI followed Intel’s 4004/4040,
4 bit processor design and added some amount of RAM, program storage memory (ROM) and I/O support on
a single chip, there by eliminated the requirement of multiple hardware chips for self-functioning. Provision
to add custom instructions to the CPU was another innovative feature of TMS 1000. TMS 1000 was released
in 1974.
In 1977 Intel entered the microcontroller market with a family of controllers coming under one umbrella
named MCS-48TM family. The processors came under this family were 8038HL, 8039HL, 8040AHL, 8048H,
8049H, and 8050AH. Intel 8048 is recognised as Intel’s first microcontroller and it was the most prominent
member in the MCS-48TM* family. It was used in the original IBM PC keyboard. The inspiration behind 8048
was Fairchild’s F8 microprocessor and Intel’s goal of developing a low cost and small size processor. The
design of 8048 adopted a true Harvard architecture where program and data memory shared the same address
bus and is differentiated by the related control signals.
Eventually Intel came out with its most fruitful design in the 8bit microcontroller domain–the 8051 family
and its derivatives. It is the most popular and powerful 8bit microcontroller ever built. It was developed in
the 1980s and was put under the family MCS-51. Almost 75% of the microcontrollers used in the embedded
domain were 8051 family based controllers during the 1980–90s. 8051 processor cores are used in more than

*
MCS-48TM is a trade mark owned by Intel
 The Typical Embedded System 21

100 devices by more than 20 independent manufacturers like Maxim, NXP, Atmel, etc. under the license
from Intel. Due to the low cost, wide availability, memory efficient instruction set, mature development tools
and Boolean processing (bit manipulation operation) capability, 8051 family derivative microcontrollers are
much used in high-volume consumer electronic devices, entertainment industry and other gadgets where
cost-cutting is essential.
Another important family of microcontrollers used in industrial control and embedded applications is the
PIC family micro controllers from Microchip Technologies (It will be discussed in detail in a later section of
this book). It is a high performance RISC microcontroller complementing the CISC (Complex Instruction Set
Computing) features of 8051. The terms RISC and CISC will be explained in detail in a separate heading.
Some embedded system applications require only 8bit controllers whereas some embedded applications
requiring superior performance and computational needs demand 16/32bit microcontrollers. Infineon,
Freescale, Philips, Atmel, Maxim, Microchip etc. are the key suppliers of 16bit microcontrollers. Philips
tried to extend the 8051 family microcontrollers to use for 16bit applications by developing the Philips XA
(eXtended Architecture) microcontroller series.
8bit microcontrollers are commonly used in embedded systems where the processing power is not a big
constraint. As mentioned earlier, more than 20 companies are producing different flavours of the 8051 family
microcontroller. They try to add more and more functionalities like built in SPI, I2C serial buses, USB
controller, ADC, Networking capability, etc. So the competitive market is driving towards a one-stop solution
chip in microcontroller domain. High processing speed microcontroller families like ARM Cortex M Series
are also available in the market, which provides solution to applications requiring hardware acceleration and
high processing capability.
Freescale, Renesas, Zilog, Cypress (Spansion), Infineon, ST Micro Electronics, EPSON, Texas Instruments,
Toshiba, NXP, Microchip, Analog Devices, Daewoo, Intel, Maxim, Sharp, Silicon Laboratories, HOLTEK,
LAPIS, CYROD, Atmel, etc. are the key players in the microcontroller market. Of these Atmel has got
special significance. They are the manufacturers of a variety of Flash memory based microcontrollers. They
also provide In-System Programmability (which will be discussed in detail in a later section of this book) for
the controller. The Flash memory technique helps in fast reprogramming of the chip and thereby reduces the
product development time. Atmel also provides another special family of microcontroller called AVR (it will
be discussed in detail in a later chapter), an 8bit RISC Flash microcontroller, fast enough to execute powerful
instructions in a single clock cycle and provide the latitude you need to optimise power consumption.
The instruction set architecture of a microcontroller can be either RISC or CISC. Microcontrollers are
designed for either general purpose application requirement (general purpose controller) or domain- specific
application requirement (application specific instruction set processor). The Intel 8051 microcontroller is a
typical example for a general purpose microcontroller, whereas the automotive AVR microcontroller family
from Atmel Corporation is a typical example for ASIP specifically designed for the automotive domain.
2.1.1.4 Microprocessor vs Microcontroller The following table summarises the differences between
a microcontroller and microprocessor.

Microprocessor Microcontroller
A silicon chip representing a central processing unit (CPU), A microcontroller is a highly integrated chip that contains a
which is capable of performing arithmetic as well as logical CPU, scratchpad RAM, special and general purpose register
operations according to a predefined set of instructions arrays, on chip ROM/FLASH memory for program storage,
timer and interrupt control units and dedicated I/O ports
(Contd.)
22 Introduc on to Embedded Systems

Microprocessor Microcontroller
It is a dependent unit. It requires the combination of other It is a self-contained unit and it doesn’t require external
chips like timers, program and data memory chips, interrupt interrupt controller, timer, UART, etc. for its functioning
controllers, etc. for functioning
Most of the time general purpose in design and operation Mostly application-oriented or domain-specific
Doesn’t contain a built in I/O port. The I/O port functionality Most of the processors contain multiple built-in I/O ports
needs to be implemented with the help of external program- which can be operated as a single 8 or 16 or 32 bit port or
mable peripheral interface chips like 8255 as individual port pins
Targeted for high end market where performance is im- Targeted for embedded market where performance is not so
portant critical (At present this demarcation is invalid)
Limited power saving options compared to microcon- Includes lot of power saving features
trollers

2.1.1.5 Digital Signal Processors Digital Signal Processors (DSPs) are powerful special purpose
8/16/32 bit microprocessors designed specifically to meet the computational demands and power constraints
of today’s embedded audio, video, and communications applications. Digital signal processors are 2 to 3
times faster than the general purpose microprocessors in signal processing applications. This is because
of the architectural difference between the two. DSPs implement algorithms in hardware which speeds up
the execution whereas general purpose processors implement the algorithm in firmware and the speed of
execution depends primarily on the clock for the processors. In general, DSP can be viewed as a microchip
designed for performing high speed computational operations for ‘addition’, ‘subtraction’, ‘multiplication’
and ‘division’. A typical digital signal processor incorporates the following key units:
Program Memory Memory for storing the program required by DSP to process the data.
Data Memory Working memory for storing temporary variables and data/signal to be processed.
Computa onal Engine Performs the signal processing in accordance with the stored program memory.
Computational Engine incorporates many specialised arithmetic units and each of them operates simultaneously
to increase the execution speed. It also incorporates multiple hardware shifters for shifting operands and
thereby saves execution time.
I/O Unit Acts as an interface between the outside world and DSP. It is responsible for capturing signals to
be processed and delivering the processed signals.
Audio video signal processing, telecommunication, and multimedia applications are typical examples
where DSP is employed. Digital signal processing employs a large amount of real-time calculations. Sum of
products (SOP) calculation, convolution, fast fourier transform (FFT), discrete fourier transform (DFT), etc,
are some of the operations performed by digital signal processors.
Blackfin®† processors from Analog Devices is an example of DSP which delivers breakthrough signal-
processing performance and power efficiency while also offering a full 32-bit RISC MCU programming
model. Blackfin processors present high-performance, homogeneous software targets, which allows flexible
resource allocation between hard real-time signal processing tasks and non real-time control tasks. System
control tasks can often run in the shadow of demanding signal processing and multimedia tasks.
2.1.1.6 RISC vs. CISC Processors/Controllers The term RISC stands for Reduced Instruction Set
Computing. As the name implies, all RISC processors/controllers possess lesser number of instructions,
†
Blackfin® is a Registered trademark of Analog Devices Inc.
 The Typical Embedded System 23

typically in the range of 30 to 40. CISC stands for Complex Instruction Set Computing. From the definition
itself it is clear that the instruction set is complex and instructions are high in number. From a programmers
point of view RISC processors are comfortable since s/he needs to learn only a few instructions, whereas for
a CISC processor s/he needs to learn more number of instructions and should understand the context of usage
of each instruction (This scenario is explained on the basis of a programmer following Assembly Language
coding. For a programmer following C coding it doesn’t matter since the cross-compiler is responsible for the
conversion of the high level language instructions to machine dependent code). Atmel AVR microcontroller
is an example for a RISC processor and its instruction set contains only 32 instructions. The original version
of 8051 microcontroller (e.g. AT89C51) is a CISC controller and its instruction set contains 255 instructions.
Remember it is not the number of instructions that determines whether a processor/controller is CISC or
RISC. There are some other factors like pipelining features, instruction set type, etc. for determining the
RISC/CISC criteria. Some of the important criteria are listed below:

RISC CISC
Lesser number of instructions Greater number of Instructions
Instruction pipelining and increased execution speed Generally no instruction pipelining feature
Orthogonal instruction set (Allows each instruction to oper- Non-orthogonal instruction set (All instructions are not
ate on any register and use any addressing mode) allowed to operate on any register and use any addressing
mode. It is instruction-specific)
Operations are performed on registers only, the only Operations are performed on registers or memory depend-
memory operations are load and store ing on the instruction
A large number of registers are available Limited number of general purpose registers
Programmer needs to write more code to execute a task Instructions are like macros in C language. A programmer
since the instructions are simpler ones can achieve the desired functionality with a single instruc-
tion which in turn provides the effect of using more simpler
single instructions in RISC
Single, fixed length instructions Variable length instructions
Less silicon usage and pin count More silicon usage since more additional decoder logic is
required to implement the complex instruction decoding.
With Harvard Architecture Can be Harvard or Von-Neumann Architecture

I hope now you are clear about the terms RISC and CISC in the processor technology. Isn’t it?
2.1.1.7 Harvard vs. Von-Neumann Processor/Controller Architecture The terms Harvard and
Von-Neumann refers to the processor architecture design.
Microprocessors/controllers based on the Von-Neumann architecture shares a single common bus for
fetching both instructions and data. Program instructions and data are stored in a common main memory.
Von-Neumann architecture based processors/controllers first fetch an instruction and then fetch the data to
support the instruction from code memory. The two separate fetches slows down the controller’s operation.
Von-Neumann architecture is also referred as Princeton architecture, since it was developed by the Princeton
University.
Microprocessors/controllers based on the Harvard architecture will have separate data bus and instruction
bus. This allows the data transfer and program fetching to occur simultaneously on both buses. With Harvard
architecture, the data memory can be read and written while the program memory is being accessed. These
separated data memory and code memory buses allow one instruction to execute while the next instruction
is fetched (“prefetching”). The prefetch theoretically allows much faster execution than Von-Neumann
24 Introduc on to Embedded Systems

architecture. Since some additional hardware logic is required for the generation of control signals for this
type of operation it adds silicon complexity to the system. Figure 2.2 explains the Harvard and Von-Neumann
architecture concept.

Fig. 2.2 Harvard vs Von-Neumann architecture

The following table highlights the differences between Harvard and Von-Neumann architecture.

Harvard Architecture Von-Neumann Architecture

Separate buses for instruction and data fetching Single shared bus for instruction and data fetching
Easier to pipeline, so high performance can be achieved Low performance compared to Harvard architecture
Comparatively high cost Cheaper
No memory alignment problems Allows self modifying codes*
Since data memory and program memory are stored Since data memory and program memory are stored
physically in different locations, no chances for accidental physically in the same chip, chances for accidental
corruption of program memory corruption of program memory

2.1.1.8 Big-Endian vs. Li le-Endian Processors/Controllers Endianness specifies the order in which
the data is stored in the memory by processor operations in a multibyte system (Processors whose word size
is greater than one byte). Suppose the word length is two byte then data can be stored in memory in two
different ways:
(1) Higher order of data byte at the higher memory and lower order of data byte at location just below the
higher memory.
(2) Lower order of data byte at the higher memory and higher order of data byte at location just below the
higher memory.
Li le-endian Little-endian (Fig. 2.3) means the lower-order byte of the data is stored in memory at the
lowest address, and the higher-order byte at the highest address. (The little end comes first.) For example, a 4
byte long integer Byte3 Byte2 Byte1 Byte0 will be stored in the memory as shown below:

Fig. 2.3 Little-Endian operation

*
Self-modifying code is a code/instruction which modifies itself while execution.
 The Typical Embedded System 25

Big-endian Big-endian (Fig. 2.4) means the higher-order byte of the data is stored in memory at the lowest
address, and the lower-order byte at the highest address. (The big end comes first.) For example, a 4 byte long
integer Byte3 Byte2 Byte1 Byte0 will be stored in the memory as follows‡:

Fig. 2.4 Big-Endian operation

2.1.1.9 Load Store Opera on and Instruc on Pipelining As mentioned earlier, the RISC processor
instruction set is orthogonal, meaning it operates on registers. The memory access related operations are
performed by the special instructions load and store. If the operand is specified as memory location, the
content of it is loaded to a register using the load instruction. The instruction store stores data from a specified
register to a specified memory location. The concept of Load Store Architecture is illustrated with the
following example:
Suppose x, y and z are memory locations and we want to add the contents of x and y and store the result in
location z. Under the load store architecture the same is achieved with 4 instructions as shown in Fig. 2.5.

Fig. 2.5 The concept of load store architecture

The first instruction load R1, x loads the register R1 with the content of memory location x, the second
instruction load R2,y loads the register R2 with the content of memory location y. The instruction add R3,
R1, R2 adds the content of registers R1 and R2 and stores the result in register R3. The next instruction store
R3,z stores the content of register R3 in memory location z.
The conventional instruction execution by the processor follows the fetch-decode-execute sequence.
Where the ‘fetch’ part fetches the instruction from program memory or code memory and the decode part
decodes the instruction to generate the necessary control signals. The execute stage reads the operands,

‡ Note that the base address is chosen arbitrarily as 0×20000

26 Introduc on to Embedded Systems

perform ALU operations and stores the result. In conventional program execution, the fetch and decode
operations are performed in sequence. For simplicity let’s consider decode and execution together. During
the decode operation the memory address bus is available and if it is possible to effectively utilise it for an
instruction fetch, the processing speed can be increased. In its simplest form instruction pipelining refers to
the overlapped execution of instructions. Under normal program execution flow it is meaningful to fetch the
next instruction to execute, while the decoding and execution of the current instruction is in progress. If the
current instruction in progress is a program control flow transfer instruction like jump or call instruction,
there is no meaning in fetching the instruction following the current instruction. In such cases the instruction
fetched is flushed and a new instruction fetch is performed to fetch the instruction. Whenever the current
instruction is executing the program counter will be loaded with the address of the next instruction. In case of
jump or branch instruction, the new location is known only after completion of the jump or branch instruction.
Depending on the stages involved in an instruction (fetch, read register and decode, execute instruction,
access an operand in data memory, write back the result to register, etc.), there can be multiple levels of
instruction pipelining. Figure 2.6 illustrates the concept of Instruction pipelining for single stage pipelining.

Fig. 2.6 The single-stage pipelining concept

2.1.2 Application Specific Integrated Circuits (ASICs)

Application Specific Integrated Circuit (ASIC) is a microchip designed to perform a specific or unique
application. It is used as replacement to conventional general purpose logic chips. It integrates several
functions into a single chip and there by reduces the system development cost. Most of the ASICs are
proprietary products. As a single chip, ASIC consumes a very small area in the total system and thereby helps
in the design of smaller systems with high capabilities/functionalities.
ASICs can be pre-fabricated for a special application or it can be custom fabricated by using the components
from a re-usable ‘building block’ library of components for a particular customer application. ASIC based
systems are profitable only for large volume commercial productions. Fabrication of ASICs requires a non-
refundable initial investment for the process technology and configuration expenses. This investment is
known as Non-Recurring Engineering Charge (NRE) and it is a one time investment.
If the Non-Recurring Engineering Charges (NRE) is borne by a third party and the Application Specific
Integrated Circuit (ASIC) is made openly available in the market, the ASIC is referred as Application Specific
Standard Product (ASSP). The ASSP is marketed to multiple customers just as a general-purpose product
is, but to a smaller number of customers since it is for a specific application. “The ADE7760 Energy Metre
ASIC developed by Analog Devices for Energy metreing applications is a typical example for ASSP”.
Since Application Specific Integrated Circuits (ASICs) are proprietary products, the developers of such
chips may not be interested in revealing the internal details of it and hence it is very difficult to point out
an example of it. Moreover it will create legal disputes if an illustration of such an ASIC product is given
without getting prior permission from the manufacturer of the ASIC. For the time being, let us park the
discussion about it aside. We will come back to it in another part of this book series.
 The Typical Embedded System 27

2.1.3 Programmable Logic Devices

Logic devices provide specific functions, including device-to-device interfacing, data communication, signal
processing, data display, timing and control operations, and almost every other function a system must
perform. Logic devices can be classified into two broad categories–fixed and programmable. As the name
indicates, the circuits in a fixed logic device are permanent, they perform one function or set of functions–
once manufactured, they cannot be changed. On the other hand, Programmable Logic Devices (PLDs) offer
customers a wide range of logic capacity, features, speed, and voltage characteristics–and these devices can
be re-configured to perform any number of functions at any time.
With programmable logic devices, designers use inexpensive software tools to quickly develop, simulate,
and test their designs. Then, a design can be quickly programmed into a device, and immediately tested in
a live circuit. The PLD that is used for this prototyping is the exact same PLD that will be used in the final
production of a piece of end equipment, such as a network router, a DSL modem, a DVD player, or an
automotive navigation system. There are no NRE costs and the final design is completed much faster than that
of a custom, fixed logic device. Another key benefit of using PLDs is that during the design phase customers
can change the circuitry as often as they want until the design operates to their satisfaction. That’s because
PLDs are based on re-writable memory technology–to change the design, the device is simply reprogrammed.
Once the design is final, customers can go into immediate production by simply programming as many PLDs
as they need with the final software design file.
2.1.3.1 CPLDs and FPGAs The two major types of programmable logic devices are Field Programmable
Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). Of the two, FPGAs offer the
highest amount of logic density, the most features, and the highest performance. The largest FPGA now
shipping, part of the Xilinx Virtex™§ line of devices, provides eight million “system gates” (the relative
density of logic). These advanced devices also offer features such as built-in hardwired processors (such as
the IBM power PC), substantial amounts of memory, clock management systems, and support for many of
the latest, very fast device-to-device signaling technologies. FPGAs are used in a wide variety of applications
ranging from data processing and storage, to instrumentation, telecommunications, and digital signal
processing.
CPLDs, by contrast, offer much smaller amounts of logic–up to about 10,000 gates. But CPLDs offer
very predictable timing characteristics and are therefore ideal for critical control applications. CPLDs such
as the Xilinx CoolRunner™† series also require extremely low amounts of power and are very inexpensive,
making them ideal for cost-sensitive, battery-operated, portable applications such as mobile phones and
digital handheld assistants.
Advantages of PLD Programmable logic devices offer a number of important advantages over fixed logic
devices, including the following:
(1) PLDs offer customers much more flexibility during the design cycle because design iterations are
simply a matter of changing the programming file, and the results of design changes can be seen
immediately in working parts.
(2) PLDs do not require long lead times for prototypes or production parts–the PLDs are already on a
distributor’s shelf and ready for shipment.
(3) PLDs do not require customers to pay for large NRE costs and purchase expensive mask sets–PLD
suppliers incur those costs when they design their programmable devices and are able to amortize those
costs over the multi-year lifespan of a given line of PLDs.
(4) PLDs allow customers to order just the number of parts they need, when they need them, allowing them
to control inventory. Customers who use fixed logic devices often end up with excess inventory which
§ Virtex™ and CoolRunner™ are the registered trademarks of Xilinx Inc.
28 Introduc on to Embedded Systems

must be scrapped, or if demand for their product surges, they may be caught short of parts and face
production delays.
(5) PLDs can be reprogrammed even after a piece of equipment is shipped to a customer. In fact, thanks
to programmable logic devices, a number of equipment manufacturers now tout the ability to add
new features or upgrade products that already are in the field. To do this, they simply upload a new
programming file to the PLD, via the Internet, creating new hardware logic in the system.
Over the last few years programmable logic suppliers have made such phenomenal technical advances
that PLDs are now seen as the logic solution of choice from many designers. One reason for this is that PLD
suppliers such as Xilinx are “fabless” companies; instead of owning chip manufacturing foundries, Xilinx
outsource that job to partners like Toshiba and UMC, whose chief occupation is making chips. This strategy
allows Xilinx to focus on designing new product architectures, software tools, and intellectual property
cores while having access to the most advanced semiconductor process technologies. Advanced process
technologies help PLDs in a number of key areas: faster performance, integration of more features, reduced
power consumption, and lower cost.
FPGAs are especially popular for prototyping ASIC designs where the designer can test his design by
downloading the design file into an FPGA device. Once the design is set, hardwired chips are produced for
faster performance.
Just a few years ago, for example, the largest FPGA was measured in tens of thousands of system gates
and operated at 40 MHz. Older FPGAs also were relatively expensive, costing often more than $150 for the
most advanced parts at the time. Today, however, FPGAs with advanced features offer millions of gates of
logic capacity, operate at 300 MHz, can cost less than $10, and offer a new level of integrated functions such
as processors and memory.

2.1.4 Commercial Off-the-Shelf Components (COTS)

A Commercial Off-the-Shelf (COTS) product is one which is used ‘as-is’. COTS products are designed in
such a way to provide easy integration and interoperability with existing system components. The COTS
component itself may be developed around a general purpose or domain specific processor or an Application
Specific Integrated circuit or a programmable logic device. Typical examples of COTS hardware unit are
remote controlled toy car control units including the RF circuitry part, high performance, high frequency
microwave electronics (2–200 GHz), high bandwidth analog-to-digital converters, devices and components
for operation at very high temperatures, electro-optic IR imaging arrays, UV/IR detectors, etc. The major
advantage of using COTS is that they are readily available in the market, are cheap and a developer can cut
down his/her development time to a great extent. This in
turn reduces the time to market your embedded systems.
The TCP/IP plug-in module available from various
manufactures like ‘WIZnet’, ‘HanRun’, ‘Viewtool’, etc.
are very good examples of COTS product (Fig. 2.7). This
network plug-in module gives the TCP/IP connectivity to
the system you are developing. There is no need to design
this module yourself and write the firmware for the TCP/
IP protocol and data transfer. Everything will be readily
supplied by the COTS manufacturer. What you need to do
is identify the COTS for your system and give the plug-
in option on your board according to the hardware plug- Fig. 2.7 An example of a COTS product for TCP/IP
in connections given in the specifications of the COTS. plug-in from WIZnet
(WIZnet Network Plug in Module-Courtesy of
Though multiple vendors supply COTS for the same WIZnet h p://www.wiznet.co.kr/en/)
 The Typical Embedded System 29

application, the major problem faced by the end-user is that there are no operational and manufacturing
standards. A Commercial Off-The-Shelf (COTS) component manufactured by a vendor need not have
hardware plug-in and firmware interface compatibility with one manufactured by a second vendor for the
same application. This restricts the end-user to stick to a particular vendor for a particular COTS. This greatly
affects the product design.
The major drawback of using COTS components in embedded design is that the manufacturer of the
COTS component may withdraw the product or discontinue the production of the COTS at any time if a
rapid change in technology occurs, and this will adversely affect a commercial manufacturer of the embedded
system which makes use of the specific COTS product.

2.2 MEMORY
Memory is an important part of a processor/controller based embedded systems.
LO 2 Explain
Some of the processors/controllers contain built in memory and this memory is
different memory
referred as on-chip memory. Others do not contain any memory inside the chip
technologies and
and requires external memory to be connected with the controller/processor to
memory types used
store the control algorithm. It is called off-chip memory. Also some working
in embedded system
memory is required for holding data temporarily during certain operations. This
development
section deals with the different types of memory used in embedded system
applications.

2.2.1 Program Storage Memory (ROM)

The program memory or code storage memory of an embedded system stores the program instructions and it
can be classified into different types as per the block diagram representation given in Fig. 2.8.

Fig. 2.8 Classification of Program Memory (ROM)

The code memory retains its contents even after the power to it is turned off. It is generally known as
non-volatile storage memory. Depending on the fabrication, erasing, and programming techniques they are
classified into the following types.
2.2.1.1 Masked ROM (MROM) Masked ROM is a one-time programmable device. Masked ROM
makes use of the hardwired technology for storing data. The device is factory programmed by masking and
metallisation process at the time of production itself, according to the data provided by the end user. The
primary advantage of this is low cost for high volume production. They are the least expensive type of solid
state memory. Different mechanisms are used for the masking process of the ROM, like
30 Introduc on to Embedded Systems

(1) Creation of an enhancement or depletion mode transistor through channel implant.

(2) By creating the memory cell either using a standard transistor or a high threshold transistor. In the high
threshold mode, the supply voltage required to turn ON the transistor is above the normal ROM IC
operating voltage. This ensures that the transistor is always off and the memory cell stores always logic 0.
Masked ROM is a good candidate for storing the embedded firmware for low cost embedded devices.
Once the design is proven and the firmware requirements are tested and frozen, the binary data (The firmware
cross compiled/assembled to target processor specific machine code) corresponding to it can be given to the
MROM fabricator. The limitation with MROM based firmware storage is the inability to modify the device
firmware against firmware upgrades. Since the MROM is permanent in bit storage, it is not possible to alter
the bit information.
2.2.1.2 Programmable Read Only Memory (PROM) / (OTP) Unlike Masked ROM Memory, One
Time Programmable Memory (OTP) or PROM is not pre-programmed by the manufacturer. The end user
is responsible for programming these devices. This memory has nichrome or polysilicon wires arranged
in a matrix. These wires can be functionally viewed as fuses. It is programmed by a PROM programmer
which selectively burns the fuses according to the bit pattern to be stored. Fuses which are not blown/burned
represents a logic “1” whereas fuses which are blown/burned represents a logic “0”. The default state is
logic “1”. OTP is widely used for commercial production of embedded systems whose proto-typed versions
are proven and the code is finalised. It is a low cost solution for commercial production. OTPs cannot be
reprogrammed.
2.2.1.3 Erasable Programmable Read Only Memory (EPROM) OTPs are not useful and worth for
development purpose. During the development phase, the code is subject to continuous changes and using an
OTP each time to load the code is not economical. Erasable Programmable Read Only Memory (EPROM)
gives the flexibility to re-program the same chip. EPROM stores the bit information by charging the floating
gate of an FET. Bit information is stored by using an EPROM programmer, which applies high voltage to
charge the floating gate. EPROM contains a quartz crystal window for erasing the stored information. If the
window is exposed to ultraviolet rays for a fixed duration, the entire memory will be erased. Even though the
EPROM chip is flexible in terms of re-programmability, it needs to be taken out of the circuit board and put
in a UV eraser device for 20 to 30 minutes. So it is a tedious and time-consuming process.
2.2.1.4 Electrically Erasable Programmable Read Only Memory (EEPROM) As the name indicates,
the information contained in the EEPROM memory can be altered by using electrical signals at the register/
Byte level. They can be erased and reprogrammed in-circuit. These chips include a chip erase mode and in
this mode they can be erased in a few milliseconds. It provides greater flexibility for system design. The only
limitation is their capacity is limited when compared with the standard ROM (A few kilobytes).
2.2.1.5 FLASH FLASH is the latest ROM technology and is the most popular ROM technology used
in today’s embedded designs. FLASH memory is a variation of EEPROM technology. It combines the re-
programmability of EEPROM and the high capacity of standard ROMs. FLASH memory is organised as
sectors (blocks) or pages. FLASH memory stores information in an array of floating gate MOSFET transistors.
The erasing of memory can be done at sector level or page level without affecting the other sectors or pages.
Each sector/page should be erased before re-programming. The typical erasable capacity of FLASH is of the
order of a few 1000 cycles. SST39LF010 from Microchip (www.microchip.com) is an example of 1Mbit
(Organised as 128K x8) Flash memory with typical endurance of 100,000 cycles.
2.2.1.6 NVRAM Non-volatile RAM is a random access memory with battery backup. It contains static
RAM based memory and a minute battery for providing supply to the memory in the absence of external
 The Typical Embedded System 31

power supply. The memory and battery are packed together in a single package. The life span of NVRAM is
expected to be around 10 years. DS1644 from Maxim/Dallas is an example of 32KB NVRAM.

2.2.2 Read-Write Memory/Random Access Memory (RAM)

RAM is the data memory or working memory of the controller/processor. Controller/processor can read from
it and write to it. RAM is volatile, meaning when the power is turned off, all the contents are destroyed. RAM
is a direct access memory, meaning we can access the desired memory location directly without the need for
traversing through the entire memory locations to reach the desired memory position (i.e. random access of
memory location). This is in contrast to the Sequential Access Memory (SAM), where the desired memory
location is accessed by either traversing through the entire memory or through a ‘seek’ method. Magnetic
tapes, CD ROMs, etc. are examples of sequential access memories. RAM generally falls into three categories:
Static RAM (SRAM), dynamic RAM (DRAM), and non-volatile RAM (NVRAM) (Fig. 2.9).

Read/Write
Memory (RAM)

SRAM DRAM NVRAM

Fig. 2.9 Classification of Working Memory (RAM)

2.2.2.1 Sta c RAM (SRAM) Static RAM stores data in the form of voltage. They are made up of flip-
flops. Static RAM is the fastest form of RAM available. In typical implementation, an SRAM cell (bit) is
realised using six transistors (or 6 MOSFETs). Four of the transistors are used for building the latch (flip-
flop) part of the memory cell and two for controlling the access. SRAM is fast in operation due to its resistive
networking and switching capabilities. In its simplest representation an SRAM cell can be visualised as
shown in Fig. 2.10.

Bit Line B\ Bit Line B

Q1 Q3

Q5 Q6

Q2 Q4
Vcc

Word Line

Fig. 2.10 SRAM cell implementation

32 Introduc on to Embedded Systems

This implementation in its simpler form can be visualised as two-cross coupled inverters with read/write
control through transistors. The four transistors in the middle form the cross-coupled inverters. This can be
visualised as shown in Fig. 2.11.
From the SRAM implementation diagram, it is Write control Read control
clear that access to the memory cell is controlled
by the line Word Line, which controls the access
transistors (MOSFETs) Q5 and Q6. The access Data to Data
transistors control the connection to bit lines B & B\. write read
In order to write a value to the memory cell, apply the
desired value to the bit control lines (For writing 1,
make B = 1 and B\ =0; For writing 0, make B = 0 and Fig. 2.11 Visualisation of SRAM cell
B\ =1) and assert the Word Line (Make Word line
high). This operation latches the bit written in the flip-flop. For reading the content of the memory cell, assert
both B and B\ bit lines to 1 and set the Word line to 1.
The major limitations of SRAM are low capacity and high cost. Since a minimum of six transistors
are required to build a single memory cell, imagine how many memory cells we can fabricate on a silicon
wafer.
2.2.2.2 Dynamic RAM (DRAM) Dynamic RAM stores data in the Bit line B
form of charge. They are made up of MOS transistor gates. The advantages
of DRAM are its high density and low cost compared to SRAM. The
disadvantage is that since the information is stored as charge it gets leaked
off with time and to prevent this they need to be refreshed periodically. Word line
Special circuits called DRAM controllers are used for the refreshing
operation. The refresh operation is done periodically in milliseconds +
interval. Figure 2.12 illustrates the typical implementation of a DRAM –
cell.
The MOSFET acts as the gate for the incoming and outgoing data
whereas the capacitor acts as the bit storage unit. Table given below Fig. 2.12 DRAM cell implementation
summarises the relative merits and demerits of SRAM and DRAM
technology.

SRAM cell DRAM cell

Made up of 6 CMOS transistors (MOSFET) Made up of a MOSFET and a capacitor
Doesn’t require refreshing Requires refreshing
Low capacity (Less dense) High capacity (Highly dense)
More expensive Less expensive
Fast in operation. Typical access time is 10ns Slow in operation due to refresh requirements. Typical access
time is 60ns. Write operation is faster than read operation.

2.2.2.3 NVRAM Non-volatile RAM is a random access memory with battery backup. It contains static
RAM based memory and a minute battery for providing supply to the memory in the absence of external
power supply. The memory and battery are packed together in a single package. NVRAM is used for the non-
volatile storage of results of operations or for setting up of flags, etc. The life span of NVRAM is expected to
be around 10 years. DS1744 from Maxim/Dallas is an example for 32KB NVRAM.
 The Typical Embedded System 33

2.2.3 Memory According to the Type of Interface

The interface (connection) of memory with the processor/controller can be of various types. It may be a
parallel interface [The parallel data lines (D0-D7) for an 8 bit processor/controller will be connected to
D0-D7 of the memory] or the interface may be a serial interface like I2C (Pronounced as I Square C. It is a
2 line serial interface) or it may be an SPI (Serial peripheral interface, 2+n line interface where n stands for
the total number of SPI bus devices in the system). It can also be of a single wire interconnection (like Dallas
1-Wire interface). Serial interface is commonly used for data storage memory like EEPROM. The memory
density of a serial memory is usually expressed in terms of kilobits, whereas that of a parallel interface
memory is expressed in terms of kilobytes. Atmel Corporations AT24C512 is an example for serial memory
with capacity 512 kilobits and 2-wire interface. Please refer to the section ‘Communication Interface’ for
more details on I2C, SPI, and 1-Wire Bus.

2.2.4 Memory Shadowing

Generally the execution of a program or a configuration from a Read Only Memory (ROM) is very slow
(120 to 200 ns) compared to the execution from a random access memory (40 to 70 ns). From the timing
parameters it is obvious that RAM access is about three times as fast as ROM access. Shadowing of memory
is a technique adopted to solve the execution speed problem in processor-based systems. In computer systems
and video systems there will be a configuration holding ROM called Basic Input Output Configuration ROM
or simply BIOS. In personal computer systems BIOS stores the hardware configuration information like the
address assigned for various serial ports and other non-plug ‘n’ play devices, etc. Usually it is read and the
system is configured according to it during system boot up and it is time consuming. Now the manufactures
included a RAM behind the logical layer of BIOS at its same address as a shadow to the BIOS and the first
step that happens during the boot up is copying the BIOS to the shadowed RAM and write protecting the
RAM then disabling the BIOS reading. You may be thinking that what a stupid idea it is and why both
RAM and ROM are needed for holding the same data. The answer is: RAM is volatile and it cannot hold the
configuration data which is copied from the BIOS when the power supply is switched off. Only a ROM can
hold it permanently. But for high system performance it should be accessed from a RAM instead of accessing
from a ROM.

2.2.5 Memory Selection for Embedded Systems

Embedded systems require a program memory for holding the control algorithm (For a super-loop based
design) or embedded OS and the applications designed to run on top of it (for OS based designs), data memory
for holding variables and temporary data during task execution, and memory for holding non-volatile data
(like configuration data, look up table etc) which are modifiable by the application (Unlike program memory,
which is non-volatile as well unalterable by the end user). The memory requirement for an embedded system
in terms of RAM and ROM (EEPROM/FLASH/NVRAM) is solely dependent on the type of the embedded
system and the applications for which it is designed. There is no hard and fast rule for calculating the memory
requirements. Lot of factors need to be considered when selecting the type and size of memory for embedded
system. For example, if the embedded system is designed using SoC or a microcontroller with on-chip RAM
and ROM (FLASH/EEPROM), depending on the application need the on-chip memory may be sufficient for
designing the total system. As a rule of thumb, identify your system requirement and based on the type of
processor (SoC or microcontroller with on-chip memory) used for the design, take a decision on whether the
on-chip memory is sufficient or external memory is required. Let’s consider a simple electronic toy design
as an example. As the complexity of requirements are less and data memory requirement are minimal, we
can think of a microcontroller with a few bytes of internal RAM, a few bytes or kilobytes (depending on the
number of tasks and the complexity of tasks) of FLASH memory and a few bytes of EEPROM (if required)
34 Introduc on to Embedded Systems

for designing the system. Hence there is no need for external memory at all. A PIC microcontroller device
which satisfies the I/O and memory requirements can be used in this case. If the embedded design is based on
an RTOS, the RTOS requires certain amount of RAM for its execution and ROM for storing the RTOS image
(Image is the common name given for the binary data generated by the compilation of all RTOS source files).
Normally the binary code for RTOS kernel containing all the services is stored in a non-volatile memory
(Like FLASH) as either compressed or non-compressed data. During boot-up of the device, the RTOS files
are copied from the program storage memory, decompressed if required and then loaded to the RAM for
execution. The supplier of the RTOS usually gives a rough estimate on the run time RAM requirements and
program memory requirements for the RTOS. On top of this add the RAM requirements for executing user
tasks and ROM for storing user applications. On a safer side, always add a buffer value to the total estimated
RAM and ROM size requirements. A smart phone device with Windows mobile operating system is a typical
example for embedded device with OS. Say 512MB RAM and 1GB ROM are the minimum requirements for
running the Windows mobile device, indeed you need extra RAM and ROM for running user applications.
So while building the system, count the memory for that also and arrive at a value which is always at the
safer side, so that you won’t end up in a situation where you don’t have sufficient memory to install and
run user applications. There are two parameters for representing a memory. The first one is the size of the
memory chip (Memory density expressed in terms of number of memory bytes per chip). There is no option
to get a memory chip with the exact required number of bytes. Memory chips come in standard sizes like
512bytes, 1024bytes (1 kilobyte), 2048bytes (2 kilobytes), 4Kb,¶ 8Kb, 16Kb, 32Kb, 64Kb, 128Kb, 256Kb,
512Kb, 1024Kb (1 megabytes), etc. Suppose your embedded application requires only 750 bytes of RAM,
you don’t have the option of getting a memory chip with size 750 bytes, the only option left with is to choose
the memory chip with a size closer to the size needed. Here 1024 bytes is the least possible option. We cannot
go for 512 bytes, because the minimum requirement is 750 bytes. While you select a memory size, always
keep in mind the address range supported by your processor. For example, for a processor/controller with
16 bit address bus, the maximum number of memory locations that can be addressed is 216 = 65536 bytes =
64Kb. Hence it is meaningless to select a 128Kb memory chip for a processor with 16bit wide address bus.
Also, the entire memory range supported by the processor/controller may not be available to the memory
chip alone. It may be shared between I/O, other ICs and memory. Suppose the address bus is 16bit wide and
only the lower 32Kb address range is assigned to the memory chip, the memory size maximum required is
32Kb only. It is not worth to use a memory chip with size 64Kb in such a situation. The second parameter
that needs to be considered in selecting a memory is the word size of the memory. The word size refers to the
number of memory bits that can be read/write together at a time. 4, 8, 12, 16, 24, 32, etc. are the word sizes
supported by memory chips. Ensure that the word size supported by the memory chip matches with the data
bus width of the processor/controller.
FLASH memory is the popular choice for ROM (Program Storage Memory) in embedded applications.
It is a powerful and cost-effective solid-state storage technology for mobile electronics devices and other
consumer applications. FLASH memory comes in two major variants, namely, NAND and NOR FLASH.
NAND FLASH is a high-density low cost non-volatile storage memory. On the other hand, NOR FLASH is
less dense and slightly expensive. But it supports the Execute in Place (XIP) technique for program execution.
The XIP technology allows the execution of code memory from ROM itself without the need for copying it to
the RAM as in the case of conventional execution method. It is a good practice to use a combination of NOR
and NAND memory for storage memory requirements, where NAND can be used for storing the program
code and or data like the data captured in a camera device. NAND FLASH doesn’t support XIP and if NAND
FLASH is used for storing program code, a DRAM can be used for copying and executing the program code.
NOR FLASH supports XIP and it can be used as the memory for bootloader or for even storing the complete
program code.
¶
Kb—Kilobytes
 The Typical Embedded System 35

The EEPROM data storage memory is available as either serial interface or parallel interface chip. If
the processor/controller of the device supports serial interface and the amount of data to write and read
to and from the device is less, it is better to have a Serial EEPROM chip. The Serial EEPROM saves the
address space of the total system. The memory capacity of the serial EEPROM is usually expressed in bits or
kilobits. 512 bits, 1Kbits, 2Kbits, 4Kbits, etc. are examples for serial EEPROM memory representation. For
embedded systems with low power requirements like portable devices, choose low power memory devices.
Certain embedded devices may be targeted for operating at extreme environmental conditions like high
temperature, high humid area, etc. Select an industrial grade memory chip in place of the commercial grade
chip for such devices.

2.3 SENSORS AND ACTUATORS

At the very beginning of this chapter it is already mentioned that an embedded
LO 3 Analyse the
system is in constant interaction with the Real world and the controlling/
role of sensors,
monitoring functions executed by the embedded system is achieved in
actuators, and their
accordance with the changes happening to the Real world. The changes in
interfacing with the
system environment or variables are detected by the sensors connected to the
I/O subsystems of
input port of the embedded system. If the embedded system is designed for any
an embedded system
controlling purpose, the system will produce some changes in the controlling
variable to bring the controlled variable to the desired value. It is achieved
through an actuator connected to the output port of the embedded system. If the embedded system is designed
for monitoring purpose only, then there is no need for including an actuator in the system. For example, take
the case of an ECG machine. It is designed to monitor the heart beat status of a patient and it cannot impose
a control over the patient’s heart beat and its order. The sensors used here are the different electrode sets
connected to the body of the patient. The variations are captured and presented to the user (may be a doctor)
through a visual display or some printed chart.

2.3.1 Sensors
A sensor is a transducer device that converts energy from one form to another for any measurement or control
purpose. This is what I “by-hearted” during my engineering degree from the transducers paper.
Looking back to the ‘Wearable devices’ example given at the end of Chapter 1, we can identify that the
sensor which counts steps for pedometer functionality is an Accelerometer sensor and the sensor used in
some of the smartwatch devices to measure the light intensity is an Ambient Light Sensor (ALS)

2.3.2 Actuators
Actuator is a form of transducer device (mechanical or electrical) which converts signals to corresponding
physical action (motion). Actuator acts as an output device.
Looking back to the ‘Wearable devices’ example given at the end of Chapter 1, we can see that certain
smartwatches use Ambient Light Sensor to detect the surrounding light intensity and uses an electrical/
electronic actuator circuit to adjust the screen brightness for better readability.

2.3.3 The I/O Subsystem

The I/O subsystem of the embedded system facilitates the interaction of the embedded system with the
external world. As mentioned earlier the interaction happens through the sensors and actuators connected to
the input and output ports respectively of the embedded system. The sensors may not be directly interfaced to
the input ports, instead they may be interfaced through signal conditioning and translating systems like ADC,
36 Introduc on to Embedded Systems

optocouplers, etc. This section illustrates some of the sensors and actuators used in embedded systems and
the I/O systems to facilitate the interaction of embedded systems with external world.
2.3.3.1 Light Emi ng Diode (LED) Light Emitting Diode (LED) is an important output device for
visual indication in any embedded system. LED can be used as an indicator for the status of various signals
or situations. Typical examples are indicating the presence of power conditions like ‘Device ON’, ‘Battery
low’ or ‘Charging of battery’ for a battery operated handheld embedded devices. Vcc
Light Emitting Diode is a p-n junction diode (Refer Analog Electronics
fundamentals to refresh your memory for p-n junction diode ☺) and it contains an

R
anode and a cathode. For proper functioning of the LED, the anode of it should be
connected to +ve terminal of the supply voltage and cathode to the –ve terminal
of supply voltage. The current flowing through the LED must be limited to a value
below the maximum current that it can conduct. A resister is used in series between
the power supply and the LED to limit the current through the LED. The ideal GND
LED interfacing circuit is shown in Fig. 2.13.
LEDs can be interfaced to the port pin of a processor/controller in two ways. Fig. 2.13 LED interfacing
In the first method, the anode is directly connected to the port pin and the port pin drives the LED. In this
approach the port pin ‘sources’ current to the LED when the port pin is at logic High (Logic ‘1’). In the
second method, the cathode of the LED is connected to the port pin of the processor/controller and the anode
to the supply voltage through a current limiting resistor. The LED is turned on when the port pin is at logic
Low (Logic ‘0’). Here the port pin ‘sinks’ current. If the LED is directly connected to the port pin, depending
on the maximum current that a port pin can source, the brightness of LED may not be to the required level.
In the second approach, the current is directly sourced by the power supply and the port pin acts as the sink
for current. Here we will get the required brightness for the LED.
2.3.3.2 7-Segment LED Display The 7-segment LED display is an output device for displaying alpha
numeric characters. It contains 8 light-emitting diode (LED)
segments arranged in a special form. Out of the 8 LED
segments, 7 are used for displaying alpha numeric characters A
and 1 is used for representing ‘decimal point’ in decimal
number display. Figure 2.14 explains the arrangement of F B
LED segments in a 7-segment LED display.
The LED segments are named A to G and the decimal G
point LED segment is named as DP. The LED segments A E C
to G and DP should be lit accordingly to display numbers
and characters. For example, for displaying the number 4, D
the segments F, G, B and C are lit. For displaying 3, the DP
segments A, B, C, D, G and DP are lit. For displaying the
character ‘d’, the segments B, C, D, E and G are lit. All these Fig. 2.14 7-Segment LED Display
8 LED segments need to be connected to one port of the processor/controller for displaying alpha numeric
digits. The 7-segment LED displays are available in two different configurations, namely; Common Anode
and Common Cathode. In the common anode configuration, the anodes of the 8 segments are connected
commonly whereas in the common cathode configuration, the 8 LED segments share a common cathode line.
Figure 2.15 illustrates the Common Anode and Cathode configurations.
Based on the configuration of the 7-segment LED unit, the LED segment’s anode or cathode is connected
to the port of the processor/controller in the order ‘A’ segment to the least significant port pin and DP
segment to the most significant port pin.
 The Typical Embedded System 37

Anode
DP G F E D C B A

DP G F E D C B A
Common Anode LED Display Cathode
Common Cathode LED Display
Fig. 2.15 Common anode and cathode configurations of a 7-segment LED Display

The current flow through each of the LED segments should be limited to the maximum value supported
by the LED display unit. The typical value for the current falls within the range of 20mA. The current
through each segment can be limited by connecting a current limiting resistor to the anode or cathode of
each segment. The value for the current limiting resistors can be calculated using the current value from the
electrical parameter listing of the LED display.
For common cathode configurations, the anode of each LED segment is connected to the port pins of the
port to which the display is interfaced. The anode of the common anode LED display is connected to the 5V
supply voltage through a current limiting resistor and the cathode of each LED segment is connected to the
respective port pin lines. For an LED segment to lit in the Common anode LED configuration, the port pin to
which the cathode of the LED segment is connected should be set at logic 0.
7-segment LED display is a popular choice for low cost embedded applications like, Public telephone call
monitoring devices, point of sale terminals, etc.
2.3.3.3 Optocoupler Optocoupler is a solid state device to isolate two parts of a circuit. Optocoupler
combines an LED and a photo-transistor in a single housing (package). Figure 2.16 illustrates the functioning
of an optocoupler device.
In electronic circuits, an optocoupler is used for suppressing
LED
interference in data communication, circuit isolation, high voltage I/O interface
separation, simultaneous separation and signal intensification, I/O interface
etc. Optocouplers can be used in either input circuits or in output
Photo-transistor
circuits. Figure 2.17 illustrates the usage of optocoupler in
input circuit and output circuit of an embedded system with a
Fig. 2.16 An optocoupler device
microcontroller as the system core.

Vcc

AT89C51 LED
LED
I/p interface Port pin
O/p interface
Port pin
Photo-transistor Photo-transistor

Optocoupler Microcontroller Optocoupler

IC MCT2M IC MCT2M

Fig. 2.17 Optocoupler in Input and Output circuit

38 Introduc on to Embedded Systems

Optocoupler is available as ICs from different semiconductor manufacturers. The MCT2M IC from
Fairchild semiconductor (http://www.fairchildsemi.com/) is an example for optocoupler IC.
2.3.3.4 Stepper Motor A stepper motor is an electro-mechanical device which generates discrete
displacement (motion) in response to dc electrical signals. It differs from the normal dc motor in its operation.
The dc motor produces continuous rotation on applying dc voltage whereas a stepper motor produces discrete
rotation in response to the dc voltage applied to it. Stepper motors are widely used in industrial embedded
applications, consumer electronic products and robotics control systems. The paper feed mechanism of a
printer/fax makes use of stepper motors for its functioning.
Based on the coil winding arrangements, a two-phase stepper motor is classified into two. They are:
(1) Unipolar
(2) Bipolar
(1) Unipolar A unipolar stepper motor contains two windings per
phase. The direction of rotation (clockwise or anticlockwise) of a
stepper motor is controlled by changing the direction of current flow. A
Current in one direction flows through one coil and in the opposite

GND
M
direction flows through the other coil. It is easy to shift the direction
of rotation by just switching the terminals to which the coils are C
connected. Figure 2.18 illustrates the working of a two-phase unipolar
stepper motor. B D
The coils are represented as A, B, C and D. Coils A and C carry
current in opposite directions for phase 1 (only one of them will GND
be carrying current at a time). Similarly, B and D carry current in
opposite directions for phase 2 (only one of them will be carrying Fig. 2.18 2-Phase unipolar stepper motor
current at a time).
(2) Bipolar A bipolar stepper motor contains single winding per phase. For reversing the motor rotation
the current flow through the windings is reversed dynamically. It requires complex circuitry for current flow
reversal. The stator winding details for a two phase unipolar stepper motor is shown in Fig. 2.19.
The stepping of stepper motor can be implemented in different ways by changing the sequence of activation
of the stator windings. The different stepping modes supported by stepper motor are explained below.
Full Step In the full step mode both the phases are energised simultaneously. The coils A, B, C and D are
energised in the following order:

Step Coil A Coil B Coil C Coil D

1 H H L L
2 L H H L
3 L L H H
4 H L L H

It should be noted that out of the two windings, only one winding of a phase is energised at a time.
 The Typical Embedded System 39

A C B D

GND

N
GND

Fig. 2.19 Stator Winding details for a 2 Phase unipolar stepper motor
Wave Step In the wave step mode only one phase is energised at a time and each coils of the phase is
energised alternatively. The coils A, B, C, and D are energised in the following order:
Step Coil A Coil B Coil C Coil D
1 H L L L
2 L H L L
3 L L H L
4 L L L H

Half Step It uses the combination of wave and full step. It has the highest torque and stability. The coil
energising sequence for half step is given below.
Step Coil A Coil B Coil C Coil D
1 H L L L
2 H H L L
3 L H L L
4 L H H L
5 L L H L
6 L L H H
7 L L L H
8 H L L H
40 Introduc on to Embedded Systems

The rotation of the stepper motor can be reversed by reversing the order in which the coil is energised.
Two-phase unipolar stepper motors are the popular choice for embedded applications. The current
requirement for stepper motor is little high and hence the port pins of a microcontroller/processor may not be
able to drive them directly. Also the supply voltage required to operate stepper motor varies normally in the
range 5V to 24 V. Depending on the current and voltage requirements, special driving circuits are required to
interface the stepper motor with microcontroller/processors. Commercial off-the-shelf stepper motor driver
ICs are available in the market and they can be directly interfaced to the microcontroller port. ULN2803 is
an octal peripheral driver array available from Texas Instruments and ST microelectronics for driving a 5V
stepper motor. Simple driving circuit can also be built using transistors.
The following circuit diagram (Fig. 2.20) illustrates the interfacing of a stepper motor through a driver
circuit connected to the port pins of a microcontroller/processor.

Port pins A
M

Driver IC C
Microcontroller
ULN2803 B D

Vcc Vcc

Fig. 2.20 Interfacing of stepper motor through driver circuit

2.3.3.5 Relay Relay is an electro-mechanical device. In embedded application, the ‘Relay’ unit acts as
dynamic path selectors for signals and power. The ‘Relay’ unit contains a relay coil made up of insulated
wire on a metal core and a metal armature with one or more contacts.
‘Relay’ works on electromagnetic principle. When a voltage is applied to the relay coil, current flows
through the coil, which in turn generates a magnetic field. The magnetic field attracts the armature core and
moves the contact point. The movement of the contact point changes the power/signal flow path. ‘Relays’ are
available in different configurations. Figure 2.21 given below illustrates the widely used relay configurations
for embedded applications.
Relay coil

Relay coil

Relay coil

Single pole single Single pole single Single pole double

throw normally throw normally throw
open closed
Fig. 2.21 Relay configurations
 The Typical Embedded System 41

The Single Pole Single Throw configuration has only one path for information flow. The path is either
open or closed in normal condition. For normally Open Single Pole Single Throw relay, the circuit is normally
open and it becomes closed when the relay is energised. For normally closed Single Pole Single Throw
configuration, the circuit is normally closed and it becomes open when the relay is energised. For Single
Pole Double Throw Relay, there are two paths for information flow and they are selected by energising or
de-energising the relay.
The Relay is normally controlled using a relay driver circuit connected to the port pin of the processor/
controller. A transistor is used for building the relay driver circuit. Figure 2.22 illustrates the same.

Vcc

Freewheeling diode

Relay coil
Load
Port pin

Relay unit

Fig. 2.22 Transistor based Relay driving circuit

A free-wheeling diode is used for free-wheeling the voltage produced in the opposite direction when the
relay coil is de-energised. The freewheeling diode is essential for protecting the relay and the transistor.
Most of the industrial relays are bulky and requires high voltage to operate. Special relays called ‘Reed’
relays are available for embedded application requiring switching of low voltage DC signals.
2.3.3.6 Piezo Buzzer Piezo buzzer is a piezoelectric device for generating audio indications in embedded
application. A piezoelectric buzzer contains a piezoelectric diaphragm which produces audible sound in
response to the voltage applied to it. Piezoelectric buzzers are available in two types. ‘Self-driving’ and
‘External driving’. The ‘Self-driving’ circuit contains all the necessary components to generate sound at a
predefined tone. It will generate a tone on applying the voltage. External driving piezo buzzers supports the
generation of different tones. The tone can be varied by applying a variable pulse train to the piezoelectric
buzzer. A piezo buzzer can be directly interfaced to the port pin of the processor/control. Depending on the
driving current requirements, the piezo buzzer can also be interfaced using a transistor based driver circuit as
in the case of a ‘Relay’.
2.3.3.7 Push Bu on Switch It is an input device. Push button switch comes in two configurations,
namely ‘Push to Make’ and ‘Push to Break’. In the ‘Push to Make’ configuration, the switch is normally in
the open state and it makes a circuit contact when it is pushed or pressed. In the ‘Push to Break’ configuration,
the switch is normally in the closed state and it breaks the circuit contact when it is pushed or pressed. The
push button stays in the ‘closed’ (For Push to Make type) or ‘open’ (For Push to Break type) state as long as
it is kept in the pushed state and it breaks/makes the circuit connection when it is released. Push button is used
for generating a momentary pulse. In embedded application push button is generally used as reset and start
switch and pulse generator. The Push button is normally connected to the port pin of the host processor/
42 Introduc on to Embedded Systems

controller. Depending on the way in which the push Vcc Vcc

button interfaced to the controller, it can generate either
a ‘HIGH’ pulse or a ‘LOW’ pulse. Figure 2.23 illustrates
how the push button can be used for generating ‘LOW’
and ‘HIGH’ pulses. Port pin Port pin

2.3.3.8 Keyboard Keyboard is an input device for

user interfacing. If the number of keys required is very
limited, push button switches can be used and they
can be directly interfaced to the port pins for reading.
However, there may be situations demanding a large
number of keys for user input (e.g. PDA device with ‘LOW’ Pulse generator ‘HIGH’ Pulse generator
alpha-numeric keypad for user data entry). In such
Fig. 2.23 Push button switch configurations
situations it may not be possible to interface each keys
to a port pin due to the limitation in the number of general purpose port pins available for the processor/
controller in use and moreover it is wastage of port pins. Matrix keyboard is an optimum solution for handling
large key requirements. It greatly reduces the number of interface connections. For example, for interfacing
16 keys, in the direct interfacing technique 16 port pins are required, whereas in the matrix keyboard only
8 lines are required. The 16 keys are arranged in a 4 column × 4 Row matrix. Figure 2.24 illustrates the
connection of keys in a matrix keyboard.
Vcc
4.7K

4.7K
4.7K

4.7K

Row 0
To microcontroller /processor port

Row 1

Row 2

Row 3
Column 0

Column 1

Column 2

Column 3

To microcontroller /processor port

Fig. 2.24 Matrix keyboard Interfacing
 The Typical Embedded System 43

In a matrix keyboard, the keys are arranged in matrix fashion (i.e. they are connected in a row and column
style). For detecting a key press, the keyboard uses the scanning technique, where each row of the matrix
is pulled low and the columns are read. After reading the status of each columns corresponding to a row,
the row is pulled high and the next row is pulled low and the status of the columns are read. This process is
repeated until the scanning for all rows are completed. When a row is pulled low and if a key connected to the
row is pressed, reading the column to which the key is connected will give logic 0. Since keys are mechanical
devices, there is a possibility for de-bounce issues, which may give multiple key press effect for a single
key press. To prevent this, a proper key de-bouncing technique should be applied. Hardware key de-bouncer
circuits and software key de-bounce techniques are the key de-bouncing techniques available. The software
key de-bouncing technique doesn’t require any additional hardware and is easy to implement. In the software
de-bouncing technique, on detecting a key-press, the key is read again after a de-bounce delay. If the key
press is a genuine one, the state of the key will remain as ‘pressed’ on the second read also. Pull-up resistors
are connected to the column lines to limit the current that flows to the Row line on a key press.
2.3.3.9 Programmable Peripheral Interface (PPI) Programmable Peripheral Interface (PPI) devices
are used for extending the I/O capabilities of processors/controllers. Most of the processors/controllers
provide very limited number of I/O and data ports and at times it may require more number of I/O ports
than the one supported by the controller/processor. A programmable peripheral interface device expands the
I/O capabilities of the processor/controller. 8255A is a popular PPI device for 8bit processors/controllers.
8255A supports 24 I/O pins and these I/O pins can be grouped as either three 8-bit parallel ports (Port A,
Port B and Port C) or two 8bit parallel ports (Port A and Port B) with Port C in any one of the following
configurations:
(1) As 8 individual I/O pins
(2) Two 4bit ports namely Port CUPPER (CU) and Port CLOWER (CL)
This is configured by manipulating the control register of 8255A. The control register holds the configuration
for Port A, Port B and Port C. The bit details of control register is given below:

D7 D6 D5 D4 D3 D2 D1 D0

The table given below explains the meaning and use of each bit.

Bit Description
D0 Port C Lower (CL) I/O mode selector
D0 = 1; Sets CL as input port
D0 = 0; Sets CL as output port
D1 Port B I/O mode selector
D1 = 1; Sets port B as input port
D1 = 0; Sets port B as output port
D2 Mode selector for port C lower and port B
D2 = 0; Mode 0 – Port B functions as 8bit I/O Port. Port C lower functions as 4bit port.
D2 = 1; Mode 1 – Handshake mode. Port B uses 3 bits of Port C as handshake signals
(Contd.)
44 Introduc on to Embedded Systems

Bit Description
D3 Port C Upper (CU) I/O mode selector
D3 = 1; Sets CU as input port
D3 = 0; Sets CU as output port
D4 Port A I/O mode selector
D4 = 1; Sets Port A as input port
D4 = 0; Sets Port A as output port
D5, D6 Mode selector for port C upper and port A
D6 D5 = 00; Mode 0 – Simple I/O mode
D6 D5 = 01; Mode 1 – Handshake mode. Port A uses 3 bits of
Port C as handshake signals
D6 D5 = 1X; Mode 2. X can be 0 or 1 – Port A functions as bi-directional port
D7 Control/Data mode selector for port C
D7 = 1; I/O mode.
D7 = 0; Bit set/reset (BSR) mode. Functions as the control/status lines for ports A and B. The bits of
port C can be set or reset just as if they were output ports.

Please refer to the 8255A datasheet available at http://www.intersil.com/data/fn/fn2969.pdf for more

details about the different operating modes of 8255.
Figure 2.25 illustrates the generic interfacing of a 8255A device with an 8bit processor/controller with
16bit address bus (Lower order Address bus is multiplexed with data bus).

Processor/
82C55A
Controller Data bus D0….D7 D0….D7
Data bus port
Pins 34 to 27
Latch
A0 Pin 9
(Eg: 74LS373) PA0….PA7
A1 Pin 8
Port A
ALE
A2….A7 PB0….PB7
Port B
Higher order
Address bus Address bus Address
CS\ Pin 6
(A8….A15) decoder PC0….PC7
Port C
RD\\ RD\ Pin 5
WR\ WR\ Pin 36
RESET OUT RESET Pin 35

Fig. 2.25 Interfacing of 8255 with an 8 bit microcontroller

The ports of 8255 can be configured for different modes of operation by the processor/controller.
 The Typical Embedded System 45

2.4 COMMUNICATION INTERFACE

Communication interface is essential for communicating with various subsystems
LO 4 Examine
of the embedded system and with the external world. For an embedded product,
the different
the communication interface can be viewed in two different perspectives; namely;
communication
Device/board level communication interface (Onboard Communication Interface)
interfaces of an
and Product level communication interface (External Communication Interface).
embedded system
Embedded product is a combination of different types of components (chips/
devices) arranged on a printed circuit board (PCB). The communication channel which interconnects the
various components within an embedded product is referred as device/board level communication interface
(onboard communication interface). Serial interfaces like I2C, SPI, UART, 1-Wire, etc and parallel bus
interface are examples of ‘Onboard Communication Interface’.
Some embedded systems are self-contained units and they don’t require any interaction and data transfer
with other sub-systems or external world. On the other hand, certain embedded systems may be a part of a large
distributed system and they require interaction and data transfer between various devices and sub-modules.
The ‘Product level communication interface’ (External Communication Interface) is responsible for data
transfer between the embedded system and other devices or modules. The external communication interface
can be either a wired media or a wireless media and it can be a serial or a parallel interface. Infrared (IR),
Bluetooth (BT), Wireless LAN (Wi-Fi), Radio Frequency waves (RF), GPRS/3G/4GLTE, etc. are examples
for wireless communication interface. RS-232C/RS-422/RS-485, USB, Ethernet, IEEE 1394 port, Parallel
port, CF-II interface, SDIO, PCMCIA/PCIex, etc. are examples for wired interfaces. It is not mandatory that
an embedded system should contain an external communication interface. Mobile communication equipment
is an example for embedded system with external communication interface.
The following section gives you an overview of the various ‘Onboard’ and ‘External’ communication
interfaces for an embedded product. We will discuss about the various physical interface, firmware
requirements and initialisation and communication sequence for these interfaces in a dedicated book titled
‘Device Interfacing’, which is planned under this series.

2.4.1 Onboard Communication Interfaces

Onboard Communication Interface refers to the different communication channels/buses for interconnecting
the various integrated circuits and other peripherals within the embedded system. The following section gives
an overview of the various interfaces for onboard communication.
2.4.1.1 Inter Integrated Circuit (I2C) Bus The Inter Integrated Circuit Bus (I2C–Pronounced ‘I square
C’) is a synchronous bi-directional half duplex (one-directional communication at a given point of time) two
wire serial interface bus. The concept of I2C bus was developed by ‘Philips semiconductors’ in the early
1980s. The original intention of I2C was to provide an easy way of connection between a microprocessor/
microcontroller system and the peripheral chips in television sets. The I2C bus comprise of two bus lines,
namely; Serial Clock–SCL and Serial Data–SDA. SCL line is responsible for generating synchronisation
clock pulses and SDA is responsible for transmitting the serial data across devices. I2C bus is a shared bus
system to which many number of I2C devices can be connected. Devices connected to the I2C bus can act as
either ‘Master’ device or ‘Slave’ device. The ‘Master’ device is responsible for controlling the communication
by initiating/terminating data transfer, sending data and generating necessary synchronisation clock pulses.
‘Slave’ devices wait for the commands from the master and respond upon receiving the commands. ‘Master’
and ‘Slave’ devices can act as either transmitter or receiver. Regardless whether a master is acting as transmitter
or receiver, the synchronisation clock signal is generated by the ‘Master’ device only. I2C supports multi
46 Introduc on to Embedded Systems

masters on the same bus. The following bus interface diagram shown in Fig. 2.26 illustrates the connection
of master and slave devices on the I2C bus.

SCL SDA Vcc

2.2K

SDA
2.2K
Port pins SCL
Slave 1
SCL I2C Device
Master SDA (e.g. Serial
(Microprocessor/ EEPROM)
Controller)

SCL Slave 2
SDA I2C Device

I2C bus
Fig. 2.26 12C Bus Interfacing

The I2C bus interface is built around an input buffer and an open drain or collector transistor. When the
bus is in the idle state, the open drain/collector transistor will be in the floating state and the output lines (SDA
and SCL) switch to the ‘High Impedance’ state. For proper operation of the bus, both the bus lines should
be pulled to the supply voltage (+5V for TTL family and +3.3V for CMOS family devices) using pull-up
resistors. The typical value of resistors used in pull-up is 2.2K. With pull-up resistors, the output lines of the
bus in the idle state will be ‘HIGH’.
The address of a I2C device is assigned by hardwiring the address lines of the device to the desired logic
level. The address to various I2C devices in an embedded device is assigned and hardwired at the time of
designing the embedded hardware. The sequence of operations for communicating with an I2C slave device
is listed below:
1. The master device pulls the clock line (SCL) of the bus to ‘HIGH’
2. The master device pulls the data line (SDA) ‘LOW’, when the SCL line is at logic ‘HIGH’ (This is the
‘Start’ condition for data transfer)
3. The master device sends the address (7 bit or 10 bit wide) of the ‘slave’ device to which it wants to
communicate, over the SDA line. Clock pulses are generated at the SCL line for synchronising the bit
reception by the slave device. The MSB of the data is always transmitted first. The data in the bus is
valid during the ‘HIGH’ period of the clock signal
4. The master device sends the Read or Write bit (Bit value = 1 Read operation; Bit value = 0 Write
operation) according to the requirement
5. The master device waits for the acknowledgement bit from the slave device whose address is sent on
the bus along with the Read/Write operation command. Slave devices connected to the bus compares
the address received with the address assigned to them
 The Typical Embedded System 47

6. The slave device with the address requested by the master device responds by sending an acknowledge
bit (Bit value = 1) over the SDA line
7. Upon receiving the acknowledge bit, the Master device sends the 8bit data to the slave device over
SDA line, if the requested operation is ‘Write to device’. If the requested operation is ‘Read from
device’, the slave device sends data to the master over the SDA line
8. The master device waits for the acknowledgement bit from the device upon byte transfer complete for
a write operation and sends an acknowledge bit to the Slave device for a read operation
9. The master device terminates the transfer by pulling the SDA line ‘HIGH’ when the clock line SCL is
at logic ‘HIGH’ (Indicating the ‘STOP’ condition)
The first generation I2C devices were designed to support data rates only up to 100kbps. Over time there
have been several additions to the specification so that there are now five operating speed categories; Namely,
Standard mode (Sm - Data rate up to 100kbit/sec), Fast mode (Fm - Data rate up to 400kbit/sec), Fast mode
Plus (Fm+ - Data rate up to 1Mbit/sec), and High-speed mode (Hs-mode - Data rate up to 3.4Mbit/sec) and
an Ultra Fast-mode (UFm), with a bit rate up to 5 Mbit/s for unidirectional I2C bus.
2.4.1.2 Serial Peripheral Interface (SPI) Bus The Serial Peripheral Interface Bus (SPI) is a synchronous
bi-directional full duplex four-wire serial interface bus. The concept of SPI was introduced by Motorola. SPI
is a single master multi-slave system. It is possible to have a system where more than one SPI device can be
master, provided the condition only one master device is active at any given point of time, is satisfied. SPI
requires four signal lines for communication. They are:
Master Out Slave In (MOSI): Signal line carrying the data from master to slave device. It is also
known as Slave Input/Slave Data In (SI/SDI)
Master In Slave Out (MISO): Signal line carrying the data from slave to master device. It is also
known as Slave Output (SO/SDO)
Serial Clock (SCLK): Signal line carrying the clock signals
Slave Select (SS): Signal line for slave device select. It is an active low signal
The bus interface diagram shown in Fig. 2.27 illustrates the connection of master and slave devices on
the SPI bus.
The master device is responsible for generating the clock signal. It selects the required slave device by
asserting the corresponding slave device’s slave select signal ‘LOW’. The data out line (MISO) of all the
slave devices when not selected floats at high impedance state.
The serial data transmission through SPI bus is fully configurable. SPI devices contain a certain set of
registers for holding these configurations. The serial peripheral control register holds the various configuration
parameters like master/slave selection for the device, baudrate selection for communication, clock signal
control, etc. The status register holds the status of various conditions for transmission and reception.
SPI works on the principle of ‘Shift Register’. The master and slave devices contain a special shift register
for the data to transmit or receive. The size of the shift register is device dependent. Normally it is a multiple
of 8. During transmission from the master to slave, the data in the master’s shift register is shifted out to
the MOSI pin and it enters the shift register of the slave device through the MOSI pin of the slave device.
At the same time the shifted out data bit from the slave device’s shift register enters the shift register of the
master device through MISO pin. In summary, the shift registers of ‘master’ and ‘slave’ devices form a
circular buffer. For some devices, the decision on whether the LS/MS bit of data needs to be sent out first is
configurable through configuration register (e.g. LSBF bit of the SPI control register for Motorola’s 68HC12
controller).
When compared to I2C, SPI bus is most suitable for applications requiring transfer of data in ‘streams’.
The only limitation is SPI doesn’t support an acknowledgement mechanism.
48 Introduc on to Embedded Systems

MOSI SCL MISO

MISO
SCL
MOSI MOSI Slave 1
SCL SPI device
Master (e.g.: Serial
MISO
(Microprocessor/ EEPROM)
SS\
Controller)
SS1\
SS2\
MOSI
Slave 2
SCL
SPI device
MISO
(e.g.: LCD)
SS\

SPI bus
Fig. 2.27 SPI bus interfacing

2.4.1.3 Universal Asynchronous Receiver Transmi er (UART) Universal Asynchronous Receiver

Transmitter (UART) based data transmission is an asynchronous form of serial data transmission. UART
based serial data transmission doesn’t require a clock signal to synchronise the transmitting end and receiving
end for transmission. Instead it relies upon the pre-defined agreement between the transmitting device and
receiving device. The serial communication settings (Baudrate, number of bits per byte, parity, number of
start bits and stop bit and flow control) for both transmitter and receiver should be set as identical. The start
and stop of communication is indicated through inserting special bits in the data stream. While sending a byte
of data, a start bit is added first and a stop bit is added at the end of the bit stream. The least significant bit of
the data byte follows the ‘start’ bit.
The ‘start’ bit informs the receiver that a data byte is about to arrive. The receiver device starts polling its
‘receive line’ as per the baudrate settings. If the baudrate is ‘x’ bits per second, the time slot available for one
bit is 1/x seconds. The receiver unit polls the receiver line at exactly half of the time slot available for the bit.
If parity is enabled for communication, the UART of the transmitting device adds a parity bit (bit value is 1
for odd number of 1s in the transmitted bit stream and 0 for even number of 1s). The UART of the receiving
device calculates the parity of the bits received and compares it with the received parity bit for error checking.
The UART of the receiving device discards the ‘Start’, ‘Stop’ and ‘Parity’ bit from the received bit stream
and converts the received serial bit data to a word (In the case of 8 bits/byte, the byte is formed with the
received 8 bits with the first received bit as the LSB and last received data bit as MSB).
For proper communication, the ‘Transmit line’ of the sending device should be connected to the ‘Receive
line’ of the receiving device. Figure 2.28 illustrates the same.
 The Typical Embedded System 49

TXD TXD
UART UART
RXD RXD

TXD: Transmitter line

RXD: Receiver line
Fig. 2.28 UART Interfacing

In addition to the serial data transmission function, UART provides hardware handshaking signal support
for controlling the serial data flow. UART chips are available from different semiconductor manufacturers.
National Semiconductor’s 8250 UART chip is considered as the standard setting UART. It was used in the
original IBM PC.
Nowadays most of the microprocessors/controllers are available with integrated UART functionality and
they provide built-in instruction support for serial data transmission and reception.
2.4.1.4 1-Wire Interface 1-wire interface is an asynchronous half-duplex communication protocol
developed by Maxim Dallas Semiconductor (http://www.maxim-ic.com). It is also known as Dallas 1-Wire®
protocol. It makes use of only a single signal line (wire) called DQ for communication and follows the
master-slave communication model. One of the key feature of 1-wire bus is that it allows power to be sent
along the signal wire as well. The 1-Wire slave devices incorporate internal capacitor (typically of the order
of 800 pF) to power the device from the signal line. The 1-wire interface supports a single master and one
or more slave devices on the bus. The bus interface diagram shown in Fig. 2.29 illustrates the connection of
master and slave devices on the 1-wire bus.
Vcc

4.7K

DQ Slave 1
Port pin
1-wire device
(e.g.: DS2762 Battery
GND
monitor IC )
Master
(Microprocessor/
Controller)
DQ Slave 2
1-wire device
(e.g.: DS2431 1024
GND GND
Bit EEPROM )

Fig. 2.29 1-Wire Interface bus

50 Introduc on to Embedded Systems

Every 1-wire device contains a globally unique 64bit identification number stored within it. This unique
identification number can be used for addressing individual devices present on the bus in case there are
multiple slave devices connected to the 1-wire bus. The identifier has three parts: an 8bit family code, a 48bit
serial number and an 8bit Cyclic Redundancy Check (CRC) computed from the first 56 bits. The sequence of
operation for communicating with a 1-wire slave device is listed below.
1. The master device sends a ‘Reset’ pulse on the 1-wire bus.
2. The slave device(s) present on the bus respond with a ‘Presence’ pulse.
3. The master device sends a ROM command (Net Address Command followed by the 64bit address of
the device). This addresses the slave device(s) to which it wants to initiate a communication.
4. The master device sends a read/write function command to read/write the internal memory or register
of the slave device.
5. The master initiates a Read data/Write data from the device or to the device
All communication over the 1-wire bus is master initiated. The communication over the 1-wire bus is
divided into timeslots of 60 microseconds for the regular speed mode of operation (16.3kbps). The ‘Reset’
pulse occupies 8 time slots. For starting a communication, the master asserts the reset pulse by pulling the
1-wire bus ‘LOW’ for at least 8 time slots (480ms). If a ‘slave’ device is present on the bus and is ready for
communication it should respond to the master with a ‘Presence’ pulse, within 60ms of the release of the
‘Reset’ pulse by the master. The slave device(s) responds with a ‘Presence’ pulse by pulling the 1-wire bus
‘LOW’ for a minimum of 1 time slot (60ms). For writing a bit value of 1 on the 1-wire bus, the bus master
pulls the bus for 1 to 15ms and then releases the bus for the rest of the time slot. A bit value of ‘0’ is written on
the bus by master pulling the bus for a minimum of 1 time slot (60ms) and a maximum of 2 time slots (120ms).
To Read a bit from the slave device, the master pulls the bus ‘LOW’ for 1 to 15ms. If the slave wants to send a
bit value ‘1’ in response to the read request from the master, it simply releases the bus for the rest of the time
slot. If the slave wants to send a bit value ‘0’, it pulls the bus ‘LOW’ for the rest of the time slot.
2.4.1.5 Parallel Interface The on-board parallel interface is normally used for communicating with
peripheral devices which are memory mapped to the host of the system. The host processor/controller of
the embedded system contains a parallel bus and the device which supports parallel bus can directly connect
to this bus system. The communication through the parallel bus is controlled by the control signal interface
between the device and the host. The ‘Control Signals’ for communication includes ‘Read/Write’ signal and
device select signal. The device normally contains a device select line and the device becomes active only
when this line is asserted by the host processor. The direction of data transfer (Host to Device or Device
to Host) can be controlled through the control signal lines for ‘Read’ and ‘Write’. Only the host processor
has control over the ‘Read’ and ‘Write’ control signals. The device is normally memory mapped to the host
processor and a range of address is assigned to it. An address decoder circuit is used for generating the chip
select signal for the device. When the address selected by the processor is within the range assigned for the
device, the decoder circuit activates the chip select line and thereby the device becomes active. The processor
then can read or write from or to the device by asserting the corresponding control line (RD\ and WR\
respectively). Strict timing characteristics are followed for parallel communication. As mentioned earlier,
parallel communication is host processor initiated. If a device wants to initiate the communication, it can
inform the same to the processor through interrupts. For this, the interrupt line of the device is connected to
the interrupt line of the processor and the corresponding interrupt is enabled in the host processor. The width
of the parallel interface is determined by the data bus width of the host processor. It can be 4bit, 8bit, 16bit,
32bit or 64bit etc. The bus width supported by the device should be same as that of the host processor. The
bus interface diagram shown in Fig. 2.30 illustrates the interfacing of devices through parallel interface.
 The Typical Embedded System 51

D0 to Data bus
Dx-1 Peripheral device
RD\ RD\ (e.g.: ADC)
WR\ WR\
Host Control signals CS\
(Microprocessor /
Controller ) Chip select

A0 to Address bus Address de-coder

Ay-1 circuit

x: Data bus width

y: Address bus width
Fig. 2.30 Parallel Interface Bus

Parallel data communication offers the highest speed for data transfer.

2.4.2 External Communication Interfaces

The External Communication Interface refers to the different communication channels/buses used by the
embedded system to communicate with the external world. The following section gives an overview of the
various interfaces for external communication.
2.4.2.1 RS-232 C & RS-485 RS-232 C (Recommended Standard number 232, revision C from the
Electronic Industry Association) is a legacy, full duplex, wired, asynchronous serial communication interface.
The RS-232 interface is developed by the Electronics Industries Association (EIA) during the early 1960s.
RS-232 extends the UART communication signals for external data communication.
UART uses the standard TTL/CMOS logic (Logic ‘High’ corresponds to bit value 1 and Logic ‘Low’
corresponds to bit value 0) for bit transmission whereas RS-232 follows the EIA standard for bit transmission.
As per the EIA standard, a logic ‘0’ is represented with voltage between +3 and +25V and a logic ‘1’ is
represented with voltage between –3 and –25V. In EIA standard, logic ‘0’ is known as ‘Space’ and logic ‘1’
as ‘Mark’. The RS-232 interface defines various handshaking and control signals for communication apart
from the ‘Transmit’ and ‘Receive’ signal lines for data communication. RS-232 supports two different types
of connectors, namely; DB-9: 9-Pin connector and DB-25: 25-Pin connector. Figure 2.31 illustrates the
connector details for DB-9 and DB-25.

1 13
1 5

6 9 14 25
DB-25
DB-9
Fig. 2.31 DB-9 and DB-25 RS-232 Connector Interface
52 Introduc on to Embedded Systems

The pin details for the two connectors are explained in the following table:

Pin Name Pin no: (For DB-9 Pin no: (For DB-25 Description
Connector) Connector)
TXD 3 2 Transmit Pin for Transmitting Serial Data
RXD 2 3 Receive Pin for Receiving Serial Data
RTS 7 4 Request to send.
CTS 8 5 Clear To Send
DSR 6 6 Data Set Ready
GND 5 7 Signal Ground
DCD 1 8 Data Carrier Detect
DTR 4 20 Data Terminal Ready
RI 9 22 Ring Indicator
FG 1 Frame Ground
SDCD 12 Secondary DCD
SCTS 13 Secondary CTS
STXD 14 Secondary TXD
TC 15 Transmission Signal Element Timing
SRXD 16 Secondary RXD
RC 17 Receiver Signal Element Timing
SRTS 19 Secondary RTS
SQ 21 Signal Quality detector
NC 9 No Connection
NC 10 No Connection
NC 11 No Connection
NC 18 No Connection
NC 23 No Connection
NC 24 No Connection
NC 25 No Connection

RS-232 is a point-to-point communication interface and the devices involved in RS-232 communication
are called ‘Data Terminal Equipment (DTE)’ and ‘Data Communication Equipment (DCE)’. If no data flow
control is required, only TXD and RXD signal lines and ground line (GND) are required for data transmission
and reception. The RXD pin of DCE should be connected to the TXD pin of DTE and vice versa for proper
data transmission.
If hardware data flow control is required for serial transmission, various control signal lines of the RS-232
connection are used appropriately. The control signals are implemented mainly for modem communication
and some of them may not be irrelevant for other type of devices. The Request To Send (RTS) and Clear To
Send (CTS) signals co-ordinate the communication between DTE and DCE. Whenever the DTE has a data to
send, it activates the RTS line and if the DCE is ready to accept the data, it activates the CTS line.
 The Typical Embedded System 53

The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept data. The Data Set
Ready (DSR) is activated by DCE when it is ready for establishing a communication link. DTR should be in
the activated state before the activation of DSR.
The Data Carrier Detect (DCD) control signal is used by the DCE to indicate the DTE that a good signal
is being received.
Ring Indicator (RI) is a modem specific signal line for indicating an incoming call on the telephone line.
The 25 pin DB connector contains two sets of signal lines for transmit, receive and control lines. Nowadays
DB-25 connector is obsolete and most of the desktop systems are available with DB-9 connectors only.
As per the EIA standard RS-232 C supports baudrates up to 20Kbps (Upper limit 19.2 Kbps) The commonly
used baudrates by devices are 300bps, 1200bps, 2400bps, 9600bps, 11.52Kbps and 19.2Kbps. 9600 is the
popular baudrate setting used for PC communication. The maximum operating distance supported by RS-232
is 50 feet at the highest supported baudrate.
Embedded devices contain a UART for serial communication and they generate signal levels conforming
to TTL/CMOS logic. A level translator IC like MAX 232 from Maxim Dallas semiconductor is used for
converting the signal lines from the UART to RS-232 signal lines for communication. On the receiving side
the received data is converted back to digital logic level by a converter IC. Converter chips contain converters
for both transmitter and receiver.
Though RS-232 was the most popular communication interface during the olden days, the advent of other
communication techniques like Bluetooth, USB, Firewire, etc are pushing down RS-232 from the scenes.
Still RS-232 is popular in certain legacy industrial applications.
RS-232 supports only point-to-point communication and not suitable for multi-drop communication. It
uses single ended data transfer technique for signal transmission and thereby more susceptible to noise and it
greatly reduces the operating distance.
RS-422 is another serial interface standard from EIA for differential data communication. It supports data
rates up to 100Kbps and distance up to 400 ft. The same RS-232 connector is used at the device end and an
RS-232 to RS-422 converter is plugged in the transmission line. At the receiver end the conversion from RS-
422 to RS-232 is performed. RS-422 supports multi-drop communication with one transmitter device and
receiver devices up to 10.
RS-485 is the enhanced version of RS-422 and it supports multi-drop communication with up to 32
transmitting devices (drivers) and 32 receiving devices on the bus. The communication between devices in
the bus uses the ‘addressing’ mechanism to identify slave devices.
2.4.2.2 Universal Serial Bus (USB) Universal Serial Bus (USB) is a wired high speed serial bus for
data communication. The first version of USB (USB1.0) was released in 1995 and was created by the USB
core group members consisting of Intel, Microsoft, IBM, Compaq, Digital and Northern Telecom. The USB
communication system follows a star topology with a USB host at the centre and one or more USB peripheral
devices/USB hosts connected to it. A USB 2.0 host can support connections up to 127, including slave
peripheral devices and other USB hosts. Figure 2.32 illustrates the star topology for USB device connection.
USB transmits data in packet format. Each data packet has a standard format. The USB communication is
a host initiated one. The USB host contains a host controller which is responsible for controlling he data
communication, including establishing connectivity with USB slave devices, packetizing and formatting the
data packet. There are different standards for implementing the USB Host Control interface; namely Open
Host Control Interface (OHCI) and Universal Host Control Interface (UHCI).
The physical connection between a USB peripheral device and master device is established with a USB
cable. The USB cable in USB 2.0 specification supports communication distance of up to 5 meters. The USB
2.0 standard uses two different types of connector at the ends of the USB cable for connecting the USB
54 Introduc on to Embedded Systems

peripheral device and host device. ‘Type A’ connector is used for upstream connection (connection with
host) and Type B OR Mini/Micro USB connector is used for downstream connection (connection with slave
device). The USB 2.0 connector seen at desktop PCs or laptops
are examples for ‘Type A’ USB connector. Both Type A and
Type B connectors contain 4 pins for communication. The Pin
details for the USB 2.0 Type A & B connectors are listed in the Peripheral
table given below. device 2
Pin no. Pin name Description
1 VBUS Carries power (5V)
2 D– Differential data carrier line Peripheral USB host Peripheral
3 D+ Differential data carrier line device 1 (Hub) device 3
4 GND Ground signal line

USB uses differential signals for data transmission. It

improves the noise immunity. USB interface has the ability to USB host
supply power to the connecting devices. Two connection lines (Hub)
(Ground and Power) of the USB interface are dedicated for
carrying power. A Standard Downstream USB 2.0 Port (SDP)
Peripheral Peripheral
can supply power up to 500 mA at 5 V, whereas a Charging
device 4 device 5
Downstream USB 2.0 Port (CDP) can supply power up to 1500
mA at 5 V. It is sufficient to operate low power devices. Mini Fig. 2.32 USB Device Connection topology
and Micro USB connectors are available for small form factor
devices like portable media players and Smartphones. Each USB device contains a Product ID (PID) and a
Vendor ID (VID). The PID and VID are embedded into the USB chip by the USB device manufacturer. The
VID for a device is supplied by the USB standards forum. PID and VID are essential for loading the drivers
corresponding to a USB device for communication.
USB supports four different types of data transfers, namely; Control, Bulk, Isochronous and Interrupt.
Control transfer is used by USB system software to query, configure and issue commands to the USB
device. Bulk transfer is used for sending a block of data to a device. Bulk transfer supports error checking and
correction. Transferring data to a printer is an example for bulk transfer. Isochronous data transfer is used for
real-time data communication. In Isochronous transfer, data is transmitted as streams in real-time. Isochronous
transfer doesn’t support error checking and re-transmission of data in case of any transmission loss. All
streaming devices like audio devices and medical equipment for data collection make use of the isochronous
transfer. Interrupt transfer is used for transferring small amount of data. Interrupt transfer mechanism makes
use of polling technique to see whether the USB device has any data to send. The frequency of polling is
determined by the USB device and it varies from 1 to 255 milliseconds. Devices like Mouse and Keyboard,
which transmits fewer amounts of data, makes use of Interrupt transfer.
USB 3.x is the latest version of the USB standard for peripheral connectivity. USB 3.x brings a number of
improvements over USB 2.0, and adds a new transfer mode called SuperSpeed (SS), capable of transferring
data at speeds up to 4.8 Gbps, which is more than ten times as fast as the 480 Mbps high speed of USB 2.0.
USB 3.x uses an entirely different set of Type A & B physical connectors compared to USB 2.0
connectors. Both Type A and Type B USB 3.0 connectors contain 9 pins. Similar to the USB 2.0 connector,
3.0 connectors include VBUS, Differential data pair (D−, D+), and GND. In addition to these pins, USB
3.0 connectors include two additional differential pairs (StdA_SSRX−, StdA_SSRX+ and StdA_SSTX−,
StdA_SSTX+; StdB_SSRX−, StdB_SSRX+ and StdB_SSTX− StdB_SSTX+,) for Superspeed data transfer
 The Typical Embedded System 55

and an associated ground (GND_DRAIN). USB 3.0 also introduced a new Micro-B connector, which is a
combination of the standard USB 2.0 Micro-B connector side by side with an additional 5-pin plug. USB
Type-C is a small, compact and reversible plug connector for USB devices and USB cabling. It replaces the
standard USB Type-A and B connections as well as the myriad of micro and mini USB ports. It supports
various new USB standard like USB 3.1 and USB power delivery (USB PD) and also a variety of different
protocols using “alternate modes,” which allows outputting HDMI, VGA, Display Port, or other types of
connections from the single USB Type C port through adapters.
USB.ORG (www.usb.org) is the standards body for defining and controlling the standards for USB
communication. Presently USB supports different data rates namely; Low Speed (1.5Mbps), Full Speed
(12Mbps), High Speed (480Mbps) , SuperSpeed (5Gbps) and SuperSpeed + (or SuperSpeed USB 10 Gbps).
The Low Speed and Full Speed specifications are defined by USB1.0 and the High Speed specification
is defined by USB 2.0. USB 3.0 defines the specifications for Super Speed. Wireless USB is the wireless
extension to USB based on Ultra Wide Band (UWB) technology for data transmission. Wireless USB
combines the speed and security of wired USB technology with the ease-of-use of wireless technology.
2.4.2.3 IEEE 1394 (Firewire) IEEE 1394 is a wired, isochronous high speed serial communication bus.
It is also known as High Performance Serial Bus (HPSB). The research on 1394 was started by Apple Inc.
in 1985 and the standard for this was coined by IEEE. The implementation of it is available from various
players with different names. Apple Inc’s (www.apple.com) implementation of 1394 protocol is popularly
known as Firewire. i.LINK is the 1394 implementation from Sony Corporation (www.sony.net) and Lynx is
the implementation from Texas Instruments (www.ti.com). 1394 supports peer-to-peer connection and point-
to-multipoint communication allowing 63 devices to be connected on the bus in a tree topology. 1394 is a
wired serial interface and it can support a cable length of up to 15 feet for interconnection.
The 1394 standard has evolved a lot from the first version IEEE 1394–1995 released in 1995 to the
recent version IEEE 1394–2008 released in June 2008. The 1394 standard supports a data rate of 400 to
3200Mbits/second. The IEEE 1394 uses differential data transfer (The information is sent using differential
signals through a pair of twisted cables. It increases the noise immunity) and the interface cable supports 3
types of connectors, namely; 4-pin connector, 6-pin connector (alpha connector) and 9 pin connector (beta
connector). The 6 and 9 pin connectors carry power also to support external devices (In case an embedded
device is connected to a PC through an IEEE 1394 cable with 6 or 9 pin connector interface, it can operate
from the power available through the connector.) It can supply unregulated power in the range of 24 to 30V.
(The Apple implementation is for battery operated devices and it can supply a voltage in the range 9 to 12V.)
The table given below illustrates the pin details for 4, 6 and 9 pin connectors.
Pin name Pin no: (4 Pin Pin no: (6 Pin Pin no: (9 Pin Description
Connector) Connector) Connector)
Power 1 8 Unregulated DC supply. 24 to 30V
Signal Ground 2 6 Ground connection
TPB– 1 3 1 Differential Signal line for Signal line B
TPB+ 2 4 2 Differential Signal line for Signal line B
TPA– 3 5 3 Differential Signal line for Signal line A
TPA+ 4 6 4 Differential Signal line for Signal line A
TPA(S) 5 Shield for the differential signal line A.
Normally grounded
TPB(S) 9 Shield for the differential signal line B.
Normally grounded
NC 7 No connection
56 Introduc on to Embedded Systems

There are two differential data transfer lines A and B per connector. In a 1394 cable, normally the
differential lines of A are connected to B (TPA+ to TPB+ and TPA–to TPB–) and vice versa.
1394 is a popular communication interface for connecting embedded devices like Digital Camera,
Camcorder, Scanners to desktop computers for data transfer and storage.
Unlike USB interface (Except USB OTG), IEEE 1394 doesn’t require a host for communicating between
devices. For example, you can directly connect a scanner with a printer for printing. The data-rate supported
by 1394 is far higher than the one supported by USB2.0 interface. The 1394 hardware implementation is
much costlier than USB implementation.
2.4.2.4 Infrared (IrDA) Infrared (IrDA) is a serial, half duplex, line of sight based wireless technology
for data communication between devices. It is in use from the olden days of communication and you may be
very familiar with it. The remote control of your TV, VCD player, etc. works on Infrared data communication
principle. Infrared communication technique uses infrared waves of the electromagnetic spectrum for
transmitting the data. IrDA supports point-point and point-to-multipoint communication, provided all devices
involved in the communication are within the line of sight. The typical communication range for IrDA lies in
the range 10 cm to 1 m. The range can be increased by increasing the transmitting power of the IR device. IR
supports data rates ranging from 9600bits/second to 16Mbps. Depending on the speed of data transmission
IR is classified into Serial IR (SIR), Medium IR (MIR), Fast IR (FIR), Very Fast IR (VFIR), Ultra Fast IR
(UFIR) and GigaIR. SIR supports transmission rates ranging from 9600bps to 115.2kbps. MIR supports data
rates of 0.576Mbps and 1.152Mbps. FIR supports data rates up to 4Mbps. VFIR is designed to support high
data rates up to 16Mbps. The UFIR supports data rates up-to 96Mbps, whereas the GigaIR supports data rates
512 Mbps to 1 Gbps.
IrDA communication involves a transmitter unit for transmitting the data over IR and a receiver for
receiving the data. Infrared Light Emitting Diode (LED) is the IR source for transmitter and at the receiving
end a photodiode acts as the receiver. Both transmitter and receiver unit will be present in each device
supporting IrDA communication for bidirectional data transfer. Such IR units are known as ‘Transceiver’.
Certain devices like a TV remote control always require unidirectional communication and so they contain
either the transmitter or receiver unit (The remote control unit contains the transmitter unit and TV contains
the receiver unit).
‘Infra-red Data Association’ (IrDA - http://www.irda.org/) is the regulatory body responsible for defining
and licensing the specifications for IR data communication. IrDA communication has two essential parts; a
physical link part and a protocol part. The physical link is responsible for the physical transmission of data
between devices supporting IR communication and protocol part is responsible for defining the rules of
communication. The physical link works on the wireless principle making use of Infrared for communication.
The IrDA specifications include the standard for both physical link and protocol layer.
The IrDA control protocol contains implementations for Physical Layer (PHY), Media Access Control
(MAC) and Logical Link Control (LLC). The Physical Layer defines the physical characteristics of
communication like range, data rates, power, etc.
IrDA is a popular interface for file exchange and data transfer in low cost devices. IrDA was the prominent
communication channel in mobile phones before Bluetooth’s existence. Even now most of the mobile phone
devices support IrDA.
2.4.2.5 Bluetooth (BT) Bluetooth is a low cost, low power, short range wireless technology for data and
audio communication. Bluetooth was first proposed by ‘Ericsson’ in 1994. Bluetooth operates at 2.4GHz
of the Radio Frequency spectrum and uses the Frequency Hopping Spread Spectrum (FHSS) technique for
communication. Literally it supports a data rate of up to 1Mbps to 24Mbps (and a range of approximately
 The Typical Embedded System 57

30 to 100 feet (Depending on the Bluetooth version – v1.2 supports datarate up to 1Mbps, v2.0 + EDR
supports datarate up to 3Mbps, v3.0 + HS and v4.0 supports datarate up to 24Mbps)) for data communication.
Like IrDA, Bluetooth communication also has two essential parts; a physical link part and a protocol part.
The physical link is responsible for the physical transmission of data between devices supporting Bluetooth
communication and protocol part is responsible for defining the rules of communication. The physical
link works on the Wireless principle making use of RF waves for communication. Bluetooth enabled
devices essentially contain a Bluetooth wireless radio for the transmission and reception of data. The rules
governing the Bluetooth communication is implemented in the ‘Bluetooth protocol stack’. The Bluetooth
communication IC holds the stack. Each Bluetooth device will have a 48 bit unique identification number.
Bluetooth communication follows packet based data transfer. Bluetooth supports point-to-point (device to
device) and point-to-multipoint (device to multiple device broadcasting) wireless communication. The point-
to-point communication follows the masterslave relationship. A Bluetooth device can function as either
master or slave. When a network is formed with one Bluetooth device as master and more than one device as
slaves, it is called a Piconet. A Piconet supports a maximum of seven slave devices.
Bluetooth is the favourite choice for short range data communication in handheld embedded devices.
Bluetooth technology is very popular among cell phone users as they are the easiest communication channel
for transferring ringtones, music files, pictures, media files, etc. between neighboring Bluetooth enabled
phones. Bluetooth Low Energy (BLE)/Bluetooth Smart is a latest addition to the Bluetooth technology. BLE
allows devices to use much less power compared to the standard Bluetooth connections, while offering most
of the connectivity of Bluetooth and maintaining a similar communication range.
Bluetooth 4.2 specification enables IoT support through Low-power IP connectivity, with support for
flexible Internet connectivity options (IPv6/6LoWPAN or Bluetooth Smart Gateways) and implements
industry-leading privacy, power efficiency and industry standard security
The Bluetooth standard specifies the minimum requirements that a Bluetooth device must support for a
specific usage scenario. The Generic Access Profile (GAP) defines the requirements for detecting a Bluetooth
device and establishing a connection with it. All other specific usage profiles are based on GAP. Serial Port
Profile (SPP) for serial data communication, File Transfer Profile (FTP) for file transfer between devices,
Human Interface Device (HID) for supporting human interface devices like keyboard and mouse are examples
for Bluetooth profiles. BLE implements various application specific profiles for communicating with low
power Bluetooth peripherals like fitness devices, Blood Pressure and heart rate monitors etc. Healthcare
Profiles (HTP, GLP, BLP etc.), Sports and Fitness Profiles (HRP, LNP, RNCP etc.) etc. are examples for this.
The specifications for Bluetooth communication is defined and licensed by the standards body ‘Bluetooth
Special Interest Group (SIG)’. For more information, please visit the website www.bluetooth.org

2.4.2.6 Wi-Fi Wi-Fi or Wireless Fidelity is the popular wireless communication technique for networked
communication of devices. Wi-Fi follows the IEEE 802.11 standard. Wi-Fi is intended for network
communication and it supports Internet Protocol (IP) based communication. It is essential to have device
identities in a multipoint communication to address specific devices for data communication. In an IP based
communication each device is identified by an IP address, which is unique to each device on the network.
Wi-Fi based communications require an intermediate agent called Wi-Fi router/Wireless Access point to
manage the communications. The Wi-Fi router is responsible for restricting the access to a network, assigning
IP address to devices on the network, routing data packets to the intended devices on the network. Wi-Fi
enabled devices contain a wireless adaptor for transmitting and receiving data in the form of radio signals
through an antenna. The hardware part of it is known as Wi-Fi Radio. Wi-Fi operates at 2.4GHz or 5GHz of
radio spectrum and they co-exist with other ISM band devices like Bluetooth. Figure 2.33 illustrates the
58 Introduc on to Embedded Systems

typical interfacing of devices in a Wi-Fi Wi-Fi router

network. For communicating with devices over
a Wi-Fi network, the device when its Wi-Fi
radio is turned ON, searches the available Wi-
Fi network in its vicinity and lists out the
Service Set Identifier (SSID) of the available
networks. If the network is security enabled, a
password may be required to connect to a
particular SSID. Wi-Fi employs different security
mechanisms like Wired Equivalency Privacy
(WEP) Wireless Protected Access (WPA), etc.
for securing the data communication. Wi-Fi
supports data rates ranging from 1Mbps to
1300Mbps (Growing towards higher rates as Device 1
technology progresses), depending on the
Device 3
standards (802.11a/b/g/n/ac) and access/ Device 2
modulation method. Depending on the type of
Fig. 2.33 Wi-Fi network
antenna and usage location (indoor/outdoor),
Wi-Fi offers a range of 100 to 1000 feet.

2.4.2.7 ZigBee ZigBee is a low power, low cost, wireless network communication protocol based on
the IEEE 802.15.4-2006 standard. ZigBee is targeted for low power, low data rate and secure applications
for Wireless Personal Area Networking (WPAN). The ZigBee specifications support a robust mesh network
containing multiple nodes. This networking strategy makes the network reliable by permitting messages to
travel through a number of different paths to get from one node to another.
ZigBee operates worldwide at the unlicensed bands of Radio spectrum, mainly at 2.400 to 2.484 GHz,
902 to 928 MHz and 868.0 to 868.6 MHz. ZigBee Supports an operating distance of up to 100 metres and a
data rate of 20 to 250Kbps.
In the ZigBee terminology, each ZigBee device falls under any one of the following ZigBee device category.
ZigBee Coordinator (ZC)/Network Coordinator The ZigBee coordinator acts as the root of the ZigBee
network. The ZC is responsible for initiating the ZigBee network and it has the capability to store information
about the network.
ZigBee Router (ZR)/Full func on Device (FFD) Responsible for passing information from device to another
device or to another ZR.
ZigBee End Device (ZED)/Reduced Func on Device (RFD) End
device containing ZigBee functionality for data communication. It
can talk only with a ZR or ZC and doesn’t have the capability to act
as a mediator for transferring data from one device to another.
The diagram shown in Fig. 2.34 gives an overview of ZC, ZED
and ZR in a ZigBee network.
ZigBee is primarily targeting application areas like home &
industrial automation, energy management, home control/security,
medical/patient tracking, logistics & asset tracking and sensor
networks & active RFID. Automatic Meter Reading (AMR), smoke
detectors, wireless telemetry, HVAC control, heating control, Fig. 2.34 A ZigBee network model
 The Typical Embedded System 59

lighting controls, environmental controls, etc., are examples for applications which can make use of the
ZigBee technology.
ZigBee PRO offers full wireless mesh, low-power networking capable of supporting more than 64,000
devices on a single network. It provides standardised networking designed to connect the widest range of
devices, in any industry, into a single control network. ZigBee PRO offers an optional new and innovative
feature, ‘Green Power’ to connect energy harvesting or self-powered devices into ZigBee PRO networks.
The ‘Green Power’ feature of ZigBee PRO is the most eco-friendly way to power battery-less devices such as
sensors, switches, dimmers and many other devices and allows them to securely join ZigBee PRO networks.
ZigBee 3.0 delivers all the features of ZigBee while unifying the ZigBee application standards found in
ZigBee devices. ZigBee 3.0 standard enables communication and interoperability among devices for smart
homes, connected lighting, and other markets.
The specifications for ZigBee is developed and managed by the ZigBee alliance (www.zigbee.org), a
non-profit consortium of leading semiconductor manufacturers, technology providers, OEMs and end-users
worldwide.
2.4.2.8 General Packet Radio Service (GPRS), 3G, 4G, LTE General Packet Radio Service (GPRS),
3G, 4G and LTE are cellular communication technique for transferring data over a mobile communication
network like GSM and CDMA. Data is sent as packets in GPRS communication. The transmitting device splits
the data into several related packets. At the receiving end the data is re-constructed by combining the received
data packets. GPRS supports a theoretical maximum transfer rate of 171.2kbps. In GPRS communication,
the radio channel is concurrently shared between several users instead of dedicating a radio channel to a
cell phone user. The GPRS communication divides the channel into 8 timeslots and transmits data over the
available channel. GPRS supports Internet Protocol (IP), Point to Point Protocol (PPP) and X.25 protocols
for communication. GPRS is mainly used by mobile enabled embedded devices for data communication.
The device should support the necessary GPRS hardware like GPRS modem and GPRS radio. To accomplish
GPRS based communication, the carrier network also should have support for GPRS communication. GPRS
is an old technology and it is being replaced by new generation cellular data communication techniques
like 3G (3rd Generation), High Speed Downlink Packet Access (HSDPA), 4G (4th Generation), LTE (Long
Term Evolution) etc. which offers higher bandwidths for communication. 3G offers data rates ranging from
144Kbps to 2Mbps or higher, whereas 4G gives a practical data throughput of 2 to 100+ Mbps depending on
the network and underlying technology.

2.5 EMBEDDED FIRMWARE

Embedded firmware refers to the control algorithm (Program instructions) and
LO 5 Describe what
or the configuration settings that an embedded system developer dumps into the
embedded firmware
code (Program) memory of the embedded system. It is an un-avoidable part of
is and its role in
an embedded system. There are various methods available for developing the
embedded systems
embedded firmware. They are listed below.
(1) Write the program in high level languages like Embedded C/C++ using an Integrated Development
Environment (The IDE will contain an editor, compiler, linker, debugger, simulator, etc. IDEs are
different for different family of processors/controllers. For example, Keil micro vision3 IDE is used
for all family members of 8051 microcontroller, since it contains the generic 8051 compiler C51).
(2) Write the program in Assembly language using the instructions supported by your application’s
target processor/controller.
The instruction set for each family of processor/controller is different and the program written in either of
the methods given above should be converted into a processor understandable machine code before loading
it into the program memory.