A C ircu it for All Seasons

Behzad Razavi

The Current-Steering DAC

D
Digital-to-analog converters (DACs) component, as in displays and opti- voltage experiences large fluctua-
find application in many systems, cal modulators. tions in the presence of parasitic se-
including communication trans- The current-switching structure ries inductances, such as those due
mitters and consumer electronics. shown in Figure 1(a) suffers from to bond wires.
Among various DAC realizations, the dynamic errors. As depicted in Fig­­ Both of these effects can be greatly
current-steering topology offers the ure 1(b), when a switch turns off, the suppressed through the use of current
highest speed and becomes the de top terminal voltage of its correspond- steering (Figure 2). Here, the tail cur-
facto solution at gigahertz frequen- ing current source collapses to zero. rent is steered to the left or the right
cies, especially if the analog output Thus, the next time that this branch is by each differential pair, causing only a
must be delivered to a resistive load. enabled, the (nonlinear) capacitance at small voltage excursion at node X. Also,
In this article, we study this DAC’s de- this terminal must charge up, draw- since the total array current is relatively
sign principles. ing a significant transient current constant, the ground bounce is much
from the output node. Moreover, since smaller. Of course, another advantage
Basic Topology switching actions change the total cur- of this configuration is that it naturally
We wish to convert an N -b digital rent carried by the array, the ground provides differential outputs.
signal, D in, to an analog current, I out.
This can be accomplished as illus-
trated in Figure 1(a), where each input
bit controls a current that is binarily Iout
weighted with respect to a unit value,
I u. Here, D 1 denotes the least signifi-
cant bit (LSB) and D N the most signifi- D1 D2 DN VX
X
cant bit (MSB). The current sources are ...
X CX
Vb
scaled up by a factor of two from one Iu 2Iu 2N –1Iu
bit to the next, yielding t

(a) (b)
I out =D N (2 N -1 I u) +g+D 2 (2I u) +D 1 I u .(1)

Figure 1: (a) A simple binary-weighted current-switching DAC and (b) the problem of
This circuit is an example of a simple
­discharge at X when the switch is off.
binary-weighted DAC. We can also
call it a current-switching—but not a
current-steering—implementation.
An important advantage of this +
Iout
DAC over other types is its ability
to drive resistive loads with no need –
Iout
for a buffer. This property proves M1 M2
D1 D2 ... DN
crucial if the DAC must drive a trans-
X Iu 2Iu 2N –1Iu
mission line, as in wireline systems,
Vb
or if the load contains a resistive W
M3 2W 2N –1W
L L L
Digital Object Identifier 10.1109/MSSC.2017.2771102
Date of publication: 31 January 2018 Figure 2: A binary-weighted current-steering DAC.

IEEE SOLID-STATE CIRCUITS MAGAZINE W i n t e r 2 0 18 11

 and 2 N -2 I u current sources for the
VDD VDD VDD former code and by the 2 N -1 I u cur-
+ + +
RL Vmax RL Vmax rent source for the latter. The differ-
R0 R0lSS
– – – ence is nominally equal to 1 LSB = I u,
RD RD
VDD Dj M 1 M2 Dj M1 M2 but, with mismatches present in the
circuit, it is possible that the sum
0 X X
Dj
of t he for mer g r oup is subst a n -
M3 tially different from 2 N -1 I u - I u . As
M3 lSS
VDD
a result, the DAC input–output char-
acteristic can exhibit a large error
or nonmonotonicity at this transi-
t tion (Figure 4). The fundamental
(a) (b) difficulty here is that, at this “major
carry” transition, a group of current
Figure 3: A DAC cell with (a) rail-to-rail or (b) moderate digital swings. sources turns off and a new current
source turns on.
For proper matching among the The foregoing issue can be avoided
current sources, we design a unit cell by “segmentation.” For an N -b DAC,
Iout comprising a current source and a we still incorporate 2 N - 1 unit cells
differential pair and repeat this cell but apply a different switching se-
to form larger cells. That is, cell num- quence. As shown in Figure 5, for a
ber j consists of 2 j -1 unit cells in binary input 000g01, one cell is ac-
parallel, and the entire DAC contains tivated; for 00g10, two; for 00g11,
2 N - 1 unit cells. three; etc. We say the cells are driven
One drawback of current-steering by a “thermometer code.” For exam-
DACs is their limited output voltage ple, as the binary input goes from 01
011111
100000

Din
compliance. In Figure 2, for example, to 10 to 11, the corresponding ther-
the differential-pair transistors must mometer code changes from 0001 to
Iout operate in saturation (as explained 0011 to 0111.
below), and, therefore, at least two The segmented architecture avoids
drain-source voltages are subtracted the jumps shown in Figure 4 because,
from the supply, VDD. at the major carry transition, it sim-
Another difficulty in the design is ply turns on one more LSB cell, rather
the choice of the digital input volt- than turn off one group of current
age excursions. The most convenient sources. Thus, the output changes
are rail-to-rail swings, but, as shown monotonically, and the jump is not
011111
100000

Din in Figure 3(a), such a choice 1) limits much different from 1 LSB as the new
the analog output voltage range Vmax cell has some matching with respect
to one transistor threshold if M 1 to the previous cells. In practice, of
Figure 4: Large jumps or nonmonotonicity must remain in saturation and 2) course, each cell is based on a current-
in binary-weighted DAC characteristics due leads to large dips in VX during the steering structure.
to mismatches. transitions of D j and D j . In other
words, we would prefer only a mod- Partial Segmentation
erate swing for the digital inputs, We have seen that the number of unit
with a maximum level less than VDD cells is the same for binary and seg-
so as to allow a greater Vmax. Such mented architectures and becomes
2N – 1 Units Iout swings call for another differential prohibitively large at high resolu-
pair [Figure 3(b)] and hence substan- tions. For example, a 10-b DAC would
tial power consumption. require 1,023 cells, facing severe
X ...
Iu Iu Iu area and routing issues. We note,
The Need for Segmentation however, that the matching require-
The binary-weighted arrays in Fig- ments are more relaxed for the LSB
Binary−Thermometer Decoder
ure 1(a) or Figure 2 can face undesir- current sources: even if the first and
able jumps in their output when the second LSB currents have a mismatch
Binary Input digital input goes from 011g1 to of 10%, the overall characteristic can
10g0. We observe that the output still reach 10-b precision. Let us con-
Figure 5: A segmented DAC. current is provided by the I u, 2I u, f, sider the following approach: rather

12 W i n t e r 2 0 18 IEEE SOLID-STATE CIRCUITS MAGAZINE

than copy currents by means of unit
cells, we seek a method of dividing Binary Section
Segmented Section
currents by binary factors. For exam- LSB3 LSB2 LSB1
ple, we can keep doubling the length lu lu
of the current-source transistors, as lu lu lu 2 4
lu lu W
shown in Figure 6(a). However, the lu W W W W
vb 4 2 ... L L
L L L
effective length does not double, cre- W W
W W W
ating significant errors. Instead, we 4L 2L L L L
vb W
place identical transistors in series (a) L
[Figure 6(b)]. The resulting architec- W
ture is called a “partially segmented L
DAC” to emphasize that only the MSB
(b)
section is segmented.
The exact partitioning of the DAC
Figure 6: (a) Binary weighting by doubling transistor lengths and (b) a partially segmented
into segmented and binary sections DAC employing transistors in series.
depends on the matching properties
of the transistors; the binary array
can still suffer from effects shown
in Figure 4. In a typical design, we
Iout
use binary weighting for the first
three or four LSBs and segmentation
for the remaining bits. ...
INLmax vb
P
Static Errors ...
Current-steering DACs must deal with
Din
three types of static errors. First, the (a) (b)
random mismatches among the cur-
VDD
rent sources distort the input–output
RL
characteristic. These mismatches Iout
Vout
accumulate and primarily manifest
themselves in the form of integral
nonlinearity (INL) in segmented to- ...
pologies. Illustrated in Figure 7(a),
Iu ro Iu ro Iu ro
the INL is defined as the error be-
tween the actual characteristic and Din
(c) (d)
a straight line passed through its
points. Second, the voltage drop along
the ground line traveling to the cur- Figure 7: (a) An illustration of INL, (b) the effect of ground line IR drops, (c) the effect of
output impedance of current sources, and (d) a compressed characteristic arising from (c).
rent cells can cause significant deter-
ministic nonlinearity. As depicted in
Figure 7(b), if a large number of cells
inject current into a long ground line, voltage change equal to I u (R L | | rO) Since differential operation sup-
the voltage at the farthest point from and the last, I u [R L | | (rO /M )]. Due presses even harmonics, we expect
ground, P, can reach tens of milli- to this code-dependent output resis- the differential counterpart of the
volts. With a nominal overdrive volt- tance, the input– output charac- array in Figure 7(c) to achieve a higher
age of, say, 200 mV for the current teristic exhibits compression as linearity or, for a given INL, require a
sources, the ground drop introduces D in increases [Figure 7(d)]. It can be less stringent output resistance.
excessive nonlinearity. shown that the maximum INL aris-
The third static error relates to the ing from this effect is given by Dynamic Errors
finite output resistance of the cells I u R 2L M 2 / (4rO), which, normalized to The current-steering DAC of Figure 2
if the DAC must drive a resistance. the full-scale output voltage, is ap- also suffers from dynamic errors,
From Figure 7(c), we observe that the proximately equal to MR L / (4rO). For and hence greater distortion, at high
incremental resistance at the output example, if M = 1024 and R L = 50 X, output frequencies. We examine three
node varies from R L | | rO when only then rO must exceed 12.8 MX for the such errors here.
one cell turns on to R L | | (rO /M ) when INL to remain below 0.1%. Such an The tail node capacitance in Fig-
all M cells turn on. In other words, extremely high output impedance is ure 2 introduces nonlinearity—even
the first current source produces a difficult to obtain in practice. though the voltage swing at this node

IEEE SOLID-STATE CIRCUITS MAGAZINE W i n t e r 2 0 18 13

is typically lower than 100 mV. The disturbs the bias current of the cells, where N is the resolution [3]. We
capacitance, C X , degrades the per- thus increasing the output settling also know that for two nominall y
formance through t wo mecha- time. The principal difficulty here is identical MOS current sources that
nisms [1]. First, it simply appears in that even a few millivolts of change in have relatively large dimens i o n s ,
parallel with the tail current source, Vb translate to an output disturbance v I /I u =2v VTH /(VGS -VTH ), where v VTH
lowering the unit cell output imped- of many LSBs. One can contemplate denotes the threshold m ism atch,
ance and exacerbating the code-de- the use of a bypass capacitor at Vb, and v VTH = A VTH / WL , where A VTH
pendent output impedance described but this capacitor also slows down the is a process-dependent parameter,
in the previous section. It can be settling at this node. Another remedy e.g., around 6 mV·nm. We must, there-
shown that the nth harmonic at the is to add a cascode device atop the fore, choose WL and VGS - VTH large
output has a relative magnitude giv- current sources while losing voltage enough to ensure the random INL max is
en by [MR L / (4 | Z u |)] n -1, where Z u headroom. lower than 0.5 LSB. In a typical design,
denotes the complex output imped- The third dynamic error in current- VGS - VTH is limited to 200–300 mV,
ance of the unit cell [1]. steering DACs stems from mismatches imposing a large unit transistor if
The second mechanism related to between the times at which the data resolutions of 8 b or higher are sought.
the tail capacitance involves charge edges reach the unit cells. To minimize For example, with N = 10, VGS -
transfer from one clock cycle to an- this error, each cell is preceded by a VTH = 200 mV, and A VTH = 6 mV·nm,
other [1]. As illustrated in Figure 8, latch, but clock skews and random we have WL = 1.8 nm 2. We then choose
when D j = 1, C X charges to a voltage mismatches between the latches still a large value for L to minimize the non-
that, due to rO, depends on V +out (t 1). limit the performance [2]. linearity due to the output resistances.
Now, some clock cycles later, D j goes If the cascode comprising M 1 and
to zero and VX must now change so Design Procedure M 3 in Figure 2 still does not yield
as to track V -out (t 2), which can be very The design of a current-steering DAC INL max = 2 N R L / (4rO) 1 0.5 LSB, we can
different from V +out (t 1). For this change begins with the unit cell. We must introduce a cascode device atop M 3 .
to occur, C X must receive some charge size and bias the tail current source To ensure fast switching and mini-
equal to C X (V2 - V1) from V -out, caus- so as to guarantee a maximum static mal capacitance at the tail node, the
ing a dynamic error at the output. INL of lower than 1 LSB due to both switching transistors are designed
Another type of dynamic error random mismatches and the code- with the minimum channel length.
arises in Figure 2 from the coupling dependent output resistance. It can We note that C X Figure 2 is given
of the tail nodes to the bias line, Vb, be shown that, for a random change by C GS1, 2 + C GD3 + C DB3 . The width of
through the gate-drain capacitance of v I in the unit current, I u, M 1 and M 2 is chosen so as to obtain
of the current sources. Depicted in a small overdrive voltage, around
Figure 9, the resulting jump in Vb INL max = v I 2 N LSB, (2) 50 –100 mV. As mentioned above,
2I u
this pair is preceded by a latch in
every cell.

VDD VDD The Matrix Architecture

Dj = 1 RL RL Dj = 0 RL RL Suppose we wish to design an 8-b
+
Vout(t1) –
fully segmented DAC. How do we ar-
Vout(t2) range the 255 cells while distribut-
ro ro
ing the data, clock, and power with
X X
+ + minimal parasitics? Proposed by
CX V CX V
– 1 – 2 [4], an elegant approach arranges
the unit cells in a compact matrix,
making the distribution much more
Figure 8: Dynamic distortion due to the dependence of VX on output voltages.
manageable than in a linear array.
As illustrated in Figure 10, the archi-
tecture consists of a column decod-
er, a row decoder, and 2 N unit cells,
each containing local logic, a cur-
M1 M2 rent source, and a switching pair.
D1 D2 . . . DN
(In high-speed designs, a latch also
Vb appears between the logic and the
pair.) We describe the operation for a
M3 resolution of 6 b as an example. The
input binary data D 6 D 5 D 4 D 3 D 2 D 1 is
Figure 9: A long settling time due to feedthrough of jumps at the tail node to the bias line. decomposed into two binary words

14 W i n t e r 2 0 18 IEEE SOLID-STATE CIRCUITS MAGAZINE

 D3 D2 D1

Column Decoder
Row Column
Thermometer Code Thermometer Code

D4

Row Decoder
Local
D5 Decoder

D6

Figure 10: The matrix DAC architecture.

+
Tb –
Din + Dout
+h1

MUX
Din D Q Dout
h1 –h1

– Select
DF + CK

Figure 11: A simple DFE loop. Figure 12: An unrolled DFE architecture.

D 6 D 5 D 4 and D 3 D 2 D 1 , with one ap- impedance of the current sourc- Yes, it can. We must add another
plied to the row decoder and the es is considered? flip-flop after the first, scale its out-
other to the column decoder. These 2) In the matrix architecture of Fig- put according to the value of the
words are converted to thermom- ure 10, each row experiences the second tap, and inject the result
eter codes that travel horizontally same gradient from left to right. to both summers. Alternatively, we
and vertically within the matrix. If each cell current is higher than can return the result to a summer
Each cell senses the row and column the one to its left by DI, what is inserted at the very input.
thermometer code values to deter- the maximum INL?
mine whether the current should be References
[1] P. Palmers and M. S. J. Steyaert, “A 10-bit
on or off. The local decoder senses Answers to Last Issue’s Questions 1.6-GS/s 27-mW current-steering D/A con-
the thermometer codes of two con- 1) Can the delay stage and the slic- verter with 550-MHz 54-dB SFDR band-
width in 130-nm CMOS,” IEEE J. Solid-State
secutive rows and one column to er in Figure 11 be realized as a Circuits, vol. 57, pp. 2870 –2879, Nov.
distinguish among three cases: 1) all single limiting differential pair? 2000.
[2] K. L. Chan and I. Galton, “A 14b 100MS/s
cells in a row are on, 2) all cells in a If the total delay is chosen equal DAC with fully segmented dynamic ele-
row are off, and 3) some cells in a row to 1 UI, yes, it can. However, the ment matching,” in Proc. Int. Solid State
Circuits Conf. Dig. Tech. Papers, Feb. 2006,
are on [4]. gain may not suffice to amplify the pp. 214–215.
summer output to logical levels. [3] C.-H. Lin and K. Bult, “A 10-b 500MS/s
CMOS DAC in 0.6 mm2,” IEEE J. Solid-State
Questions for the Reader Also, the delay of such an asyn- Circuits, vol. 33, pp. 1948–1958, Dec. 1998.
1) By what factor is the INL of a dif- chronous stage varies with process [4] T. Miki, “An 80-MHz 8-bit CMOS D/A con-
verter,” IEEE J. Solid-State Circuits, vol. 21,
ferential current-steering DAC and temperature. pp. 983–988, Dec. 1986.
lower than that of a single-ended 2) Can the unrolled DFE of Figure 12
topology if only the finite output accommodate a second tap? 

IEEE SOLID-STATE CIRCUITS MAGAZINE W i n t e r 2 0 18 15