1129128, 759.AM study viewer Analog Electronics Circuits FET small signal Analysis Nagamani AN Lecturer, PESIT, Bangalore — 85 Email — [email protected] FET small signal Analysis FET introduction and working principles FET small signal analysis FET self bias technique. Examples JFET self bias configuration Numerical IFET Voltage divider configuration JFET common drain configuration Source follower. Numerical JEET common gate Depletion mode Enhancement mode E MOSFET drain feedback configuration. E MOSFET voltage divider Configuration. numerical -ntpsufstudylb.netidoc/1882601 7uni-5 vise 401129128, 759.AM study viewer FET Introduction * The Field-Effect Transistor (FET) is a type of transistor that works by modulating a microscopic electric field inside a semiconductor material. + There are two general type of FET's, the MOSFET and JFET. Symbol and representation D D Ss GS TO-92 Ss n-channel JFET Sb n-channel JFET JFET Construction ‘There are two types of JFET’s: n-channel and p-chennel. The n-channel is more widely used. 9 Drain (D) channel Gime @) & source (5) -ntpsufstudylb.netidoc/1882601 7uni-5 vise 21401129128, 759.AM study viewer Basic operation of JFET * The JFET operation is compared with the water spigot. The source of water pressure * accumulated electrons at the negative pole of the applied voltage from Drain to Source The drain of water * electron deficiency (or holes) at the positive pole of the applied voltage from Drain to Source. The control of flow of water * Gate voltage that controls the width of the n-channel, which in turn controls the flow of electrons in the n-channel from source to drain. SD dvi: JFET Operating Characteristics There are three basic operating conditions for a JFET: A. VGS = 0, VDS increasing to some positive value B. VGS < 0, VDS at some positive value C. Voltage-Controlled Resistor tpsstudylib neidoc!18826017/unit5—vtuse ia1129128, 759.AM study viewer A. VGS = 0, VDS increasing to some positive value Three things happen when VGS = 0 and VDS is increased from 0 to a more positive voltage: * The depletion region between p-gate and n-channel increases as electrons from n-channel combine with holes from p-gate. Increasing the depletion region, decreases the size of the n-channel which increases the resistance of the n-channel. + But even though the n-channel resistance is increasing, the current (ID) from Source to Drain Through the n-channel is increasing. This is because VDS is increasing. -ntpsufstudylb.netidoc/1882601 7uni-5 vise 4401129128, 759.AM study viewer Pinch off Saturation -ntpsufstudylb.netidoc/1882601 7uni-5 vise1129128, 759.AM study viewer At the pinch-off point: * any further increase in VGS does not produce any increase in ID. VGS at pinch-off is denoted as Vp. + ID is at saturation or maximum. It is referred to as IDSS. * The ohmic value of the channel is at maximum. B. VGS <0, VDS at some positive value ‘As VGS becomes more negative the depletion region increases. -ntpsufstudylb.netidoc/1882601 7uni-5 vise eia01129128, 759.AM study viewer Now Id < Idss As VGS becomes more negative: + the JFET will pinch-off at a lower voltage (Vp). + ID decreases (ID < IDSS) even though VDS is increased. + Eventually ID will reach 0A. VGS at this point is called Vp or VGS(oft). Also note that at high levels of VDS the JFET reaches a breakdown. situation. ID will increases uncontrollably if VDS > VDSmax C. Voltage-Controlled Resistor + The region to the left of the pinch-off point is called the ohmic region. + The JFET can be used as a variable resistor, where VGS controls the drain-source resistance (rd). + As VGS becomes more negative, the resistance (rd) increases. -ntpsufstudylb.netidoc/1882601 7uni-5 vise 7401129128, 759.AM study viewer Transfer Characteristics * The transfer characteristic of input-to-output is not as straight forward in a JFET as it was ina BJT. * InaBIT, f indicated the relationship between IB (input) and IC (output). + Ina JFET, the relationship of VGS (input) and ID (output) is a little more complicated: Current relation T, = Ines! 1- Comparison between BJT & FET -ntpsufstudylb.netidoc/1882601 7uni-5 vise sao1129128, 759.AM study viewer BJT 1.BJT controls large output(1.) by means of a relatively small base current. It is a current controlled device. FET 1.FET controls drain current by means of small gate voltage. It is a voltage controlled device 2.Has amplification factor B 3.Has high voltage gain 4.Less input impedance 2.Has trans-conductance gm, 3.Does not have as high as BIT 4.Very high input impedance FET Small-Signal Analysis + FET Small-Signal Model * Trans-conductance The relationship of VGS (input) to [D(output)is called trans- conductance. + The trans-conductance is denoted gm. Definition of g,, using transfer characteristics -ntpsufstudylb.netidoc/1882601 7uni-5 vise sia1129128, 759.AM study viewer ‘ Example: Determine the magnitude of g,, for a JFET with Ipss = 8mA and Vp = - 4V at the following de bias points. a, At Vgs=-0.5V b. At Vgs=-1.5V c. At Vgg=-2.5V -ntpsufstudylb.netidoc/1882601 7uni-5 vise r01a01129128, 759.AM study viewer Mathematical Definition of gm FET Impedance * Input Impedance Zi : © ohms * Output Impedance Zo: r= l/yos . _ AVps "aa Wes = comsant ‘Yos-admittance equivalent eireuit parameter listed on FET specification sheets. -ntpsufstudylb.netidoc/1882601 7uni-5 vise ao1129128, 759.AM study viewer Two port model Phase Relationship * The phase relationship between input and output depends on the amplifier configuration circuit. + Common — Source ~ 180 degrees + Common - Gate ~ 0 degrees * Common ~ Drain ~ 0 degrees -ntpsufstudylb.netidoc/1882601 7uni-5 vise sao1129128, 759.AM study viewer JFET Common-Source (CS) Fixed-Bias Configuration * The input is on the gate and the output is on the drain. + Fixed bias configuration includes the coupling capacitors cl and c2 that isolate the de biasing arrangements from the applied signal and load. * They act as short circuit equivalents for the ac analysis. AC Equivalent Circuit Input impedance Zi=R, Output Impedance:Z,=ry Rp -ntpsufstudylb.netidoc/1882601 7uni-5 vise 1301129128, 759.AM study viewer Voltage gain Phase difference Negative sign in the gain expression indicates that the output voltage is 180° phase shifted to that of input. Example For fixed bias circuit, the following bias data are given. Ves=-2V, Ipo=5.625mA and V,=-8V. The input voltage vj. The value of yo.-40pS. 1. Determine Ga, 2. Find rg 3. Determine Z, 4. Calculate Zo, Av with and without effects of rg, -ntpsufstudylb.netidoc/1882601 7uni-5 vise sao1129128, 759.AM study viewer JFET Self bias configuration + Main disadvantage of fixed bias configuration requires two de voltage sources. * Self bias circuit requires only one DC supply to establish the desired operating point. Self bias configuration Yoo IfCs is removed, it affects the gain of the cireuit -ntpsufstudylb.netidoc/1882601 7uni-5 vise 1601129128, 759.AM study viewer AC Equivalent Circuit * The capacitor across the source resistance assumes its short circuit equivalent for de allowing Rs to define the operating point. * Under ac conditions the capacitors assumes short circuit state and short circuits the R,. * IfRsis left un-shorted, then ac gain will be reduced. -ntpsufstudylb.netidoc/1882601 7uni-5 vise 161401129128, 759.AM study viewer Redrawn equivalent circuit: Here R, is bypassed by X., Circuit parameters: * Since the resulting circuit is same as that of fixed bias configuration, all the parameter expression remains same as evaluated for fixed bias configuration. Input impedance Zi=Rg Output Impedance:Zo= ry parallel Ry Z,=Rp 1,210Rp Leaving Rs un-bypassed helps to reduce gain variations from device to device by providing degenerative current feedback. However, this method for minimizing gain variations is only effective when a substantial amount of gain is sacrificed. -ntpsufstudylb.netidoc/1882601 7uni-5 vise aan1129128, 759.AM study viewer > Il —8m (Ta || Rp) =-g SmaRp rg210Rp Self bias configuration with un bypassed R, G D . * + + | + ‘, 3 4 taMer — Vou s Yi RG 7 Ro Rs & = ae + - . Here R, is part of the equivalent circuit . * There is no way to reduce the network with lowest complexity. * Carefully all the parameters have to be calculated by considering all polarities properly Input Impedance * Due to open-circuit condition between gate and output network, the input impedance remains as follows: ZRe Output impedance -ntpsufstudylb.netidoc/1882601 7uni-5 vise 16401129128, 759.AM study viewer * Output impedance is defined by ZO= Vo/lo at vi-0 Setting Vi=0 results in following circuit. Lo=———_,.—- + ts gmRs +202 am Ss n vas rd Zo RD rd >10(RD+Rs) _ qo -—? Rs Id 1+ gmRs re Voltage gain: Aya 12 = gneo_ Vi ve gmrs+D*Rs rd rd 210(RD+ Rs), Ay =~ 27RD 1+ gmRs tpsstudylib neidoc!18826017/unit5—vtuse 191401129128, 759.AM study viewer Example: A self bias circuit has operating point defined by VGSo=-2.6V, IDq=2.6mA with IDSS=8mA and Vp=-6V. Yos=20uS Determine a. Gm b. Rd e. Zi d. Zo with and without rd effect. e. Av with and without rd effect Yoo Idss=10mA 33K VP=-6V G Ro tpsstudylib neidoc!18826017/unit5—vtuse 2oia01129128, 759.AM study viewer JEET voltage divider configuration rp Input Impedance: Z, =R, ||, Output Impedance: Z, =1, Rp =Ro|,oue, -ntpsufstudylb.netidoc/1882601 7uni-5 vise 2401129128, 759.AM study viewer Voltage gain: D @> Emo || Rp) A. =e m°~D |,>10Rp Note + Equations for ZO and Av are same as in fixed bias. * Only Zi is now dependent on parallel combination of RI and R2. JFET source follower Yoo -ntpsufstudylb.netidoc/1882601 7uni-5 vise 221401129128, 759.AM study viewer In a CD amplifier configuration the input is on the gate, but the output is from the source. AC equivalent circuit Yoo Input and output impedance: + Inputimpedance — : Zi-RG * Output impedance setting Vi=0V will result in the gate terminal being connected directly to ground as shown in figure below. -ntpsufstudylb.netidoc/1882601 7uni-5 vise 281401129128, 759.AM study viewer Equivalent circuit + Applying KCL at output node To+ gmVos = Tra + Tas Vo Vo =—+— ra Rs oy. -pll_l result : Io =Vo|—_+—| — gnVes Rs 1 oo. =Vo] —+—]- gnVes [ | Bus 1 oo. =Vo] —+—] - gn[-Vo E 1] sol-Fe] orfbet »| “Lea Rs 8 -ntpsufstudylb.netidoc/1882601 7uni-5 vise 241401129128, 759.AM study viewer Vo Vo 1 _ 1 fit ra Rs ee Z,=Rs|| m Iny2 10Rs rd, Rs and gm are all in parallel. Voltage gain A =Ne= Sala llRe) Vi I+enGullRs) EuRs v 1+gnRs |,,> 10, Since denominator is larger by a factor of one, the gain can never be equal to or greater than one. (as in the case of emitter follower of BIT) -ntpsufstudylb.netidoc/1882601 7uni-5 vise 251401129128, 759.AM study viewer Example: Ade analysis of the source follower has resulted in VGS=-2.86V and lo=4.56mA. Determine a. gm b. Zi cord d. Calculate Zo with and without effect of rd. e. Calculate Av with and without effect of rd. Compare the results. Given IDSS=16mA, Vp=-4V, yos=25pS. The coupling capacitors used are 0.05pF. JFET common gate configuration The input is on source and the output is on the drain. Same as the common base in BJT tpsstudylib neidoc!18826017/unit5—vtuse 261401129128, 759.AM study viewer AC equivalent circuit Impedances: 1, +R, Input Impedance: Z, =R, ||| “2 l+g.ty 1 Rg ||— m 112 10Ry Output Impedance: Z, =Rp | 1, Z, ER, 2 10RD -ntpsufstudylb.netidoc/1882601 7uni-5 vise 21401129128, 759.AM Voltage gain faR study viewer D |ng2t0Rp -ntpsufstudylb.netidoc/1882601 7uni-5 vise 281401129128, 759.AM study viewer Example: For the network shown if VGSo=-2.2V, IDoq=2.03mA, Determine gm,rd, Zi with and without the effect of rd, Av with and without the effect of rd. Also find Vo with and without rd. compare the results. Cl and c2 are given by 10uf. +12v -ntpsufstudylb.netidoc/1882601 7uni-5 vise 291401129128, 759.AM MOSFETs: MOSFETs ate of two types: * Depletion type * Enhancement type 1. Depletion type MOSFETs s study viewer channel doped with donors to give negative threshold voltage, i.e., depletion fets are always on. * Shockley’s equation is also applicable to depletion type MOSFETs. * This results in same equation for gm. -ntpsufstudylb.netidoc/1882601 7uni-5 vise The ac equivalent model for this MOS device is same as JFET. Only difference is VGSo is positive for n-channel device and negative for p-channel device. As a result of this, gm can be greater than gmo. soia01129128, 759.AM study viewer + Range of rd is very similar to that of JFETs. D-MOSFET ac equivalent model cif = Ya $Me 2% Example:A network shown below has the de analysis results as IDSS=6mA, VP=3V.VGSo=1.5V and IDQ=7.6mA.yos=10uS a.Determine gm and compare with gmo b.Find rd c.Sketch ac equivalent circuit d.Find Zi.Zo and Av. -ntpsufstudylb.netidoc/1882601 7uni-5 vise sao1129128, 759.AM study viewer 18V 110M $ 1.8K cc it ed 10M 150 Solution: gmo=4m$ gm=6mS gm is 50% more than gmo rd= 100K Q Zi=10M Q parallel with 110M Q=9.17MQ Zo=100K Q parallel with 1.8K Q=1.8KQ Av=-gmrd= 10.8 Ac equivalent circuits -ntpsufstudylb.netidoc/1882601 7uni-5 vise sao1129128, 759.AM study viewer Enhancement type MOSFET + There are two types of E-MOSFETs: nMOS or n-channel MOSFETs pMOS or p-channel MOSFETs E-MOSFET ac small signal model G D o—o + SaVes ‘4 vot Ss 1 aussi acm You! -ntpsufstudylb.netidoc/1882601 7uni-5 vise sso1129128, 759.AM study viewer + ID=k(VGS-VGS(Th))2 + gmis defined by + Taking the derivative and solving for gm, gm=2k(VGS-VGS(th)) EMOSFET drain feedback configuration Yop | tpsstudylib neidoc!18826017/unit5—vtuse s4ia01129128, 759.AM Ac equivalent model Yoo -ntpsufstudylb.netidoc/1882601 7uni-5 vise study viewer sao1129128, 759.AM study viewer Input and output impedances Input Impedance: Z,=—RetllR Teale) 7 2 Re 1+ aRo Ip oonity, n2 108 Output Impedance: Z,=R, |r |Rp Z,=Rp lagoon Rp, y210Rp Voltage gain a(R Il ta li Rp) Av = —8mRoless gino. ue 10s -ntpsufstudylb.netidoc/1882601 7uni-5 vise 61401129128, 759.AM study viewer Numerical For the above said configuration, the following results were got. K=0.24X10° A/V", Vgs9=6.4V, Ipg=2.75mA. Determine gm, rd, Z; with and without the effect of rd, Z, with and without the effect of rd. Av with and without effect of rd. And compare the results. Id(sat}/=6mA, VGS(th)=3V, VGS(on)=6V.yos=20uS. Yop + Rp=2K ohms + Ry=10M ohms + Cl,c2=1uF Solution. + gm=2k(Ves-Vesam) =1.63mS. + rd=1/yos=50KQ * Ziwith rd: +(rai/ Ro) “Avail Ra) -ntpsufstudylb.netidoc/1882601 7uni-5 vise srao1129128, 759.AM study viewer =2.42MQ * Ziwithout effect ofrd: 7k “14 geRo =2.53MQ2 Zo with rd: (Ry parallel rq parallel Rp) =1.92KQ2 Zo without rd: Zo=RD = 2KQ. Gain Ay with ry: =-24 (Rell I|Rp) -ntpsufstudylb.netidoc/1882601 7uni-5 vise seia01129128, 759.AM study viewer E MOSFET voltage divider configuration *Voo Important Parameters Input Impedance: Z,=R,||R, Output Impedance: Z_) =r, ||R, =Rp T4210Rp Ay =—8m(u || Rp) AL =—g; v SaRp |asvax, -ntpsufstudylb.netidoc/1882601 7uni-5 vise sao1129128, 759.AM study viewer Ac equivalent circuit -ntpsufstudylb.netidoc/1882601 7uni-5 vise 40140