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SPI Description

The SPI slave module receives 16-bit data serially each round and displays it in parallel on a 64-bit output after each round. It takes 4 rounds, or 1 full cycle, to fill the 64-bit output as the module is divided into 4 drivers responsible for 16 bits each. The module demonstrates receiving data serially over 2 rounds, storing it, and displaying the combined 48-bit value on the output after the second round.

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PedroSartori
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23 views3 pages

SPI Description

The SPI slave module receives 16-bit data serially each round and displays it in parallel on a 64-bit output after each round. It takes 4 rounds, or 1 full cycle, to fill the 64-bit output as the module is divided into 4 drivers responsible for 16 bits each. The module demonstrates receiving data serially over 2 rounds, storing it, and displaying the combined 48-bit value on the output after the second round.

Uploaded by

PedroSartori
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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SPI module summary

Concept
The Serial Peripheral Interface (SPI) slave module is designed to serially receive information,
bit by bit, displaying it later in parallel. It works by transmitting information in 16-bit rounds, and
then displaying the received data in a 64-bit parallel output after each round, comprising four
rounds i.e., one full cycle. The concept behind using SPI with these specifications is that each of
the four drivers are assigned to one of the 16-bits set of the output, which will be responsible for
its control, i.e., bits 0 to 15 control driver 1, bits 16 to 31 driver 2, bits 32 to 47 driver 3, and bits
48 to 63 driver 4. To facilitate the understanding of how the SPI module works and its usefulness
in the project, a conceptual diagram is shown below.

As it can be seen from the schematic above, the device has four inputs and two outputs and
their functions are described below:
• Chip select (CS): Input responsible for selecting and enabling the SPI operation.
0 = Chip selected | 1 = Chip not selected

• Reset (RST): Input pulse that resets the circuit, i.e., returns the circuit to its initial condition.
The module was designed to work for 3 full cycles (12 rounds/3 rounds for each driver),
so it must be reset after the end of the third one.
0 = Reset | 1 = Information can be transmitted
• Clock (CLK): Oscillating input that tells the SPI exactly when to sample the bits on the
data line;
Clock off = Information is not transmitted | Clock on = 1 bit transmitted per clock pulse

• Information transmitted (MOSI): Input where received data comes in;


16 bit serial data

• Write flag (WR): Output flag that indicates the module is receiving data;
0=No data | 1=SPI is receiving data

• Data output (DAT_O): Data displayed on a 64-bit parallel output.


Operational example
To elucidate the functioning of the module, a practical example is presented below,
demonstrating the utilization of all signals. It consists of two rounds of operation.

In the first round of the first cycle the numerical value 1280 (0000010100000000 in binary) is
being received serially through the MOSI input, stored, and then exhibited in the output at the end
of the next round, occupying its first 16-bits position. In the following 16-bit round, new data
(0000000000000011 in binary) are received and sent to the second position of the SPIs 64-bits
output. By combining with the information from the previous round, the number displayed in the
output after the end of the second round is 197888 (0000000000000011 0000010100000000 in
binary). It is worth noting that this whole process does not stop after one cycle, which is possible
because the prior data stored are overwritten when all bits are filled in the next cycle. For example,
after 1 full cycle all 64 bits of the output will be filled with information, which means that in the
fifth round (beginning of the second full cycle) the data contained in the first position (bits 0 to 15)
will be overwritten.
It is also worth noting that the output has a 1-round delay. This is because the information must
be stored first in a 16-bit register and then shifted to the 64-bit one.

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