Instruction Types

Most computer instructions can be classified into three categories:

1. Data transfer instructions
2. Data manipulation instructions
3. Program control instructions
Data transfer instructions cause transfer of data from one location to another without changing
the binary information content. Data manipulation instructions are those that perform arithmetic,
logic, and shift operations. Program control instructions provide decision-making capabilities and
change the path taken by the program when executed in the computer.

Data transfer instructions

Data transfer instructions move data from one place in the computer to another without changing
the data content. The most common transfers are between memory and processor registers,
between processor registers and input or output, and between the processor registers
themselves.
Table gives a list of eight data transfer instructions used in many computers with mnemonics.
Typical Data Transfer Instructions

Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

Data Manipulation Instructions

Data manipulation instructions perform operations on data and provide the computational
capabilities for the computer. The data manipulation instructions in a typical computer are usually
divided into three basic types:
1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions
Arithmetic Instructions
The four basic arithmetic operations are addition, subtraction, multiplication, and division. Most
computers provide instructions for all four operations.
The four basic arithmetic operations are sufficient for formulating solutions to scientific problems
when expressed in terms of numerical analysis methods.
A list of typical arithmetic instructions is given in Table.
Typical Arithmetic Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with carry ADDC
Subtract with borrow SUBB

Logical and Bit Manipulation Instructions

Logical instructions perform binary operations on strings of bits stored in registers.
They are useful for manipulating individual bits or a group of bits that
represent binary-coded information. The logical instructions consider each bit of the operand
separately and treat it as a Boolean variable, By proper application of the logical instructions it is
possible to change bit value, to clear a group of bits, or to insert new bit values into operands
stored in registers or memory words.
Some typical logical and bit manipulation instructions are listed in Table
Typical Logical and Bit Manipulation Instructions
Name Mnemonic
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-OR XOR
Clear carry CLRC
Set carry SETC
Complement carry COMC
Enable interrupt EI
Disable interrupt DI
Shift Instructions
Instructions to shift the content of an operand are quite useful and are often
provided in several variations.
Shifts are operations in which the bits of a word are moved to the left or right. The bit shifted in at
the end of the word determines the type of shift used.
Shift instructions may specify either logical shifts, arithmetic shifts, or rotate-type operations. In
either case the shift may be to the right or to the left.
Table lists four types of shift instructions.

Typical Shift Instructions

Name Mnemonic
Logical shift right SHR
Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right through carry RORC
Rotate left through carry ROLC

The logical shift inserts 0 to the end bit position. The end position is the leftmost bit for shift right
and the rightmost bit position for the shift left.
The arithmetic shift-right instruction must preserve the sign bit in the leftmost position. The sign
bit is shifted to the right together with the rest of the number, but the sign bit itself remains
unchanged. This is a shift-right operation with the end bit remaining the same.
The arithmetic shift-left instruction inserts 0 to the end position and is identical to the logical shift-
left instruction.
The rotate instructions produce a circular shift. Bits shifted out at one end of the word are not lost
as in a logical shift but are circulated back into the other end.
The rotate through carry instruction treats a carry bit as an extension of the register whose word
is being rotated. Thus a rotate-left through carry instruction transfers the carry bit into the rightmost
bit position of the register, transfers the leftmost bit position into the carry, and at the same time,
shifts the entire register to the left.
The arithmetic shift-left inserts a 0 into R0, and shifts all other bits to the left. The initial bit of Rn-1
is lost and replaced by the bit from Rn-2. A sign reversal occurs if the bit in Rn-1 changes in value
after the shift. This happens if the multiplication by 2 causes an overflow. An overflow occurs after
an arithmetic shift left if initially, before the shift, Rn-1 is not equal to Rn-2. An overflow flip-flop V,
can be used to detect an arithmetic shift-left overflow.
If Vs = 0, there is no overflow, but if Vs = 1, there is an overflow and a sign reversal after the shift.
Vs must be transferred into the overflow flip-flop with the same clock pulse that shifts the register.

Example
An 8-bit register contains the binary value 10011100. What is the register value after an arithmetic
shift right? Starting from the initial number 10011100, determine the register value after an
arithmetic shift left, and state whether there is an overflow ?

Program Control instructions

Instructions are always stored in successive memory locations. When processed in the CPU, the
instructions are fetched from consecutive memory
locations and executed. Each time an instruction is fetched from memory, the program counter is
incremented so that it contains the address of the next instruction in sequence. After the execution
of a data transfer or data manipulation instruction, control returns to the fetch cycle with the
program
counter containing the address of the instruction next in sequence. On the other hand, a program
control type of instruction, when executed, may change the address value in the program counter
and cause the flow of control to be altered.

Typical Program Control Instructions

Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (by subtraction) CMP
Test (by ANDing) TST
Status Bit Conditions
It is sometimes convenient to supplement the ALU circuit in the CPU with a status register where
status bit conditions can be stored for further analysis.
Status bits are also called condition-code bits or flag bits. Figure shows the block diagram of an
8-bit ALU with a 4-bit status register. The four status bits are symbolized by C, S, Z, and V . The
bits are set or cleared as a result of an operation performed in the ALU.

1. Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.

2. Bit S (sign) is set to 1 if the highest-order bit F7 is 1. It is set to 0 if the bit is 0.
3. Bit Z (zero) is set to 1 if the output of the ALU contains all 0’s. It is cleared to 0 otherwise.
In other words, Z = 1 if the output is zero and Z = 0 if the output is not zero.
4. Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries is equal to 1, and
cleared to 0 otherwise. This is the condition for an overflow when negative numbers are in
2’s complement. For the 8-bit ALU, V = 1 if the output is greater than +127 or less
than -128.
The status bits can be checked after an ALU operation to determine certain relationships
that exist between the values of A and B. If bit V is set after the addition of two signed
numbers, it indicates an overflow condition.
Instruction Formats
A computer will usually have a variety of instruction code formats. It is the function of the control
unit within the CPU to interpret each instruction code and provide the necessary control functions
needed to process the instruction.
The format of an instruction is usually depicted in a rectangular box symbolizing the bits of the
instruction as they appear in memory words or in a control register.
The bits of the instruction are divided into groups called fields. The most common fields found in
instruction formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor register.
3. A mode field that specifies the way the operand or the effective address is determined.
Other special fields are sometimes employed under certain circumstances, as for example
a field that gives the number of shifts in a shift-type instruction.
✓ Operations specified by computer instructions are executed on some data stored in memory or
processor registers.
✓ Operands residing in memory are specified by their memory address.
✓ Operands residing in processor registers are specified with a register address.
✓ A register address is a binary number of k bits that defines one of 2k registers in the CPU.
✓ Thus a CPU with 16 processor registers R0 through R15 will have a register address field of four
bits.
✓ The binary number 0101, for example, will designate register R5.
✓ Computers may have instructions of several different lengths containing varying number of
addresses.
✓ The number of address fields in the instruction format of a computer depends on the internal
organization of its registers.
✓ Most computers fall into one of three types of CPU organizations:

1. Single accumulator organization.

2. General register organization.
3. Stack organization.

Single Accumulator organization

✓ All operations are performed with an implied accumulator register.
✓ The instruction format in this type of computer uses one address field. For example, the
instruction that specifies an arithmetic addition is defined by an assembly language
instruction as
ADD X
✓ where X is the address of the operand.
✓ The ADD instruction in this case results in the operation
AC ← AC + M[X]
AC is the accumulator register and M[X] symbolizes the memory word located at address X.
General Register organization
✓ The instruction format in this type of computer needs three register address fields.
✓ Thus the instruction for an arithmetic addition may be written in an assembly language as
ADD R1, R2, R3
to denote the operation R1 ← R2 + R3
✓ The number of address fields in the instruction can be reduced from three to two if the
destination register is the same as one of the source registers. Thus the instruction
ADD R1, R2
✓ would denote the operation R1 ← R1 + R2
✓ Only register addresses for R1 and R2 need be specified in this instruction.
✓ Computers with multiple processor registers use the move instruction with a mnemonic
MOV to symbolize a transfer instruction. Thus the instruction
MOV R1, R2
denotes the transfer R1 ← R2 (or R2 ← R1, depending on the particular computer).
✓ Thus transfer-type instructions need two address fields to specify the source and the
destination.
✓ General register-type computers employ two or three address fields in their instruction
format.
✓ Each address field may specify a processor register or a memory word. An instruction
symbolized by
ADD R1, X
would specify the operation R1 ← R1 + M[X]
It has two address fields, one for register R1 and the other for the memory address X.

Stack organization
✓ Computers with stack organization would have PUSH and POP instructions which require an
address field. Thus the instruction

PUSH X
will push the word at address X to the top of the stack.
✓ The stack pointer is updated automatically.
✓ Operation-type instructions do not need an address field in stack-organized computers.
✓ This is because the operation is performed on the two items that are on top of the stack. The
instruction

ADD
in a stack computer consists of an operation code only with no address field.
✓ This operation has the effect of popping the two top numbers from the stack, adding the
numbers, and pushing the sum into the stack.
✓ There is no need to specify operands with an address field since all operands are implied
to be in the stack.
 Example
To illustrate the influence of the number of addresses on computer programs, we will
evaluate the arithmetic statement
X = (A + B) * (C + D)
using zero, one, two, or three address instructions.
We will use the symbols ADD, SUB, MUL, and DIV for the four arithmetic operations;
MOV for the transfer-type operation; and LOAD and STORE for transfers to and from
memory and AC register.
We will assume that the operands are in memory addresses A, B, C, and D, and the
result must be stored in memory at address X.

Three-Address Instructions
Computers with three-address instruction formats can use each address
field to specify either a processor register or a memory operand.
The program in assembly language that evaluates X = (A + B) * (C + D) is shown below, together
with comments that explain the register transfer operation of each instruction.
ADD R1, A, B R1 ← M[A]+M[B]
ADD R2, C, D R2 ← M[C]+M[D]
MUL X, R1, R2 M[X] ← R1* R2
It is assumed that the computer has two processor registers, R1 and R2. The symbol M[A]
denotes the operand at memory address symbolized by A.
The advantage of the three-address format is that it results in short programs when evaluating
arithmetic expressions.
The disadvantage is that the binary-coded instructions require too many bits to specify three
addresses.

Two-Address Instructions
Two-address instructions are the most common in commercial computers. Here again each
address field can specify either a processor register or a memory word.
The program to evaluate X = (A + B) * (C + D) is as follows:
MOV R1, A R1 ← M[A]
ADD R1, B R1 ← R1 + M[B]
MOV R2, C R2 ← M[C]
ADD R2, D R2 ← R2 + M[D]
MUL R1, R2 R1 ← R1*R2
MOV X, R1 M[X] ← R1
The MOV instruction moves or transfers the operands to and from memory and processor
registers. The first symbol listed in an instruction is assumed to be both a source and the
destination where the result of the operation is transferred.
One-Address Instructions
One-address instructions use an implied accumulator(AC) register for all data manipulation.
For multiplication and division there is a need for a second register.
However, here we will neglect the second register and assume
that the AC contains the result of all operations.
The program to evaluate X = (A + B) * (C + D) is as follows
LOAD A AC ← M[A]
ADD B AC ← AC + M[B]
STORE T M[T] ← ΑC
LOAD C AC ← M[C]
ADD D AC ← AC + M[D]
MUL T AC ← AC * M[T]
STORE X M[X] ← AC
All operations are done between the AC register and a memory operand.
T is the address of a temporary memory location required for storing the intermediate result.

Zero-Address Instructions
A stack-organized computer does not use an address field for the instructions ADD and MUL.
The PUSH and POP instructions, however, need an address field to specify the operand that
communicates with the stack.
The program to evaluate X = (A + B) * (C + D) for a stack organized computer. (TOS stands
for top of stack).
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B)
PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C + D)
MUL TOS ← (C + D)*(A + B)
POP X M[X] ← TOS

To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression

into Reverse Polish Notation.
The name “zero-address” is given to this type of computer because of the absence of an address
field in the computational instructions.
RISC Instructions
The instruction set of a typical RISC processor is restricted to the use of LOAD and STORE
instructions when communicating between memory and CPU.
All other instructions are executed within the registers of the CPU without referring to memory.
A program for a RISC-type CPU consists of LOAD and STORE instructions that have one memory
and one register address, and computational-type instructions that have three addresses with all
three specifying processor registers.
The program to evaluate X = (A + B) * (C + D) is given below
LOAD R1, A R1 ← M[A]
LOAD R2, B R2 ← M[B]
LOAD R3, C R3 ← M[C]
LOAD R4, D R4 ← M[D]
ADD R1, R1, R2 R1 ← R1 + R2
ADD R3, R3, R4 R3 ← R3 + R4
MUL R1, R1, R3 R1 ← R1 * R3
STORE X, R1 M[X] ← R1
Reduced Instruction Set Computer (RISC)
An important aspect of computer architecture is the design of the instruction set for the processor.
The instruction set chosen for a particular computer determines the way that machine language
programs are constructed.
Early computers had small and simple instruction sets, forced mainly by the need to minimize the
hardware used to implement them.
As digital hardware became cheaper with the advent of integrated circuits, computer instructions
tended to increase both in number and complexity.
Many computers have instruction sets that include more than 100 and sometimes even more than
200 instructions. These computers also employ a variety of data types and a large number of
addressing modes.
The trend into computer hardware complexity was influenced by various factors, such as
upgrading existing models to provide more customer applications, adding instructions that
facilitate the translation from high-level language into machine language programs.
A computer with a large number of instructions is classified as a Complex Instruction Set
Computer, abbreviated CISC.
In the early 1980s, a number of computer designers recommended that
computers use fewer instructions with simple constructs so they can be executed much faster
within the CPU without having to use memory as often.
This type of computer is classified as a
Reduced Instruction Set Computer or RISC.

CISC Characteristics
The design of an instruction set for a computer must take into consideration not only machine
language constructs, but also the requirements imposed on the use of high-level programming
languages. The translation from high-level to machine language programs is done by means of a
compiler program.
One reason for the trend to provide a complex instruction set is the desire to simplify the
compilation and improve the overall computer performance.
The task of a compiler is to generate a sequence of machine instructions for each high-level
language statement. The task is simplified if there are machine instructions that implement the
statements directly.
The essential goal of a CISC architecture is to attempt to provide a single machine instruction for
each statement that is written in a high-level language. Examples of CISC architectures are the
Digital Equipment Corporation VAX computer and the IBM 370 computer.

Another characteristic of CISC architecture is the incorporation of variable length instruction

formats.
Instructions that require register operands may be only two bytes in length, but instructions that
need two memory addresses may need five bytes to include the entire instruction code.
If the computer has 32-bit words (four bytes), the first instruction occupies half a word, while the
second instruction needs one word in addition to one byte in the next word.
The instructions in a typical CISC processor provide direct manipulation of operands residing in
memory. For example, an ADD instruction may specify one operand in memory through index
addressing and a second
operand in memory through a direct addressing. Another memory location may be included in the
instruction to store the sum. This requires three memory references during execution of the
instruction.
However, as more instructions and addressing modes are incorporated into a computer, the more
hardware logic is needed to implement and support them, and this may cause the computations
to slow down.
In summary, the major characteristics of CISC architecture are:
1. A large number of instructions—typically from 100 to 250 instructions
2. Some instructions that perform specialized tasks and are used infrequently
3. A large variety of addressing modes—typically from 5 to 20 different modes
4. Variable-length instruction formats
5. Instructions that manipulate operands in memory

Difference between RISC and CISC Processor

Instruction Cycle
A program residing in the memory unit of a computer consists of a sequence of instructions.
These instructions are executed by the processor by going through a cycle for each instruction.
Instruction Cycle is subdivided into following Phases
Fetch an instruction from memory
Decode the instruction
Read the effective address from memory.
Execute the instruction

Instruction Cycle State Diagram

Instruction Sub Cycle
The operation of a computer, in executing a program, consists of a sequence of instruction cycles,
with one machine instruction per cycle.
Each instruction cycle in turn is sub divided into a sequence of Sub cycles or phases. One such
subdivision is fetch, indirect, execute, and interrupt, with only fetch and execute always
occurring.

Fetch Cycle
During the fetch cycle, an instruction is read from memory
1. The PC contains the address of the next instruction to be fetched.
2. This address is moved to the MAR and placed on the address bus.
3. The control unit requests a memory read, and the result is placed on the data
bus
4. and copied into the MBR and then moved to the IR.
Meanwhile, the PC is incremented by 1, preparatory for the next fetch.
Once the fetch cycle is over, the control unit examines the contents of the IR to determine if it
contains an operand specifier using indirect addressing. If so, an indirect cycle is performed
Indirect Cycle
Once the fetch cycle is over, the control unit examines the contents of the IR to determine if it
contains an operand specifier using indirect addressing. If so, an indirect cycle is performed. The
rightmost N bits of the MBR, which contain the address reference, are transferred to the MAR.
Then the control unit requests a memory read, to get the desired address of the operand into the
MBR.

Execute Cycle
The execute cycle takes many forms; the form depends on which of the various machine
instruction is in the IR. This cycle may involve transferring data among registers. read or write
from memory or I/O, and/or the invocation of the ALU.

Interrupt Cycle
The current contents of the PC must be saved so that the processor can resume normal activity
after the interrupt. Thus, the contents of the PC are transferred to the MBR to be written into
memory. The special memory location reserved for this purpose is loaded into the MAR from the
control unit. It might, for example be a stack pointer. The PC is loaded with the address of the
interrupt routine. As a result, the next instruction cycle will begin by fetching the appropriate
instruction.
Processing an Instruction
To execute a program, the processor fetches one instruction at a time and performs the operations
specified. Instructions are fetched from successive memory locations until a branch or a jump
instruction is encountered. The processor keeps track of the address of the memory location
containing the next instruction to be fetched using the program counter, PC. After fetching an
instruction, the contents of the PC are updated to point to the next instruction in the sequence. A
branch instruction may load a different value into the PC. Another key register in the processor is
the instruction register, IR. Suppose that each instruction comprises 4 bytes, and that it is stored
in one memory word.
To execute an instruction, the processor has to perform the following three steps:
➢ Fetch the contents of the memory location pointed to by the PC. The contents of this
location are loaded into the IR (fetch phase).
IR ← [[PC]]
➢ Assuming that the memory is byte addressable, increment the contents of the PC by 4
(fetch phase).
PC ← [PC] + 4
➢ Carry out the actions specified by the instruction in the IR (execution phase).
With few exceptions, an instruction can be executed by performing one or more of the
following operations in some specified sequence:
➢ Transfer a word of data from one processor register to another or to the ALU
➢ Perform an arithmetic or a logic operation and store the result in a processor
register
➢ Fetch the contents of a given memory location and load them into a processor
register
➢ Store a word of data from a processor register into a given memory location
Single Bus Organization

Single-bus organization of the datapath inside a processor

Input and Output Gating for a Register

Input and Output Gating for one Register bit

Performing an Arithmetic or Logic Operation

The sequence of operations to add the contents of register R1 to those of R2 and store the result
in R3
R3  R1 + R2

Fetching a Word from Memory

Connection and Control Signals for Register MDR

An example of a read operation, consider the instruction
Move (R1),R2
The actions needed to execute this instruction are

MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]
MFC → Memory Function Completed

An example of a read operation, consider the instruction

Move (R1),R2
The memory read operation requires three steps, which can be described by the signals being
activated as follows
R1out, MARin, Read
MDRinE, WMFC
MDRout, R2in
WMFC → Wait for Memory Function Completed

Storing a Word in Memory

Writing a word into a memory location follows a similar procedure. The desired address is loaded
into MAR. Then, the data to be written are loaded into MDR, and a write command is issued.
Hence, executing the instruction
Move R2,(R1)
requires the following sequence:

R1out, MARin
R2out, MDRin, Write
MDRoutE, WMFC
WMFC → Wait for Memory Function Completed
Execution of a Complete Instruction
Consider the instruction
Add (R3), R1
which adds the contents of a memory location pointed to by R3 to register R1.
Executing this instruction requires the following actions:
➢ Fetch the instruction
➢ Fetch the first operand (the contents of memory location pointed to by R3)
➢ Perform the addition
➢ Load the result into R1

Instruction execution proceeds as follows.

In step 1, the instruction fetch operation is initiated by loading the contents of the PC into the MAR
and sending a Read request to the memory. The Select signal is set to Select4, which causes the
multiplexer MUX to select the constant 4. This value is added to the operand at input B, which is
the contents of the PC, and the result is stored in register Z. The updated value is moved from
register Z back into the PC during step 2,while waiting for the memory to respond. In step 3, the
word fetched from the memory is loaded into the IR. Steps 1 through 3 constitute the instruction
fetch phase, which is the same for all instructions. The instruction decoding circuit interprets the
contents of the IR at the beginning of step 4. This enables the control circuitry to activate the
control signals for steps 4 through 7, which constitute the execution phase. The contents of
register R3 are transferred to the MAR in step 4, and a memory read operation is initiated.
Then, the contents of R1 are transferred to register Y in step 5, to prepare for the addition
operation. When the Read operation is completed, the memory operand is available in register
MDR, and the addition operation is performed in step 6. The contents of MDR are gated to the
bus, and thus also to the B input of the ALU, and register Y is selected as the second input to the
ALU by choosing Select Y. The sum is stored in register Z, then transferred to R1 in step 7. The
End signal causes a new instruction fetch cycle to begin by returning to step 1.

Execution of Branch Instructions

A branch instruction replaces the contents of the PC with the branch target address. This address
is usually obtained by adding an offset X, which is given in the branch instruction, to the updated
value of the PC. Example mentioned here gives a control sequence that implements an
unconditional branch instruction. Processing starts, as usual, with the fetch phase. This phase
ends when the instruction is loaded into the IR in step 3. The offset value is extracted from the IR
by the instruction decoding circuit, which will also perform sign extension if required. Since the
value of the updated PC is already available in register Y, the offset X is gated onto the bus in
step 4, and an addition operation is performed. The result, which is the branch target address, is
loaded into the PC in step 5. The offset X used in a branch instruction is usually the difference
between the branch target address and the address immediately following the branch instruction.
Pipelining
Pipelining is a technique of decomposing a sequential process into suboperations, with each
subprocess being executed in a special dedicated segment that operates concurrently with all
other segments.
A pipeline can be visualized as a collection of processing segments through which binary
information flows.
Each segment performs partial processing dictated by the way the task is partitioned.
The result obtained from the computation in each segment is transferred to the next segment in
the pipeline. The final result is obtained after the data have passed through all segments. The
name “pipeline” implies a flow of information analogous to an industrial assembly line.
It is characteristic of pipelines that several computations can be in progress in distinct segments
at the same time. The overlapping of computation is made possible by associating a register with
each segment in the pipeline. The registers provide isolation between each segment so that each
can operate on distinct data simultaneously.
The pipeline organization will be demonstrated by means of a simple example. Suppose that we
want to perform the combined multiply and add operations with a stream of numbers.

Each suboperation is to be implemented in a segment within a pipeline. Each segment has one
or two registers and a combinational circuit as shown in Fig. R1 through R5 are registers that
receive new data with every clock pulse. The multiplier and adder are combinational circuits. The
suboperations performed in each segment of the pipeline are as follows:
The five registers are loaded with new data every clock pulse. The effect of each clock is shown
in Table . The first clock pulse transfers A1 and B1 into

The first clock pulse transfers A1 and B1 into R1 and R2. The second clock pulse transfers the
product of R1 and R2 into R3 and C1 into R4. The same clock pulse transfers A2 and B2 into R1
and R2. The third clock pulse operates on all three segments simultaneously. It places A3 and B3
into R1 and R2, transfers the product of R1 and R2 into R3, transfers C2 into R4, and places the
sum of R3 and R4 into R5. It takes three clock pulses to fill up the pipe and retrieve the first output
from R5. From there on, each clock produces a new output and moves the data one step down
the pipeline. This happens as long as new input data flow into the system. When no more input
data are available, the clock must continue until the last output emerges out of the pipeline.
Hardwired and Micro-programmed Control Unit
In a computer system, most of the tasks are controlled with the help of a processor or CPU, which
is the main component of a computer. The CPU usually has two main segments: control unit (CU)
and arithmetic and logic unit (ALU). The control unit (CU) is used to synchronize the tasks with
the help of sending timings and control signals. On the other hand, mathematical and logical
operations can be handled with the help of ALU. Micro programmed control units and hardwired
control units can be called two types of control units. We can execute an instruction with the help
of these two control units.
In the hardwired control unit, the execution of operations is much faster, but the implementation,
modification, and decoding are difficult. In contrast, implementing, modifying, decoding micro-
programmed control units is very easy. The micro-programmed control unit is also able to handle
complex instructions. With the help of control signals generated by micro-programmed and
hardwired control units, we are able to fetch and execute the instructions.

Hardwired Control Unit

With the help of generating control signals, the hardwired control unit is able to execute the
instructions at a correct time and proper sequence. As compared to the micro-programmed, the
hardwired CU is generally faster. In this CU, the control signals are generated with the help of
PLA circuit and state counter. Here the Central processing unit requires all these control signals.
With the help of hardware, the hardwired control signals are generated, and it basically uses the
circuitry approach. So, on the basis of the input obtained by the conditional signals, step counter,
external inputs, and instruction register, the control signals will be generated with the help of
Control signal Generator.
Micro-programmed Control Unit
A micro-programmed control unit can be described as a simple logic circuit. We can use it in two
ways, i.e., it is able to execute each instruction with the help of generating control signals, and it
is also able to do sequencing through microinstructions. It will generate the control signals with
the help of programs.
The program which is used to create the control signals is known as the "Micro-program". The
micro-program is placed on the processor chip, which is a type of fast memory. This memory is
also known as the control store or control memory.
A micro-program is used to contain a set of microinstructions. Each microinstruction or control
word contains different bit patterns. The n bit words are contained by each microinstruction. On
the basis of the bit pattern of a control word, every control signals differ from each other.
the instruction execution in a micro-programmed control unit is also performed in steps. So for
each step, the micro-program contains a control word/ microinstruction. If we want to execute a
particular instruction, we need a sequence of microinstructions. This process is known as the
micro-routine.

So in the micro-programmed control unit, the micro-programs are stored with the help of
Control memory or Control store. The implementation of this CU is very easy and flexible,
but it is slower as compared to the Hardwired control unit.
Hardwired vs Micro-programmed Control Unit

Hardwired Control Unit Microprogrammed Control Unit

The hardwired control unit generates the The microprogrammed control unit
processor's necessary control signals. generates the control signals using
microinstructions.
In comparison to microprogrammed Due to the use of microinstructions
control units, hardwired control units for signal generation, this is slower
operate more quickly since the necessary than the other.
control signals are produced by
hardware.
It is difficult to change. It is simple to change.
More expensive since logic gates must be Comparatively less expensive than
used to implement everything. hardwired control since control
signals are solely produced using
microinstructions.
Due to the complexity of the circuit It can manage complex
design, it cannot handle complicated instructions.
commands.