Digital Design - Computer Architecture

디지털 설계 - 컴퓨터구조
Sequential Circuits and Registers
Lecture 3

Brian J. d’Auriol
2023

Lecture Notes developed by Brian J. d’Auriol, permission to use material granted for non-profit, academic use, provided credit is explicitly given; all other use must request prior permission from the author.
Acknowledgements
• Lecture Notes developed by Brian J. d’Auriol, permission to use
material granted for non-profit, academic use, provided credit is
explicitly given; all other use must request prior permission from the
author.

• Presentation contains additional copyrighted images used herein for

purposes of academic teaching; all such copyrighted material retains
the original copyright terms, in some cases, a particular figure is
subject to a particular license as noted locally.

Slide 2
 Intro. Clock Signals (1)
• Clock signals oscillate between 0 and 1 in a controlled way with a well defined clock
period. Clock signals are used to synchronize sequential (state) digital devices.
• It is useful to define a clock model which abstracts a real clock: here an ideal (square)
clock model and a more realistic clock model are explained (there are a number of
realistic clock models in the literature).
Ideal (square) 1
clock model
Positive Negative
Level Level
0
Clock Period (high) (low)
Rising Falling
(positive) (negative)
edge edge
1

Rise Fall Half-way (50%)

A more between 0 and 1.
realistic
0
clock model • Clock period is reciprocal of clock frequency:
Frequency (f) = 1 / T
Edge-triggering: circuit Level Sensitive: circuit • Example
operates on a rising or operates during positive (+) • Freq = 1GHz, what is the clock period?
falling edge. level or during negative level. • 1x109s = 1 / 1x10-9s = 1ns

Slide 3
 Intro. Clock Signals (2)
Duty cycle:
ratio of high clock signal to clock period:

1
Square (perfect)
clock signal,
duty cycle 25% 0
3ns 1ns
Example:
Clock Period 1 ns / 4 ns = 0.25 (25%)

Ideal clock edge

Period Jitter: tj
change in clock 1
transition
(edge) timing 0
mimimum
Idea Clock
Period
maximum Slide 4
 Intro. Clock Signals (3)
1
A
0
Clock
Skew
1

B
0
+
tskew Positive skew if B edge is after A edge

-
tskew Negative skew if B edge is before A edge
tskew Absolute value of the difference

Clock skew: the propagation of a clock signal throughout multiple circuits depends on the
wire-path length and gate delay. Problem, clocking becomes difficult to globally synchronize
due to different path lengths from clock to devices. Need aggressive clock distribution
designs (limit clock skew 3-4% of clock period [see ITRS 2007 reports], e.g. for a 2Ghz clock,
0.015ns - 0.02ns)
Slide 5
Processor Clock Speeds
Figure obtained from: http://www.orangecone.com/archives/2010/07/
peak_mhz.html under Creative Commons License (http://creativecommons.
org/licenses/by-nc-sa/3.0/), accessed on 2015.01.04, figure attributed to
Mike Kuniavsky, July 4, 2010. This figure has been modified as follows:
image scaled up with a sharpen filter. Under the ‘ShareAlike’ license
requirement, this figure is licensed under the same license as the original.

Increasing clock frequency thus decreasing clock period Clock frequency, energy
efficiency, size , cost,
parallel, multicore factors

Slide 6
Logic Gate Delays
• Terms time
• tplh: Time for propagation low to high
transition
• tphl: Time for propagation high to low tplh
transition V 50%

• Timing depends upon loads the gate

is driving, and other environment
factors.

V
50%
tphl

time Slide 7
Logic Gate Delays: Data Sheets

tp = min (27,19)
min
= 19ns 1995
spec
tp = (27+19)/2 sheet
avg
= 23ns
tp = max (27,19)
max
= 27ns

Slide 8
Source: National Semiconductor 1995, [online] http://cache.national.com/ds/54/5408.pdf
SR - Latch (NOR version) (1)

R Q SR - Latch
NOR
S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
S NOR Q' 1 1 ?
Characteristic table
(state transition table)
NOR
x1 x2 F Unclocked latch
S Q
0 0 1 has no
0 1 0 enable/clock
1 0 0 R Q’ input signal
1 1 0
Note: sometimes also
called RS - latch

Slide 9
SR - Latch (NOR version) (2)
Because R=1
1
R 0 0
Q SR - Latch
NOR
S R Q(t+1)
0 0 Q(t)
0 1 0
0
1 0 1
S NOR Q' 1 1 ?
0 1

NOR
x1 x2 F S Q Unclocked latch
0 0 1 has no
0 1 0 enable/clock
1 0 0 R Q’ input signal
1 1 0

Slide 10
SR - Latch (NOR version) (3)

0
R Q SR - Latch
NOR
S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
S NOR Q' 1 1 ?
0

NOR
x1 x2 F
0 0 1
R=0, F is complement of 2ed input, but this is Q', so F=Q''=Q, no change
0 1 0
1 0 0 Same situation for S
1 1 0

Slide 11
 SR - Latch (NOR version) (4)

0
R Q SR - Latch
NOR
S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
S NOR Q' 1 1 ?
0

Verilog code Verilog simulation output

module SRnor(S, R, Q, Qbar);
input S, R;
output Q, Qbar;

assign Q = ~(R | Qbar);

assign Qbar = ~(S | Q);
endmodule

reset set transfer invalid

state
Slide 12
 S’R’ - Latch - NAND version (1)

1 SR - Latch
Note S’ 0
1 NAND Q S’ R’ Q(t+1)
1) the change of S w.r.t.
Q 0 0 ?
2) The characteristic 0 1 1
table is ‘reversed’ due 0 1 0 0
to the NANDs 1 NAND Q' 1 1 Q(t)
R’ 1

NAND
x1 x2 F Unclocked latch
S Q
0 0 1 has no
0 1 1
enable/clock
1 0 1 R Q’ input signal
1 1 0

Slide 13
 S’R’ - Latch - NAND version (2)

Note S’ SR - Latch
NAND Q
1) the change of S w.r.t. S’ R’ Q(t+1)
Q 0 0 ?
2) The characteristic 0 1 1
table is ‘reversed’ due 1 0 0
to the NANDs NAND Q'
R’ 1 1 Q(t)
Function table is often written
S’R’ starting at minterm 0
NAND
x1 x2 F Unclocked latch
S Q
0 0 1 has no
0 1 1
enable/clock
1 0 1 R Q’ input signal
1 1 0

Slide 14
Clocked SR - Latch (NOR version)

R
Q SR - Latch
NOR
S R Q(t+1)
0 0 Q(t)
Clock
0 1 0
1 0 1
NOR Q' 1 1 ?
S
Clock = 1, SR latch operates as per un-clocked version
Clock = 0, SR latch inputs forced zero

S Q latches may show

Latches are level sensitive: output is
E for an enable
E obtained after propagation time from
signal or C for a
R Q’ input AND clock level
clock signal
Slide 15
 Clocked SR - Latch (NAND version) (1)

Note the change S Q SR - Latch

of S w.r.t. Q S R Q(t+1)
Clock 0 0 Q(t)
0 1 0
1 0 1
R 1 1 ?

NAND
x1 x2 F
0 0 1
0 1 1
1 0 1
1 1 0

S Q latches may show

Latches are level sensitive: output is
E for an enable
E obtained after propagation time from
signal or C for a
R Q’ input AND clock level
clock signal
Slide 16
Clocked SR - Latch (NAND version) (2)

S 1 SR - Latch
Q
0 S R Q(t+1)
No 0 0 Q(t)
Clock
Change
0 0 1 0
1 0 1
R 1 1 1 ?
Note: function
NAND NAND table as SR
x1 x2 F x1 x2 F
NOR latch
0 0 1 0 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0
clock: negative level
1 1 0
Q = Q’’

S Q latches may show

Latches are level sensitive: output is
E for an enable
E obtained after propagation time from
signal or C for a
R Q’ input AND clock level
clock signal
Slide 17
 Clocked SR - Latch (NAND version) (3)

S S’ SR - Latch
Q
1 S R Q(t+1)
Clock 0 0 Q(t)
1 0 1 0
1 0 1
R R’ 1 1 ?

NAND
x1 x2 F
0 0 1 clock: positive level
0 1 1
1 0 1
F is complement
1 1 0

Slide 18
Svg updated
Clocked SR - Latch (NAND version) (3)

0 S S’ 1 0 SR - Latch
Q
1 S R Q(t+1)
Clock 0 0 Q(t)
1 1 0 1 0
1 0 1
1 R R’ 0 1 1 ?
Reset: Q=0
NAND NAND
x1 x2 F x1 x2 F
NAND 0 0 1 0 0 1
x1 x2 F 0 1 1 F=1 0 1 1
0 0 1 clock: positive level 1 0 1 1 0 1
0 1 1 1 1 0 1 1 0
1 0 1
F is complement
1 1 0

Slide 19
Clocked D - Latch

S Q SR - Latch
S R Q(t+1)
Clock 0 0 Q(t)
0 1 0
1 0 1
R 1 1 ?

Wire D to S and invert D to R thereby

eliminating 00 and 11 from state table

Slide 20
 Latches and flip flops (Overview)
• Latch: Unclocked or level sensitive device
Level sensitive
S Q Unclocked latch S Q latches may show
has no
E E for an enable
enable/clock
R Q’ R Q’ signal or C for a
input signal
clock signal

• Flip-flop: edge-sensitive device

S Q S Q S Q S Q
clk clk
R Q’ R Q’ R Q’ R Q’

Positive Negative Positive Negative

edge edge pulse pulse
triggered triggered triggered triggered
• Terms, definitions and symbols may vary from source to source. Those used here
have been compiled from multiple sources with the aim to be as correct and
consistant as possible. Slide 21
Common Types of Latches / Flip-flops
Characteristic table
(state transition table)
S R Q(t)
S Q 0 0 Q(t-1)
• SR Flip-Flop 0 1 0
R
1 0 1
1 1 ?

D Q D Q(t)
• D Flip-Flop 0 0
Q'
1 1

J K Q(t)
J Q
0 0 Q(t-1)
• JK Flip-Flop K Q'
0 1 0
1 0 1
1 1 Q'(t-1)

T Q
T Q(t)
0 Q(t-1)
• T Flip-Flop Q'
1 Q'(t-1)
Slide 22
Note: rising edge triggered shown
 SR flip flop (master-slave) (1)
Flip flops are edge sensitive: output is Left circuit Thus, the falling edge
synchronizes both circuits.
obtained after propagation time from
clock edge. Input may be sampled at
clock edge (edge triggered) or at clock Right circuit
level (pulse triggered).

S
Q

Clock This latch activates

any time during positive level

S Q Negative
clk pulse
R Q’ triggered
Slide 23
 SR flip flop (master-slave) (2)
Flip flops are edge sensitive: output is Left circuit Thus, the falling edge
synchronizes both circuits.
obtained after propagation time from
clock edge. Input may be sampled at
clock edge (edge triggered) or at clock Right circuit
level (pulse triggered).

S
Q

Clock This latch activates

at the start of negative level

S Q Negative
clk pulse
R Q’ triggered
Slide 24
D Flip Flop: positive edge triggered
Positive edge triggered, therefore,
the input D must be stable setup
D Q(t)
time before the edge, therefore, 0 0
D must have a specified value
during the clock’s negative level.
1 1

Clk S’
1
0
(Mano
0 notation)

1 R’

NAND SR - Latch
x1 x2 F S’ R’ Q(t+1)
0 0 1 0 0 ?
0 1 1 0 1 1
1 0 1 1 0 0
1 1 0 1 1 Q(t)
D Flip Flop: positive edge triggered (1)
Positive edge triggered, therefore,
the input D must be stable setup
D Q(t)
time before the edge, therefore, Note: D is transferred to 0 0
D must have a specified value this gate’s output before
during the clock’s negative level.
1 1
the positive edge

Clk S’
1
0
(Mano
0 notation)

1 R’

NAND SR - Latch
x1 x2 F S’ R’ Q(t+1)
0 0 0 1 0 0 ?
Note: D’ is the output
0 1 1 0 1 1
of this gate. 1 0 1 1 0 0
1 1 0 1 1 Q(t)
D Flip Flop: positive edge triggered (1)
Positive edge triggered, therefore,
the input D must be stable setup
D Q(t)
time before the edge, therefore, Note: D is transferred to 0 0
D must have a specified value this gate’s output before
during the clock’s negative level.
1 1
the positive edge

Clk S’
1
0
(Mano
0 notation)

1 R’

NAND SR - Latch
x1 x2 F S’ R’ Q(t+1)
1 0 0 1 0 0 ?
Note: D’ is the output
0 1 1 0 1 1
of this gate. 1 0 1 1 0 0
1 1 0 1 1 Q(t)
D Flip Flop: positive edge triggered (1)
Positive edge triggered, therefore,
the input D must be stable setup
D Q(t)
time before the edge, therefore, Note: D is transferred to 0 0
D must have a specified value this gate’s output before
during the clock’s negative level.
1 1
the positive edge

Clk S’
1
0
(Mano
0 notation)

1 R’

NAND SR - Latch
x1 x2 F S’ R’ Q(t+1)
0 0 1 0 0 ?
Note: D’ is the output
0 1 1 0 1 1
of this gate. 1 0 1 1 0 0
1 1 0 1 1 Q(t)
D Flip Flop: positive edge triggered (1)
Positive edge triggered, therefore,
the input D must be stable setup
D Q(t)
time before the edge, therefore, Note: This is the 0 0
D must have a specified value
during the clock’s negative level.
complement of the inputs 1 1

1 Note: This is the complement of the inputs, therefore the

complement of the complement maintains the original signal
Clk S’
0
(Mano
1 notation)

R’
The inputs to the RS-latch are maintained when
Clk=1, therefore, Q remains unchanged.

After th, any NAND SR - Latch

change to D x1 x2 F S’ R’ Q(t+1)
has no effect
0 0 1 0 0 ?
Note: D’ is the output
0 1 1 0 1 1
of this gate. 1 0 1 1 0 0
1 1 0 1 1 Q(t)
D Flip Flop: positive edge triggered (1)
Positive edge triggered, therefore,
the input D must be stable setup
D Q(t)
time before the edge, therefore, Note: D is transferred to 0 0
D must have a specified value this gate’s output before
during the clock’s negative level.
1 1
the positive edge
1
Clk S’
0
(Mano After tp, Q is
1 notation) set or reset

R’
At positive edge, the inputs to this NAND RS-
latch are complements, either m1 or m2

NAND SR - Latch
x1 x2 F S’ R’ Q(t+1)
0 0 1 0 0 ?
Note: D’ is the output
0 1 1 0 1 1
of this gate. 1 0 1 1 0 0
1 1 0 1 1 Q(t)
D Flip Flop: positive edge triggered (3)

D Q(t)
1 0 0
Clk 1 1

D=1 → Q=1 D=0 → Q=0

transition at +edge transition at +edge
D Flip Flop: positive edge triggered (4)
w1
g1
D Q(t)
0 0
1 1

g2 w2
g5

g6
g3
w3
module dff(clk, D, Q, Qbar);
input D, clk;
output Q, Qbar;
wire w1, w2, w3, w4;

g4 nand g1 (w1, w2, w4);

w4 nand g2 (w2, w1, clk);
nand g3 (w3, w2, clk, w4);
nand g4 (w4, D, w3);

always begin nand g5 (Q, w2, Qbar);

#2 clk = ~clk; // toggle clock nand g6 (Qbar, w3, Q);
end endmodule
JK Flip Flop
D Q D Q(t)
J 0 0
Q'
D Q 1 1
Clk
K
Q'
J K Q(t)
J Q
0 0 Q(t-1)
0 1 0
K Q' 1 0 1
1 1 Q'(t-1)
J K D = JQ’ + K’Q
0 0 Q(t-1)
0 1 0
1 0 1 ( because of Axiom #7: Q’ + Q = 1)
1 1 Q'(t-1)

Slide 33
Flip-flop Timings
1
D Q
Clock
Q'
0
1 tsu: minimum amount of time needed
D tsu th
before clock event (edge) for stable
0 data signal
1 tp
Q th: minimum amount of time needed after
tco
0
clock event (edge) for stable data signal

tp (tco): maximum propagation time of device after clock event (also

called “clock to Q”)

Slide 34
 Intro. Static Timing Analysis (STA)
Circuit model: Single cycle clock period
(one clock period) from
launch flip flop to capture D Q logic D Q

flip flop
launch capture
Clk logic

tp tL tsu
tskew

Setup Check:
+
T = tp + tL + tsu + 2tj - tskew
max max min
(Alternatively + tskew)

Hold Check:
tskew + th  tp + tL - 2tj
max min max

Clock period Check:

T ≥ tsu + th
Slide 35
Intro. Static Timing Analysis (STA) E.g. 1
T

1 NOT: tphl: 1ns

tplh: 2ns
Clock D FF: tsu: 3ns
D Q
0 th: 1ns
Q' t(D FF)
tp: 4ns
t(NOT) Tj: assume 0ns
tsu

Setup Check:
+
T = tp + tL + tsu + 2tj - tskew
max max min
T = 4 +2 +3 +0 -0 = 9ns
Hold Check:
tskew + th  tp + tL - 2tj
max min max
0 +1  4+1 -0 okay
Clock period Check:
T ≥ tsu + th
9≥3 +1 okay Slide 36
Intro. Static Timing Analysis (STA) E.g. 2
A NOT: tphl: 2ns
B D Q D Q Y
tplh: 1ns
NAND: tphl: 4ns
launch capture tplh: 3ns
Clk D FF: tsu: 3ns
Data path: A to Y (boundary to capture) Boundary delay is the delay in th: 3ns
the signal before it arrives to the tp: 4ns
Data path: B to Y (launch to capture)
input line (wire): assume zero
delay unless otherwise stated. Tj: assume 0ns
Setup Check (B to Y):
+
T = tp + tL + tsu + 2tj - tskew
max max min
T = 4 +6 +3 +0 -1 = 12ns
Hold Check (A to Y): Here tp is the boundary delay
tskew + th  tp + tL - 2tj
max min max
2 +3  0+3 -0 Not okay
Clock period Check:
T ≥ tsu + th
12 ≥ 3 + 3 okay Slide 37
Intro. Static Timing Analysis (STA) E.g. 2
Shortest path Changes too fast, so
A 3ns the requirement fails NOT: tphl: 2ns
B D Q D Q Y
tplh: 1ns
NAND: tphl: 4ns
tplh: 3ns
Clk D FF: tsu: 3ns
5ns requirement th: 3ns
Data path: A to Y (boundary to capture)
Data path: B to Y (launch to capture) tp: 4ns
Tj: assume 0ns
Setup Check (B to Y):
+
T = tp + tL + tsu + 2tj - tskew
max max min
T = 4 +6 +3 +0 -1 = 12ns
Hold Check (A to Y): Here tp is the boundary delay
tskew + th  tp + tL - 2tj
max min max
2 +3  0+3 -0 Not okay
Clock period Check:
T ≥ tsu + th
12 ≥ 3 + 3 okay Slide 38
Intro. Static Timing Analysis (STA) E.g. 2
Shortest path
A 3ns NOT: tphl: 2ns
2ns
B D Q D Q Y
tplh: 1ns
NAND: tphl: 4ns
tplh: 3ns
Clk D FF: tsu: 3ns
5ns requirement th: 3ns
Data path: A to Y (boundary to capture)
Data path: B to Y (launch to capture) tp: 4ns
Tj: assume 0ns
Setup Check (B to Y):
+
T = tp + tL + tsu + 2tj - tskew
max max min
T = 4 +6 +3 +0 -1 = 12ns
Hold Check (A to Y): Here tp is the boundary delay
tskew + th  tp + tL - 2tj
max min max
2 +3  0+5 -0 okay
Clock period Check:
T ≥ tsu + th
12 ≥ 3 + 3 okay Slide 39
Intro. Static Timing Analysis (STA) E.g. 2
Shortest path
A 3ns NOT: tphl: 2ns
2ns
B D Q D Q Y
tplh: 1ns
NAND: tphl: 4ns
tplh: 3ns
Clk D FF: tsu: 3ns
5ns requirement th: 3ns
Data path: A to Y (boundary to capture)
Data path: B to Y (launch to capture) tp: 4ns
Tj: assume 0ns
Setup Check (B to Y):
+
T = tp + tL + tsu + 2tj - tskew
max max min
T = 4 +6 +3 +0 -1 = 12ns
In this example, buffering shortest path is a solution;
Hold Check (A to Y): but, in general, additional analysis may be needed
tskew + th  tp + tL - 2tj
max min max
2 +3  0+5 -0 okay
Clock period Check:
T ≥ tsu + th
12 ≥ 3 + 3 okay Slide 40
 State Models
The Moore Finite State Machine (FSM): outputs determined by the current
state, transitions between states enabled by system inputs.

Input
Variables
x
x=1
State 0 1
Variables Ctrl 1 = Ctrl 1 = Output
A Ctrl 2 = Ctrl 2 = Variables
0 : state 0 Ctrl n = Ctrl n = Control Signals
1 : state 1
x=1
x=0 x=0
2 states,
therefore 1 state variable called A

Slide 41
State Models
ALU data ALU
inputs output ALU control signal inputs

Both rows show

x=1 correct answers
Ainvt=0 Ainvt=0
Binvt=0 Binvt=0
Op=010 Op=010
Ci=0 Ci=0
x=1
x=0 x=0
Step 1
1
x x + 2y = x + (y+y)
0 Step 1 Step 2 Step 1 Step 2
Slide 42
8-State (3-bit) Binary Counter
0

1 7
Circuit Excitation Table (State Table Changes)

A B C A B C
8 state (3-bit)
2 6
counter.

3 5

Let x be an external input

that when 0 leaves the
counter in steady-state
but when 1 advances the
counter.

Slide 43
8-State (3-bit) Binary Counter
States are represented by bits.
0 Label the state bits as ABC
with C the least significant Circuit Excitation Table
1 7 (State Table Changes)

A B C A B C
8 state (3-bit)
2 6
counter

3 5

State transition model, represent each type

of state-to-state transition as a bit: usually, 0
means no transition, 1 means transition.

Represents the graphical picture JK Flip-flop input

design requirements Slide 44
8-State (3-bit) Binary Counter
X=0
X=1 0

1 7
Circuit Excitation Table (State Table Changes)
X=1
A B C A B C
8 state (3-bit)
2 6
counter

3 5

Slide 45
8-State (3-bit) Binary Counter
J K Q(t)
0 0 Q(t-1) Circuit Excitation Table (State Table Changes)
0 1 0
1 0 1 A B C A B C
1 1 Q'(t-1)

J-K Flip-Flop Characteristic Table

0 → 0: J=0, K=x

0 → 0: J=0, K=x

0 → 1: J=1, K=x

Slide 46
8-State (3-bit) Binary Counter
Simplify

C x
Circuit Excitation Table (State Table Changes)

A B C A B C

A B

Slide 47
16-State (4-bit) Binary Counter

Note the pattern

Slide 48
Register
a0
D Q

Q'

a1
D Q

Q'
Clk

a2
D Q

Q'

a3
D Q

Q'
Parallel Load: a3a2a1a0 is clocked into the 4-
bit register

Slide 49
Register
D Q

Q'

D Q

Q'
Clk

D Q

Q'

D Q

Q'
Memory Load: because D Flip-flop is used,
the output must be wired to the input to
implement the transfer function.
Slide 50
Register
load

D Q
a0
Q'

D Q
a1
Q'
Clk

D Q
a2
Q'

D Q
a3
Q'
Control Signal Table (2-1 mux)
Load Register Operation
0 Memory
1 Parallel Load Slide 51
Register
load
0

D Q
a0
Q'

D Q
a1
Q'
Clk

D Q
a2
Q'

D Q
a3
Q'
Control Signal Table (2-1 mux)
Load Register Operation
0 Memory
1 Parallel Load Slide 52
Register
load
1

Clk
D Q
a0
Q'

load
D Q
a1
Q'
Clk a is clocked into
the register
(assuming rising
edge triggered
D Q
a2
Q'

D Q
a3
Q'
Control Signal Table (2-1 mux)
Load Register Operation
0 Memory
1 Parallel Load Slide 53
Register
load
2-1 Multiplexer: F = load Q + load’ ai

D Q
a0
Q'

D Q
a1
Q'
Clk

D Q
a2
Q'

D Q
a3
Q'
Control Signal Table (2-1 mux)
Load Register Operation
0 Memory
1 Parallel Load Slide 54
Register load

0
D Q
a0 1
Q'

0
a1 D Q
1
Q'
Clk

0
a2 D Q
1
Q'

0
a3 D Q
1
Q'
Control Signal Table (2-1 mux)
Load Register Operation
0 Memory
1 Parallel Load Slide 55
Register (bit labeling) load

0
D Q
a0 1
F(ABCD) A Q' F(DCBA)
0
a1 D Q
1
B Q'
Clk

0
a2 D Q
1
C Q'
F(A0A1A2A3) F(A3A2A1A0)
0
a3 D Q
1 Lecture notes
e.g.old Mano textbook (e.g. Table 2-4) D Q'

Slide 56
Shift Register Control Signals
S1 S0 Reg Op
0 0 no change
0 1 serial shift left
1 0 serial shift right
1 1 load

Slide 57
Shift Register Control Signals
S1 S0 Reg Op
0 0 no change
0 1 serial shift left
1 0 serial shift right
1 1 load

Slide 58
Shift Register Control Signals
S1 S0 Reg Op
0 0 no change
0 1 serial shift left
1 0 serial shift right
1 1 load

Slide 59
 Register File

Q'

Q'

Q'

Q'
Q

Q
Control Signal Table (2-1 mux)
Load Register Operation

D
0 Memory
1 Parallel Load

0
0
1

0
1

1
0
1
Control path

Clk
Encoded load
register 2-1 a3 a2 a1 a0
decoder 4 3 2
number

Q'

Q'

Q'

Q'
Q

Q
D

D
0
0
1

0
1

1
0
1

Clk
load
a3 a2 a1 a0
4 3 2
Data path
a3a2a1a0 Slide 60
Register Number
x1 x0

Q'
Q'

Q'

Q'
Q

Q
D

D
0
1

0
1
0
1

0
1

Clk

Q'
Q'

Q'

Q'
Q

Q
D

D
1
0

0
1
0
1

0
1

Clk
not used

Q'
Q'

Q'

Q'
Q

Q
Control Signal Table (2-1 mux)
Load Register Operation

D
0 Memory
1 Parallel Load

1
0

0
1
0
1

0
1

Clk
Slide 61
a3a2a1a0
Register Number Example:
x1 x0

Q'
Q'

Q'

Q'
writing to R1

Q
D

D
Control path

0
1

0
1
0
1

0
1

Clk

Q'
Q'

Q'

Q'
Q

Q
D

D
1
0

0
1
0
1

0
1

Clk
not used

Q'
Q'

Q'

Q'
Q

Q
Control Signal Table (2-1 mux)
Load Register Operation

D
0 Memory
1 Parallel Load

1
0

0
1
0
1

0
1

Clk
Data path
Slide 62
a3a2a1a0
Register File (simplified Diagram)
Register
Number
x1 x0

Q'

Q'

Q'

Q'
Q

Q
D

D
Clk
Q'

Q'

Q'

Q'
Q

Q
D

D
Clk
Q'

Q'

Q'

Q'
Q

Q
4

D
a3 a2 a1 a0

Clk
a3a2a1a0
Slide 63
Register File (simplified Diagram)

Q'

Q'

Q'

Q'
Q

Q
load

D
Clk
Register
Number

Q'

Q'

Q'

Q'
Q

Q
2 to 4

D
Line
decoder

Clk
Q'

Q'

Q'

Q'
Q

Q
4

D
a3 a2 a1 a0

Clk
a3a2a1a0
Slide 64
Register File

Q'

Q'

Q'

Q'
Q

Q
D

D
Clk
Register
Number

Q'

Q'

Q'

Q'
Q

Q
0 2 to 4

D
1 Line
decoder

Clk
Q'

Q'

Q'

Q'
Q

Q
4

D
a3 a2 a1 a0

Clk
a3a2a1a0
Slide 65
Register File (MIPS)

Rs

Rt

Rd

Slide 66
 Register File (MIPS)

Rs

Rt

Rd

5x32 decoder

register

AND gate

Slide 67
Register File (MIPS)
Control signal
control path Only 1 AND gate enabled
from each decoder

Data Rs
source
control
paths Rt

Data Rd
Destination
control paths

Slide 68
Register File (MIPS)

Data path

Rs

Rt

Rd

Slide 69
Register File (MIPS)
Control signal
control path

00000 Rs

00001 Rt

11111 Rd

Slide 70
Register File (MIPS)
Control signal
control path

ALU
00000 Rs control

00001 Rt

11111 Rd

Slide 71
Register File (MIPS)

ALU
00000 Rs control

00001 Rt

11111 Rd

Slide 72
 Register File (MIPS)
Register Transfer
Language (RTL)
Registers are a
basic data unit of
digital systems
Rd ← Rs op Rt
ALU
00000 Rs control

00001 Rt

11111 Rd

In this example
R31 ← R0 + R1

Slide 73
 Register File (MIPS)
Register Transfer
Language (RTL)
Registers are a
basic data unit of
digital systems
Rd ← Rs op Rt

The architecture
supports RTL
design
requirements;

RTL operations
may be limited
by the architecture.

For this
architecture
the following are
examples of unsupported RTL operations
Note: some architectures, e.g. PowerPC
R0 ← Rs op Rt R0 ← Rs op1 Rt op2 Ru and Itanium support multiply-add Slide 74
instruction (Rd=Rs*Rt+Ru)
 Register File (MIPS)
Registers
may be
specified
in a special
register
called the
Instruction
Register (IR).

The IR gets
its
bit pattern
from the
executable
program