Digital VLSI Design

Lecture 9:
Routing
Semester A, 2018-19
Lecturer: Dr. Adam Teman

January 25, 2019

Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
please feel free to email [email protected] and I will address this as soon as possible.
 Routing: The Problem
• Scale
• Millions of wires
• MUST connect them all
• Geometric Complexity
• Basic starting point – grid representation.
• But at nanoscale – Geometry rules are complex!
• Also, many routing layers with different “costs”.
• Electrical Complexity
• It’s not enough to just connect all the wires.
• You also have to:
• Ensure that the delays through the wires are small.
• Ensure that wire-to-wire interactions (crosstalk)
doesn’t mess up behavior.
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 Problem Definition
• Problem:
• Given a placement, and a fixed number of metal layers, find a valid pattern
of horizontal and vertical wires that connect the terminals of the nets.
• Input: • Objective
• Cell locations, netlist • 100% connectivity of a system
• Minimum area, wirelength
• Output:
• Geometric layout of each net • Constraints
connecting various standard cells • Number of routing layers
• Design rules
• Two-step process • Timing (delay)
• Global routing • Crosstalk
• Detailed routing • Process variations
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Lecture Contents

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 2 2
1
Routing Routing in
Intro
Algorithms Practice

Routing Algorithms

This section is heavily based on Rob Rutenbar’s “From Logic to Layout”,

Lecture 11 from 2013. For a better ☺ and more detailed explanation, do
yourself a favor and go see the original!
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Grid Assumption
• Despite the complexity of nanoscaled routing, we will use a grid assumption
and add the complexity in later.
• Layout is a grid of regular squares Target
• A legal wire is a set of connected grid T
cells through unobstructed cells.
• Obstacles (or blockages) are marked
in the grid. Obstacle
• Wires are strictly horizontal and vertical
(Manhattan Routing) S
• Paths go
Source
• North/South
• East/West.

© Adam Teman, 2018

 Maze Routers
• Also known as “Lee Routers”
• C. Y. Lee, “An algorithm for path connections and its applications” 1961
• Strategy:
• Route one net at a time.
• Find the best wiring path for the current net.
• Problems:
• Early wired nets may block path of later nets.
• Optimal choice for one net may block others.
• Basic Idea:
• Expand → Backtrace → Cleanup
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 Maze Routing: Expansion
• Start at the source. 3 2 3 4 5 6
• Find all paths 1 cell away.
• Continue until reaching the target. 2 S1 2 3 4 5
• We approach the target with a
“wavefront” 3 2 3 4 5 6
• We found that the shortest path to
the target is 6 unit steps. 4 3 4 5 6

5 4 5 T
6

6 5 6

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 Maze Routing: Backtrace & Cleanup
• Backtrace: 3 2 3 4 5 6
• Follow the path lengths backwards in
descending order.
• This will mark a shortest-path to the target.
2 S1 2 3 4 5

• However, there may be many shortest 3 2 3 4 5 6

paths, so optimization can be used to
select the best one.
4 3 4 5 6
• Cleanup
• We have now routed the first net.
• To ensure that future nets do not try to use
5 4 5 T
6

the same resources, mark the net path 6 5 6

from S to T as an obstacle.
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 Maze Routing: Blockages
• How do we deal with blockages?
• Easy. Just “go around” them!
4 5 T6
3
To summarize:
• Expand: 2 S1 2
• Breadth-first-search (BFS) to find all
paths from S to T in path-length order. 3 2 3
• Backtrace:
• Walk shortest path back to source. 4 3 4
• Cleanup:
5 4 5 6
• Mark net as obstacle
and erase distance markers.
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 Multi-Point Nets
• How do we go about routing a net with 4 3 4
multiple targets?
• Actually, pretty straightforward.
• Start with our regular maze routing
3 2 3 TS4
algorithm to find the path to the nearest
target.
2 S1 S2 S3 4

• Then re-label all cells on found path as 3 2 3 4

sources, and re-run maze router using all
sources simultaneously.
4 3 4

4 T
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 Multi-Point Nets
• How do we go about routing a net with 4 3 3 2 3
multiple targets?
• Actually, pretty straightforward.
• Start with our regular maze routing
3 2 2 S1 2 3

algorithm to find the path to the nearest

target.
2 S1 S1 S1 2 3

• Then re-label all cells on found path as 3 2 2 2 3 4

sources, and re-run maze router using all
sources simultaneously.
4 3 3 3 4 5
• Repeat until reaching all target points.
Note that this does not guarantee the
shortest path (=“Steiner Tree”)
5 4 4 4 T5
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 Multi-Layer Routing
• Okay, so what about dealing with several routing layers?
• Same basic idea of grid – one grid for each layer.
• Each grid box can contain one via.
• New expansion direction – up/down.

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 Multi-Layer Routing
3 2 3 4 5 6

2 S1 2 3 4 5 8

3 2 3 5 6 8 7 6 7 8

4 3 V
4 6 7 7 6 V
5 6 7 8

5 4 5 7 V
8 8 7 6 7 T8 V
6 5 6 7 8 8 7 8

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Metal 1 Metal 2 © Adam Teman, 2018
 Non-Uniform Grid Costs
• But we know that vias have (relatively) high resistance.
• Shouldn’t we prefer to stay on the same metal layer?
• We also prefer Manhattan Routing
• Each layer is only routed in one direction.
• A “turn” requires going through a via or a “jog” should be penalized.
• Is there a way to prefer routing in a certain layer/direction?

• Yes.
• Let’s introduce non-uniform grid costs.

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 Multi-Layer Routing
Cost of Via = 10

11 12 13 14 15 16

S1 2 V
3 4 5 6 23 V
13

15 16 24 14

T
26 V
25 26 25 26 25 V
15

35 35 26 16
Cost of wrong
way route = 10 27 17 27

Vertical
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Horizontal Metal 1 Metal 2 © Adam Teman, 2018
 How do we implement this?
• Grids are huge.
• Assume 1cm X 1cm chip. All of this is hard!
• Assume 100 nm track
• Assume 10 routing layers
• That is 1010 (100 billion) grid cells!
• We need a low cost representation
• Only store the wavefront. Use many different heuristics:
• Remember which cells have been
• Which net to route first
reached, at what cost, and from
which direction. • Bias towards the right direction
• Use Dijkstra’s algorithm to find the • How to go about fixing problems
cheapest cell first. • etc., etc., etc.
17 • Store data in a heap. © Adam Teman, 2018
 Divide and Conquer: Global Routing
• To deal with a big chip, we make our problem smaller
• Divide the chip into big, course regions
• e.g., 200 X 200 tracks each.
• These are called GBOXes.
• Now Maze Route through the GBOXes

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 Divide and Conquer: Global Routing
• Global routing takes care of basic congestion.
• Balances supply vs. demand of routing resources.
• Generates regions of confinement for the wires.
• Detailed routing decides on the exact path.

GBOXes have a
dynamic cost
according to how
congested they are!

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 2 2
1
Routing Routing in
Intro
Algorithms Practice

Routing in practice

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Layer Stacks
• Metal stacks are changing W2

(and growing)
U2 W1 Intel 45nm 8 metal stack
Representative layer stacks for
130 nm - 32 nm technology
U1
nodes E2

E2 E1 E1
B3
E1 B3
B2
B2 B3 B1 B2
M6 B1 B2 C2 B1
UMC 6 metal stack
M5 M5 B1 C1 M5
M4 M4 M4 M4 M4
M3 M3 M3 M3 M3
M2 M2 M2 M2 M2
M1 M1 M1 M1 M1
130 nm 90 nm 65 nm 45 nm 32 nm

© Adam Teman, 2018

 Global Route
• Divide floorplan into GCells
• Approximately 10 tracks
per layer each.
Vertical routing

• Perform fast grid routing: capacity = 9

tracks

• Minimize wire-length Y

• Balance Congestion
Horizontal routing
• Timing-driven capacity = 9
tracks
• Noise/SI-driven
• Keep buses together X

• Also used for trial route

• During earlier stages of the flow X
Y

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 Congestion map

Congestion Map
• Use congestion map and report to
examine design routability

Congestion Report
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# Metal 1 H 7607 9692 1336335 62.57%
# Metal 2 H 7507 9792 1336335 55.84%
# Metal 3 V 7636 9663 1336335 59.51%
# Metal 4 H 8609 8691 1336335 52.02%
# Metal 5 V 5747 11551 1336335 56.39%
# Metal 6 H 5400 11899 1336335 55.09%
# Metal 7 V 1831 2486 1336335 55.30%
# Metal 8 H 2415 1903 1336335 43.85%
# --------------------------------------------------------------
# Total 46753 56.99% 10690680 55.07%
#
# 589 nets (0.47%) with 1 preferred extra spacing.
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 Detailed Route Detailed Route Boxes Solve
shorts
• Using global route plan,
within each global route cell
Notch
• Assign nets to tracks Spacing
• Lay down wires
• Connect pins to nets Notch
• Solve DRC violations Spacing
• Reduce cross couple cap
• Apply special routing rules
Thin&Fat
• Flow: Spacing

• Track Assignment (TA) Min

• DRC fixing inside a Global Routing Cell (GRC) Spacing

• Iterate to achieve a solution (default ~20 iterations)

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Timing-Driven Routing
• Optimize critical paths
• Route some nets first
• Most routing freedom at start
• Use shortest paths possible
• Net weights
• Order of routing (priorities: e.g., Default : Clocks 50, others 2)
• Wire widening
• Reduce resistance
• If you have a congested design you may need to set the timing
driven effort to “low”
• Beware when changing default options
© Adam Teman, 2018
 Signal Integrity (SI)
• Signal Integrity during routing is synonymous with Crosstalk.
• A switching signal may affect a neighboring net.
• The switching net is called the Aggressor.
• The affected net is called the Victim.
• Two major effects:
net 1 Aggressor
• Signal slow down
• When the aggressor and victim
switch in opposite directions. net 2 Victim
• Signal speed up
• When the aggressor and victim
switch in the same direction.
Speed Up Delay

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 SI Multi-Aggressor Timing Analysis
• Infinite Window Analysis
• An infinite noise window Net X
aggressor
applies the maximum delay
Net Y
due to crosstalk during timing analysis. aggressor
• This model was sufficient for older (pre-90nm)
technologies, but became too severe with the Noise bumps on net C

growing sidewall capacitances at scaled nodes. Crosstalk

noise from

• Propagated Noise Analysis

X
Crosstalk
noise from Y
• Min/Max vectors are propagated through the design to
Propagated
create a transition window for all aggressors in relation noise from B
to a certain victim. Worst-case
• Noise is only applied at the overlap of the two combination of noise
bumps on net C
windows to determine the worst case noise bump.
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 Signal Integrity - Solutions
• Crosstalk Prevention Increasing
wire
• Limit length of parallel nets Upsizing spacing Adding shielding
victim
• Wire spreading driver Inserting buffer
• Shield special nets
Critical Nets
• Upsize driver or buffer
Grounded shields
Extra space

Shielding
Same layer (H)
Spacing Wire Spreading Adjacent layers (V)
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Net Ordering
 Design For Manufacturing
• During route, apply additional
design for manufacturing (DFM)
and/or design for yield (DFY) rules:
• Via reduction
• Redundant via insertion
Wire straightening (reduce jogs)
• Wire straightening
• Wire spreading

Avoid
asymmetrical
contacts
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 DFM: Via Optimization
• Post-Route Via Optimization, includes:
• Incremental routing for the minimization of vias.
• Replacement of single vias with multi-cut vias.
• These operations are required for:
• Reliability:
• The ability to create reliable vias decreases with each process
node. If a single via fails, it creates an open and the circuit is extra vias
useless. added
• Electromigration:
• Electromigration hazards are even more significant in vias,
which are essentially long, narrow conductors.

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 DFM: Wire Spreading • High-density
critical area
• High probability of
yield-killing defect
• Wire spreading achieves:
• Lower capacitance and better signal integrity.
• Lower susceptibility to shorts or opens due to
random particle defects.
• Density reduced,
yield risk reduced
• No timing impact!
Center of conductive defects within Center of non-conductive defects within
critical area – causing shorts critical area – causing opens
Metal 3
+ +
+ + + +
+ +
Center of conductive defects Critical Areas Center of non-conductive defects
outside critical area – no shorts outside critical area – no opens

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 Routing in Innovus/Encounter
• The detailed routing engine used by Innovus/Encounter is called “NanoRoute”
• NanoRoute provides concurrent timing-driven and SI-driven routing.
• In addition, it can perform multi-cut via insertion, wire widening and spacing.
• The commands for running a route with NanoRoute are:
set_db route_design_with_timing_driven true
set_db route_design_with_si_driven true
route_design

• Following detailed route wire optimization and timing optimization:

set_db route_design_with_timing_driven false
set_db route_design_detail_post_route_spread_wire true
set_db route_design_detail_use_multi_cut_via_effort high
route_design –wire_opt
set_db route_design_with_timing_driven true
opt_design –post_route –setup -hold
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Routing in Innovus/Encounter
• To achieve a high percentage of multi-cut vias:
set_db route_design_concurrent_minimize_via_count_effort high
set_db route_design_detail_use_multi_cut_via_effort high

• To check your design after routing:

report_route; # provide routing statistics
report_wires; # provides wire statistics including wirelength
time_design –post_route; # check timing after routing
check_drc; # Run a DRC check – in new techs: “verify_drc”
check_connectivity; # Run an LVS check

• To perform incremental routing (ECO routing):

set_db route_design_with_eco true
route_global_detail
© Adam Teman, 2018
 The Chip Hall of Fame
• With RISC processors a central part of our computing lives
today, we should really thank the revolution of the

Photo: Mark Richards

• Scalable Processor Architecture
SPARCstation 1+ “pizzabox”
• Release date: 1987 SPARC v7 32-bit Architecture
• The first major commercial RISC processor taking
Patterson’s ideas at Berkeley into a product.
• “SPARC will take Sun from a $500M/year company to a
$1B/year company”.
• The first SPARC powered the Sun-4 workstations,
which made Sun a $1B/year company.
• Terminated in 2017 by Oracle, but now part of Fujitsu.
Photo: Wikipedia
2017 Inductee to the IEEE Chip Hall of Fame
 Main References
• Rob Rutenbar “From Logic to Layout” 2013
• Synopsys University Courseware
• IDESA
• Kahng, et al. “VLSI Physical Design: From Graph Partitioning to Timing
Closure” – Chapter 6

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