VLSI Test Technology and Reliability

(ET4076)

Lecture 7

Memory Testing
Said Hamdioui

Computer Engineering Lab

Delft University of Technology
2009-2010

Faculty: Electrical Engineering, Mathematics and Computer Science (EEMCS)

Section: Computer Engineering Laboratory (CE)
Date:Vermelding onderdeel organisatie
2009-2010
Motivation
• Combinational logic contains no flip flops (no memory)

• Space of possible tests is

• O(2no_pi), no_pi = #primary inputs
• If no_pi = 64 & circuit runs @ 1GHz
How long does a full test take??

full test takes 585 years!

• How can we deal with this problem??

Stuck-at faults are used to model s-a-0

defects and limit test space

VLSI Test Technology and Reliability 2

Motivation
• Sequential logic contains some flip flops (limited memory)
• Space of possible tests is
• O(2no_pi x 2no_ff)
no_pi = #primary inputs
no_ff = #flip flops
• If no_pi = 64, no_ff = 16 @ 1GHz
How long should we test??

test takes about 50 million years!

• How can we deal with this problem??

s-a-0
Stuck-at faults & s-a-0 t=1

time-frame expansion
t=0
VLSI Test Technology and Reliability 3
Motivation
• Memory contains millions of states

• Testing memory is EXTREMELY difficult

• Exhaustive testing takes more than

the age of the UNIVERSE!!

• Special fault models are needed

VLSI Test Technology and Reliability 4

Learning aims

• Describe the problem of memory testing, its

objectives and its importance
• Describe different fault types
• Define the different memory fault models
• Classify the memory test algorithms
• Analyze the fault coverage of memory algorithms
• Develop memory algorithms for given fault models
• Describe the major challenges for memory testing

VLSI Test Technology and Reliability 5

Contents
1. Basics of memory devices
2. Semiconductor memory architecture
3. Functional fault models
4. Memory test development
(to detect the memory faults we defined)
5. Well-known memory tests

VLSI Test Technology and Reliability 6

 VLSI Test Technology and Reliability
(ET4076)

Memory Testing:
1. Basics of memory devices

Faculty: Electrical Engineering, Mathematics and Computer Science (EEMCS)

Section: Computer Engineering Laboratory (CE)
Vermelding onderdeel organisatie
1. Basics of memory devices

Topics:
• History of memory
• History of DRAM
• History of SRAM
• Importance of memory testing
• Test objectives and requirements

VLSI Test Technology and Reliability 8

1. Basics: history of memory
• Memory is important
for data processing
Registers
• More memory needed Bigger,
slower,
for faster CPUs cheaper
• Hierarchy of memory Cache

used:
• Registers: Flip flops Main memory
• Cache: SRAM
• Main: DRAM
Secondary storage
• Secondary: Hard disk

VLSI Test Technology and Reliability 9

1. Basics: history of DRAM

DRAMs are
• Widely used
• Standalone chip
• Most sensitive VLSI
chip
• Increase exponentially
in size
• 32 GB+ in 2020!

VLSI Test Technology and Reliability 10

1. Basics: history of SRAM

SRAMs are
• Widely used
• Embedded with logic
• More sensitive than
logic
• Increase in size
• Dominate chip area
• 94% in 2014!

VLSI Test Technology and Reliability 11

1. Basics: importance of memory testing

 Yield decreases dramatically with increasing in memory size

 Redundancy dramatically improves memory yield
VLSI Test Technology and Reliability 12
1. Basics: test objectives & requirements

• Requirements to detect faults

High fault coverage

High quality Tests required! Low cost

T=10 ns 16 Kbits 32 Kbits 64 Kbits

- Realistic fault models
O(n) [10n] 1.64 ms 3.28 ms 6.56 ms
- Memory-specific O(n2) [10n2] 26.84 s 107.37 s 7.16 min

- Appropriate stresses O(n3) [10n3] 122.2 h 977.3 h ?????

VLSI Test Technology and Reliability 13

1. Basics: test objectives & requirements

• Requirements to increase yield

Large impact on yield

Repair capabilities
BIST required BISR

-The only way to deal with - Improve the yield

embedded memories
- Use redundancy elements
- At speed testing
- On fly repair
- Reduce the cost (ATE)

VLSI Test Technology and Reliability 14

 VLSI Test Technology and Reliability
(ET4076)

Memory Testing:
2. Semiconductor memory architecture

Faculty: Electrical Engineering, Mathematics and Computer Science (EEMCS)

Section: Computer Engineering Laboratory (CE)
Vermelding onderdeel organisatie
2. Semiconductor memory architecture

Topics:
• Memory models
• Behavioral model
• Functional model
• Electrical model
• Layout model (rarely reported)

VLSI Test Technology and Reliability 16

2. Architecture: memory models
If (cond) then read (x) Behavioral
Behavioral fault

Column decoder

Row decoder
Functional Memory Functional fault;
array <1; 0/1/->
Increasing
level Logical
of abstraction Electrical
fault
Electrical

Layout Defect

VLSI Test Technology and Reliability 17

2. Architecture: behavioral model

• General memory Model

• Nothing known about the internal structure
• Data sheet describing functionality provided
Addresses N
Data-in B Data-out
Memory
Controls C

• B: the word width

• Data-in and Data-out are usually combined
=> Bi-directional data lines
VLSI Test Technology and Reliability 18
2. Architecture: functional model

• Functions of
the system
• functional blocks
(with behavior model)
• Memory cell array
consist of n cells
n=RxC
R: Rows (Word lines)
C: Columns (Bit lines)

VLSI Test Technology and Reliability 19

2. Architecture: electrical model (array)

SRAM cell (CMOS) DRAM cell (1T)

Six Transistors per bit Due to leakage, refresh required

Low density High density
Fast access time (e.g., 2ns) Low access time (e.g., 20 ns)
High prices Low prices

VLSI Test Technology and Reliability 20

2. Architecture: layout model (array)

• Physical implementation
of the system
• Diffusion regions, metal
layers, contacts, etc.

• Most detailed description

of any system
• Most complex level to analyze

• Usually confidential

VLSI Test Technology and Reliability 21

2. Architecture: layout model (array)

• Physical implementation
of the system
• Diffusion regions, metal
layers, contacts, etc.

• Most detailed description

of any system
• Most complex level to analyze

• Usually confidential

VLSI Test Technology and Reliability 22

 VLSI Test Technology and Reliability
(ET4076)

Memory Testing:
3. Functional fault models

Faculty: Electrical Engineering, Mathematics and Computer Science (EEMCS)

Section: Computer Engineering Laboratory (CE)
Vermelding onderdeel organisatie
3. Functional fault models

Topics:
• Reduced memory model
• Memory cell array faults
• Fault primitive concept
• Classification
• Definition of fault models
• Neighborhood pattern sensitive faults
• Address decoder faults
• Read/Write logic faults

VLSI Test Technology and Reliability 24

3. Faults: reduced memory model

• Memory faults can be divided into three types/classes

Addresses

Address decoders

Memory cell array

Control
Data-out
Read/write circuits
Data-in

VLSI Test Technology and Reliability 25

3. Faults: array (fault primitives and fault models)
Fault primitive concept (FP)
Control signals

Data
Memory Data outputs
inputs

Notation: <S / F / R > = < 0r0 / 1 / 1 >

• S: sensitizing sequence; e.g. a read 0 operation (0r0)

• F: Fault effect; e.g. cell flips from 0 to 1 (1)
• R: Read value; e.g. an incorrect value 1 is read (1)
• A Fault model (FM) is a non-empty set of FPs
• E.g., Read Destructive Fault (RDF): {<0r0/ 1 / 1 >, <1r1/ 0 / 0 >}

VLSI Test Technology and Reliability 26

3. Faults: array (classification of fault primitives)

Fault Primitive: FP = <S/F/R>

• Depending on #Cells (C) in S
• Single-cell, two-cell, and neighborhood pattern sensitive faults
• Depending on #Operations (O) in S
• Static faults versus dynamic faults

Fault primitives

#C #O

#C=1 #C=2 #C>2 #O=<1 #O>1

Neighborhood
Single cell Coupling pattern sensitive Static Dynamic

VLSI Test Technology and Reliability 27

3. Faults: array (classification of fault primitives)
• Static faults can be classified as:
• Single-cell (1-cell)
• Two-cells (2-cell) (i.e., coupling faults)

FP Ca: aggressor cell

Cv: victim cell
1-cell 2-cell

state a-cell v-cell

Cv Ca Cv Ca Cv Ca Cv

VLSI Test Technology and Reliability 28

3. Faults: array (definition of fault models)
# S F R <S/F/R>
• Single-cell FPs: <S/F/R>
1 0 1 - <0/1/->
S∈{0,1,0w0,1w1,0w1,1w0, 0r0, 1r1}
2 1 0 - <1/0/->
F∈{0,1}
R∈{0,1,-} 3 0w0 1 - <0w0/1/->
Cv 4 1w1 0 - <1w1/0/->
5 0w1 0 - <0w1/0/->
6 1w0 1 - <1w0/1/->
• Compile the 12 FPs into 6 FMs 7 0r0 0 1 <0r0/0/1>
1. State Fault {1,2} (SF)/(SAF)
8 0r0 1 0 <r0r/1/0>
2. Write Disturb Fault {3,4} (WDF)
3. Transition Fault {5,6} (TF) 9 0r0 1 1 <0r0/1/1>
4. Incorrect Read Fault {7, 10} (IRF) 10 1r1 1 0 <1r1/1/0>
5. Read Destructive Fault {9, 12} (RDF)
11 1r1 0 1 <1r1/0/1>
6. Deceptive Read Destructive Fault
{8,11} (DRDF) 12 1r1 0 0 <1r1/0/0>

VLSI Test Technology and Reliability 29

3. Faults: array (definition of fault models)

• Two-cell FPs: state

<S/F/R>= <Sa; Sv/F/R> Ca Cv

Sa∈{0,1}, Sv∈{0,1}
F∈{0,1}
R∈{0,1,-}
# Sa Sv F R <Sa; Sv/F/R>
1 0 0 1 - <0; 0/1/->
Compile the 4 FPs into 1 FM: 2 0 1 0 - <0; 1/0/->
State Coupling Fault (CFst) 3 1 0 1 - <1; 0/1/->
4 1 1 0 - <1; 1/0/->

VLSI Test Technology and Reliability 30

3. Faults: array (definition of fault models)

Two-cell FPs: a-cell accessed

Sa∈{0w0, 1w1, 0w1, 1w0, 0r0, 1r1} Ca Cv
Sv∈{0,1}; F∈{0,1}; R∈{-}
x*= NOT x; x∈{0,1}
r= read; w= write # Sa Sv F R <Sa; Sv/F/R>
1 xwx* 0 1 - <xwx*; 0/1/->
Compile the 12 FPs into 1 FM: 2 xwx* 1 0 - <xwx*; 1/0/->
Disturb Coupling Fault
3 xwx 0 1 - <xwx; 0/1/->
(CFds)
CFds divided into 3 types: 4 xwx 1 0 - <xwx; 1/0/->
• CFdst {1, 2} (transition write) 5 xrx 0 1 - <xrx; 0/1/->
• CFdsn {3, 4} (non-trans. write)
• CFdsr {5,6} (read) 6 xrx 1 0 - <xrx; 1/0/->

VLSI Test Technology and Reliability 31

3. Faults: array (definition of fault models)
Two-cell FPs: 1PF2v (v-cell accessed)
Sa∈{0,1} Ca Cv
Sv∈{0w0,1w1,0w1,1w0, 0r0, 1r1}
F∈{0,1} # Sa Sv F R <S/F/R>
R∈{0,1,-} 1 x 0w0 1 - <x; 0w0/1/->
x∈{0,1} 2 x 1w1 0 - <x; 1w1/0/->
3 x 0w1 0 - <x; 0w1/0/->
4 x 1w0 1 - <x; 1w0/1/->
Compile the 24 FPs into 5 FMs:
5 x 0r0 0 1 <x; 0r0/0/1>
CF= Coupling Fault
1. Write Disturb CF {1,2} (CFwd) 6 x 0r0 1 0 <x; r0r/1/0>
2. Transition CF {3,4} (CFtr) 7 x 0r0 1 1 <x; 0r0/1/1>
3. Incorrect Read CF {5,8 } (CFir) 8 x 1r1 1 0 <x; 1r1/1/0>
4. Read Destructive CF {7,10}(CFrd) 9 x 1r1 0 1 <x; 1r1/0/1>
5. Deceptive CFrd {6,9} (CFdr)
10 x 1r1 0 0 <x; 1r1/0/0>
VLSI Test Technology and Reliability 32
3. Faults: array (definition of fault models)

• Pattern sensitive faults, PSF, (k-coupling faults)

• Conditional single-cell fault
• k-1 cell in a certain state
• Conditional two-cell fault b
• k-2 cells in a certain state
• Neighborhood PSF (NPSF)
• PSF very complicated
• Restrictions: k cells are neighbors (5 or 9) b Base cell
• Types of NPSFs
• Passive NPSF: conditional Transition Fault (TF) 5 neighbors
• Static NPSF: conditional State Coupling Fault (CFst)
• Disturb NPSF: conditional Disturb coupling Fault (CFds) 9 neighbors

K-coupling

VLSI Test Technology and Reliability 33

3. Faults: address decoder (functional faults)
• 1-1 correspondence: Address <----> Cell
• Possible faults:
1. An address does not access a certain cell
2. A cell is not accessed with a certain address
3. With a certain address, multiple cells are accessed
4. A certain cell can be accessed with multiple addresses

Ax Cx Cx Ax Cx
Ay Cy Ay
Fault 1 Fault 2 Fault 3 Fault 4

• Fault combinations

Ax Cx Ax Cx Ax Cx Ax Cx

Ay Cy Ay Cy Ay Cy
Fault A (1+2) Fault B (1+3) Fault C (2+4) Fault D (3+4)

VLSI Test Technology and Reliability 34

3. Faults: Read/Write logic (functional faults)
• Consist of faults in
• Sense amplifiers, Write drivers
• Pre-charge circuits, Multiplexes
• Etc

• They have never been analyzed

• Research map them into memory cell
array faults
• Assuming a defect to be
• Complete open
• A short / bridges with very low resistance
value

• Good coverage realized in the past

(old technologies >0.1um)
VLSI Test Technology and Reliability 35
3. Faults: address decoder (delay/dynamic faults)
• Delay faults
• Word lines and bit lines have an increasing load
and high capacitance
• Open defects are becoming dominant in new
technologies
⇒ Delay faults are becoming important

Volt

Time

VLSI Test Technology and Reliability 36

3. Faults: Read/Write logic (delay/dynamic faults)

• Consist of e.g.,:
• Slow Sense Amplifier Fault (SSAF)
• Slow Write Driver Fault (SWDF)
• Slow PRecharge circuit Fault (SPRF)
⇒Speed related faults

• Cannot be mapped nto memory cell array faults

• Require specific operation sequences!
• Requires specific addressing direction!

VLSI Test Technology and Reliability 37

 VLSI Test Technology and Reliability
(ET4076)

Memory Testing:
4. Memory test development

Faculty: Electrical Engineering, Mathematics and Computer Science (EEMCS)

Section: Computer Engineering Laboratory (CE)
Vermelding onderdeel organisatie
Contents …

Topics:
1. Test notation
How we can describe a memory test

2. Detection conditions
Fault model  test requirements

VLSI Test Technology and Reliability 39

1. Test notation… needed info

How can we test a memory??

• We need:
• Operations (reads and writes)
• Data-in (what to write)
• Data-out (what to read)
• Addresses (which cells)

Addresses N
Data-in B Data-out
Memory
Controls C

VLSI Test Technology and Reliability 40

1. Test notation… operations and data
• Operations and data
• wx = write data x
• rx = read data (expected value x)
• Example of a sequence
• (w1, r1, w0, r0)
• Write and read a cell with 1
• Then write and read a 0

Cell

w1 r1 w0 r0 time

VLSI Test Technology and Reliability 41

1. Test notation… addresses
• Addressing:
• Up addressing: ⇑ (i.e., from i=0 to N)
• Down addressing: ⇓ (i.e., from i=N to 0)
• Irrelevant: 
• Two dimensional arrays
x direction
• x-addressing: ⇑x
• y-addressing: ⇑y
y direction c c c c c
c c c c c
• Example:
c c c c c
• ⇑ (w1, r1, w0, r0)
c c c c c
• Perform sequence going up!
• MARCH ELEMENT c c c c c

Memory (c = cell)

VLSI Test Technology and Reliability 42

1. Test notation… march tests

• A march test = sequence of march elements

(w0); ⇑(r0, w1); ⇓(r1)}

• Example: {

• Up or down, write 0 in all cells

c c c c c
• Going up, read 0, then write 1
c c c c c
• Going down, read 1 c c c c c
c c c c c
c c c c c

Memory (c = cell)

VLSI Test Technology and Reliability 43

2. Detection conditions… what is it?

• A detection condition = incomplete march test

• Detects a specific set of faults!

• Example:
• Transition Fault 1 (TF1) = <0w1/0/->
• To detect, start with 0, write 1, then read it!
State
• Detection condition 0

• (…0, w1, …, r1, …)

Write 1

VLSI Test Technology and Reliability 44

2. Detection conditions… single-cell faults
• Single-cell FPs: <S/F/R> # S F R <S/F/R>
S∈{0,1,0w0,1w1,0w1,1w0, 0r0, 1r1} 1 0 1 - <0/1/->
F∈{0,1} 2 1 0 - <1/0/->
R∈{0,1,-}
3 0w0 1 - <0w0/1/->
Cv 4 1w1 0 - <1w1/0/->
5 0w1 0 - <0w1/0/->
• Compile the 12 FPs into 6 FMs 6 1w0 1 - <1w0/1/->
1. State Fault {1,2} (SF)/(SAF)
7 0r0 0 1 <0r0/0/1>
2. Write Disturb Fault {3,4} (WDF)
3. Transition Fault {5,6} (TF) 8 0r0 1 0 <0r0/1/0>
4. Incorrect Read Fault {7, 10} (IRF) 9 0r0 1 1 <0r0/1/1>
5. Read Destructive Fault {9, 12} (RDF)
6. Deceptive Read Destructive Fault {8,11} 10 1r1 1 0 <1r1/1/0>
(DRDF) 11 1r1 0 1 <1r1/0/1>
12 1r1 0 0 <1r1/0/0>

VLSI Test Technology and Reliability 45

2. Detection conditions… single-cell faults
• State Faults (SF) = {<0/1/->, <1/0/->}
• Incorrect Read Fault (IRF) = {<0r0/0/1>, <1r1/1/0>}
• Read Destructive Fault (RDF)= {<0r0/1/1>, <1r1/0/0>}
Condition: Read 0 and read 1 from each cell

• Deceptive RDF (DRDF)= {<0r0/1/0>, <1r1/0/1>}

Apply a read to sensitize the fault, followed with a read to detect it

• Transition Fault (TF)= {<0w1/0/->, <1w0/1/->}

Apply a transition write followed with a read operation

• Write Destructive Fault (WDF) = {<0w0/1/->, <1w1/0/->}

Apply a non-transition write followed with a read

VLSI Test Technology and Reliability 46

2. Detection conditions… single-cell faults
⇑(w0); ⇑(r0); ⇑(w1); ⇑(r1)}
Question: consider the test Scan= {⇑

Which faults (fault models) are not detected at all?

a. SF b. IRF c. RDF
d. DRDF e. TF f. WDF

Which faults are partially detected?

a. SF b. IRF c. RDF
d. DRDF e. TF f. WDF

How many single-cell faults does Scan detect?

a. 12/12 b. 11/12 c. 10/12
d. 9/12 e. 8/12 f. 7/12

VLSI Test Technology and Reliability 47

2. Detection conditions… two-cell faults

• Two-cell FPs: state

<S/F/R>= <Sa; Sv/F/R>

Sa∈{0,1}, Sv∈{0,1} Ca Cv
F∈{0,1}
R∈{0,1,-}

# Sa Sv F R <Sa; Sv/F/R>
Compile the 4 FPs into 1 FM: 1 0 0 1 - <0; 0/1/->
State Coupling Fault (CFst)
2 0 1 0 - <0; 1/0/->
3 1 0 1 - <1; 0/1/->
4 1 1 0 - <1; 1/0/->

VLSI Test Technology and Reliability 48

2. Detection conditions… two-cell faults
1. State Coupling Faults CFst= {<0; 0/1/->, <0; 1/0/->, <1; 0/1/->, <1; 1/0/->}
• Sensitization: the four states of any two cells are reached
• Detection: a read operation is applied to each cell within each state
• Example:{⇑(w0); ⇑(r0); ⇑(w1); ⇑(r1)}; consider cells Ci and Cj where i<j
M0 M1 M2 M3

# Mi State Oper. State Effect

1 M0 - - w0 to Ci 0- -
2 M0 0 - w0 to Cj 00 <0; 0/1/->i,j and <0; 0/1/->j,i sensitized
3 M1 00 r0 to Ci 00 <0; 0/1/->j,i detected
4 M1 00 r0 to Cj 00 <0; 0/1/->i,j detected
5 M2 00 w1 to Ci 10 <0; 1/0/->j,i and <1; 0/1/->i,j sensitized
6 M2 10 w1 to Cj 11 <1; 1/0/->i,j and <1; 1/0/->j,i sensitized
7 M3 11 r1 to Ci 11 <1; 1/0/->j,i detected
8 M3 11 r1 to Cj 11 <1; 1/0/->i,j detected

Fault Coverage FC=4/8 sub-Fault Primitives

VLSI Test Technology and Reliability 49

2. Detection conditions… two-cell faults
Two-cell FPs: 1PF2v (v-cell accessed)
Sa∈{0,1}
Ca Cv
Sv∈{0w0,1w1,0w1,1w0, 0r0, 1r1}
F∈{0,1}
R∈{0,1,-} # Sa Sv F R <S/F/R>
x∈{0,1} 1 x 0w0 1 - <x; 0w0/1/->
2 x 1w1 0 - <x; 1w1/0/->
Compile the 24 FPs into 5 FMs: 3 x 0w1 0 - <x; 0w1/0/->
CF= Coupling Fault 4 x 1w0 1 - <x; 1w0/1/->
1. Write Disturb CF {1,2} (CFwd) 5 x 0r0 0 1 <x; 0r0/0/1>
2. Transition CF {3,4} (CFtr)
3. Incorrect Read CF {5,8 } (CFir) 6 x 0r0 1 0 <x; r0r/1/0>
4. Read Destructive CF {7,10}(CFrd) 7 x 0r0 1 1 <x; 0r0/1/1>
5. Deceptive CFrd {6,9} (CFdr)
8 x 1r1 1 0 <x; 1r1/1/0>
9 x 1r1 0 1 <x; 1r1/0/1>
10 x 1r1 0 0 <x; 1r1/0/0>
VLSI Test Technology and Reliability 50
2. Detection conditions… two-cell faults
2. Incorrect Read Coupling Faults
• CFir= {<0; 0r0/0/1>, <0; 1r1/1/0>, <1; 0r0/0/1>, <1; 1r1/1/0>}
• Sensitization/ Detection: the four states of any two cells are reached, and a read
operation is applied to each cell within each state.
• Example: {⇑(w0); ⇑(r0); ⇑(w1); ⇑(r1)} ; consider cells Ci and Cj where i<j

# Mi State Oper. State Effect

1 M0 -- w0 to Ci 0- -
2 M0 0- w0 to Cj 00 -
3 M1 00 r0 to Ci 00 <0; 0r0/0/1>j,i sensitized & detected
4 M1 00 r0 to Cj 00 <0; 0r0/0/1>i,j sensitized & detected
5 M2 00 w1 to Ci 10 -
6 M2 10 w1 to Cj 11 -
7 M3 11 r1 to Ci 11 <1; 1r1/1/0>j,i sensitized & detected
8 M3 11 r1 to Cj 11 <1; 1r1/1/0>i,j sensitized &detected

Result: FC=4/8 sub-Fault Primitives

VLSI Test Technology and Reliability 51

 2. Detection conditions… two-cell faults
3. Read Destructive Coupling Faults
• CFrd= {<0; 0r0/1/1>, <0; 1r1/0/0>, <1; 0r0/1/1>, <1; 1r1/0/0>}
• Sensitization/ Detection: the four states of any two cells are reached, and a read
operation is applied to each cell within each state.
• Example: {⇑(w0); ⇑(r0); ⇑(w1); ⇑(r1)} ; consider cells Ci and Cj where i<j

# Mi State Oper. State Effect

1 M0 -- w0 to Ci 0- -
2 M0 0- w0 to Cj 00 -
3 M1 00 r0 to Ci 00 <0; 0r0/0/1>j,i sensitized & detected
4 M1 00 r0 to Cj 00 <0; 0r0/0/1>i,j sensitized & detected
5 M2 00 w1 to Ci 10 -
6 M2 10 w1 to Cj 11 -
7 M3 11 r1 to Ci 11 <1; 1r1/1/0>j,i sensitized & detected
8 M3 11 r1 to Cj 11 <1; 1r1/1/0>i,j sensitized &detected

Result: FC=4/8 sub-Fault Primitives

VLSI Test Technology and Reliability 52

2. Detection conditions… two-cell faults
4. Deceptive Read Destructive Coupling Faults
• CFdr= {<0; 0r0/1/0>, <0; 1r1/0/1>, <1; 0r0/1/0>, <1; 1r1/0/1>}
• Sensitization: the four states of any two cells are reached, and a read
operation is applied to each cell within each state.
• Detection: another read is applied to each cell within each state
• Example: {⇑(w0); ⇑(r0); ⇑(w1); ⇑(r1)} ; consider cells Ci and Cj where i<j

# Mi State Oper. State Effect

1 M0 -- w0 to Ci 0- -
2 M0 0- w0 to Cj 00 -
3 M1 00 r0 to Ci 00 <0; 0r0/1/0>j,i sensitized
4 M1 00 r0 to Cj 00 <0; 0r0/1/0>i,j sensitized
5 M2 00 w1 to Ci 10 -
6 M2 10 w1 to Cj 11 -
7 M3 11 r1 to Ci 11 <1; 1r1/0/1>j,i sensitized
8 M3 11 r1 to Cj 11 <1; 1r1/0/1>i,j sensitized

Result: FC=0/8 sub-Fault Primitives

VLSI Test Technology and Reliability 53

2. Detection conditions… AFs
• Address decoder faults:

Ax Cx Ax Cx Ax Cx Ax Cx

Ay Cy Ay Cy Ay Cy
Fault A (1+2) Fault B (1+3) Fault C (2+4) Fault D (3+4)

Detection condition
A test detects AFs iff it contains the following two march elements;
x=0 or x=1:
• (rx, …, wx*, [rx*]h)
⇑
• ⇓ (rx*, …, wx , [rx]h)
h for hammer; h≥ 1
Question: what is the optimal test detecting all AFs?

•⇑ (rx, …, wx*, [rx*]h) 1. {⇑(r1,w1,r1); ⇓(r1,w0,r0) }?

•⇓ (rx*, …, wx , [rx]h) 2. {⇑(r0,w1,r1); ⇓(r1,w0,r0) }?

3. {⇑(w0); ⇑(r0,w1,r1); ⇓(r1,w0,r0) }?
VLSI Test Technology and Reliability 54
 VLSI Test Technology and Reliability
(ET4076)

Memory Testing:
5. Well-known memory tests

Faculty: Electrical Engineering, Mathematics and Computer Science (EEMCS)

Section: Computer Engineering Laboratory (CE)
Vermelding onderdeel organisatie
5. Memory tests… Ad-hoc tests
• Most know Ad-hoc test:
• Scan= Zero-One Test
• Checkerboard
• GalPat
• Walking 1/0
• Typically until 1980’s
• Absence of formal fault models
• Not acceptable due to
• Low fault coverage (Scan/ Checkerboard)
• High cost (GalPat/ Walking 1/0)

VLSI Test Technology and Reliability 56

5. Memory tests… Ad-hoc tests
Scan= Zero-One Test
1. Write 0 in all cells (starting at cell 0)
2. Read all cells (starting at cell 0)
3. Write 1 in all cells (starting at cell 0)
4. Read all cells (starting at cell 0)

• In short notation: {⇑(w0); ⇑(r0); ⇑(w1); ⇑(r1)}

• Test length: 4n => O(n): linear time complexity

• Low Fault coverage:

• 7/12 single-cell faults (1PF1s)
• 18/72 two-cell faults (1PF2s)
• No address decoder faults (AFs)

VLSI Test Technology and Reliability 57

5. Memory tests… Ad-hoc tests
• Checkerboard
1. Divide the memory cell into two groups, say cells-1 and cells-2
2. Write 1 in cells-1 and 0 in cells-2
3. Read all cells
3. Write 0 in all cells-1 and 1 in cells-2.
4. Read all cells 1 0 1 0

0 1 0 1
• Test length: 4n => O(n)
1 0 1 0

• Short Notation: {⇑(w1i , w0i+1); ⇑(r1i, r0i+1); 0 1 0 1

⇑(w0i , w1i+1); ⇑(r0i, r1i+1)}
Memory array
where 0≤i<n-2

• Low fault coverage (similar to Scan)

VLSI Test Technology and Reliability 58

5. Memory tests… Ad-hoc tests
Galpat, Walking 1/0 Read-Action Galpat
for d=0 to d=1 for cell=0 to n-1 (base-cell excluded)
{ for i=0 to n-1 { if A[cell]≠ d
A[i]=d; then output (“ERROR”)
for base-cell=0 to n-1 if A[base-cell]≠ d*
{ A[base-cell]=d*; then output (“ERROR”)
Perform Read-Action; }
A[base-cell]=d;
} Read-Action Walking 1/0
}
for cell=0 to n-1 (base-cell excluded)
{ if A[cell]≠ d
then output (“ERROR”)

Time complexity: O(n2) }
Low fault coverage if A[base-cell]≠ d*
then output (“ERROR”)
Galpat: 10/12 1PFs, 44/72 1PF2s, no AFs

Walking 1/0: 8/12 1PFs, 40/72 1PF2s, no AFs

VLSI Test Technology and Reliability 59

5. Memory tests… Ad-hoc vs march
• Ad-hoc tests:
• Low fault coverage, and/or
• High time complexity
• Industrially not acceptable for serious test purposes
• Based on speculations not on fault models

• March tests:
+ Based on fault models
+ Linear time complexity
+ Acceptable fault coverage
• With newer technologies
• New defects
• New fault models required
• New advanced tests

VLSI Test Technology and Reliability 60

5. Memory tests… march tests

List of some well known march tests

• MATS+ [Nair, 79]: { (w0); ⇑(r0,w1); ⇓(r1,w0)}

(w0); ⇑(r0,w1); ⇓(r1,w0,r0)}

• MATS++ [Breuer, 76}: {

• PMOVI [de Jonge, 76]

{⇓(w0); ⇑(r0,w1,r1); ⇑(r1,w0,r0); ⇓(r0,w1,r1); ⇓(r1,w0,r0)}

• March B [Suk, 81]:

(w0); ⇑(r0,w1,r1,w0,r0,w1); ⇑(r1,w0,w1); ⇓(r1,w0,w1,w0);
{
⇓(r0,w1,w0)}

• March C- [van de Goor, 91]:

(w0); ⇑(r0,w1); ⇑(r1,w0); ⇓(r0,w1); ⇓(r1,w0); (r0)}
{

VLSI Test Technology and Reliability 61

5. Memory tests… march tests
• Advanced tests: fault primitive-based
• High fault coverage
• Cover realistic faults
• Linear with the size of the memory
• An example of advanced tests based on fault primitives is as follows
• March MSS [Hamdioui 02, Harutunvan, 05] (18n): test for all static simple faults

March MSS={
(w0); M0
⇑(r0,r0,w1,w1); M1
⇑(r1,r1,w0,w0); M2
⇓(r0,r0,w1,w1); M3
⇓(r1,r1,w0,w0); M4
(r0)} M5

VLSI Test Technology and Reliability 62

5. Memory tests… march tests
Fault Model MATS+ March C- PMOVI March SR March G Ham. Galpat March MSS
(5n) (10n) (13n) (14n) (23n) (49n) O(n2) (22n)

SAF 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2

TF 1/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2

WDF 0/2 0/2 0/2 0/2 0/2 2/2 0/2 2/2

IRF/ RDF 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2

DRDF 0/2 0/2 2/2 2/2 0/2 2/2 0/2 2/2

CFst 4/8 8/8 8/8 8/8 6/8 8/8 8/8 8/8

CFds [rx] 3/8 8/8 8/8 8/8 7/8 8/8 8/8 8/8

CFds [xwx*] 3/8 8/8 7/8 8/8 8/8 7/8 4/8 8/8

CFds [xwx] 0/8 0/8 0/8 0/8 0/8 7/8 0/8 8/8

CFtr 2/8 8/8 8/8 8/8 4/8 8/8 4/8 8/8

CFwd 0/8 0/8 0/8 0/8 0/8 8/8 0/8 8/8

CFrd/ CFir 4/8 8/8 8/8 8/8 4/8 8/8 8/8 8/8

CFdr 0/8 0/8 6/8 4/8 0/8 6/8 0/8 8/8

Total 29/84 56/84 63/84 62/84 57/84 80/84 54/84 84/84

VLSI Test Technology and Reliability 63

Trends in memory testing

• Dynamic faults/ address decoder delay faults

• Intra-word faults
• Faults in the periphery circuits (speed related faults)
• Built-in-Self-Testing (BIST) and repair (BISR)
• On-line testing/Built-in-self-correction (BISC)/soft
faults/errors
• Reliability in memories
• Testing ROMs (FLASH memories)

VLSI Test Technology and Reliability 64

Summary
• Memory testing is very important
• Large share of SoC area, large impact on quality, yield and reliability
• Memory Faults classified into three types
• Memory cell array faults
• Single cell versus coupling faults
• Address decoder faults
• Peripheral circuits faults
• Static faults versus dynamic faults
• Three classes of memory test algorithms
• Ad-hoc tests
• March tests
• Fault-primitive based tests
• Major challenges
• Speed related faults
• Repair, diagnosis, …

VLSI Test Technology and Reliability 65