2021 International Conference on Emerging Smart Computing and Informatics (ESCI)

AISSMS Institute of Information Technology, Pune, India. Mar 5-7, 2021

Design and Verification of 16 bit RISC Processor

Using Vedic Mathematics
Ankita Yadav Varsha Bendre
2021 International Conference on Emerging Smart Computing and Informatics (ESCI) | 978-1-7281-8519-4/20/$31.00 ©2021 IEEE | DOI: 10.1109/ESCI50559.2021.9396965

Dept. Electronics & Telecommunication Dept. Electronics & Telecommunication

Pimpri Chinchwad College of Engineering Pimpri Chinchwad College of Engineering
Pune, India Pune, India
[email protected] [email protected]

Abstract— Reduced Instruction Set Computer (RISC) is a Vedic Mathematics is derived from Ancient Indian
design which presents better performances, higher speed of Scriptures, which gives mathematical outcomes and basic
operation and favors the smaller and simpler set of understandable structures. The word Vedic is known from the
instructions. A 16 bit RISC processor designed in this paper word Veda which means the storage facility of all the
is capable of executing more number of instructions with information. Vedic Mathematics is mainly based on 16 Sutras
simple design, using the Verilog Hardware Description which provides the manipulations in arithmetic, logical math,
Language (HDL) and the design is simulated in the Xilinx ISE geometry, etc.
14.7 design suite. The main achievement in this work is that
the multiplier unit in Arithmetic and Logic Unit (ALU) and In this paper section 1 describes related work literature
Multiplier and Accumulator (MAC) is implemented using survey of the RISC Processor of the system, section 2 describe
Vedic Sutras. The main principle used in Vedic mathematics the implementation of processor design methodology, section
is to reduce the typical calculation of conventional 3 describe results observed in the system, section 4 shows the
mathematics to very simple one and hence reduce the overall verification results of the proposed system.
computational complexity. In addition to these blocks,
designed RISC Processor consists of other blocks like Control Vedic Mathematics has another method of estimations and
unit and data path, Register Bank, Program Counter and has arrangement of mathematics which depends on 16 Sutras.
Memory. The proposed RISC processor is very simple and Utilizing these procedures in the processing algorithms will
capable of executing 14 instructions. The achievement in this improve the execution time, area, power, and complexity and
work is that 44% savings in power in case of MAC and that so forth . Vedic System proposes a one of a kind and
of 12% in case of ALU is achieved compared to conventional incredibly compelling methodology covering a wide range -
ALU and MAC respectively. Also the delay is reduced by beginning with essential multiplication to closing a generally
45% in case of MAC and that of 35% in case of ALU in propelled theme, the arrangement of non-direct incomplete
comparison with conventional ALU and MAC differential conditions. In any case, the Vedic structure isn't
correspondingly. These Vedic MAC and ALU are then just an accumulation of quick techniques; it is a framework, a
integrated with other blocks in processor and 16-bit Vedic brought together methodology S. Lad and V. S. Bendre [1]
processor is developed. This reduces the delay by 34% and
explained the comparison of various types of multipliers and
saves around 88% power compared to conventional
processor. Hence the improvement in speed of operation,
proved that how Vedic multipliers are efficient than tree and
reduction in power utilization and less area utilization are the array multipliers. In [2],Vishwas V. Balpande, Abhishek B.
key features of designed RISC processor. Pande, Meeta J.Walke, Bhavna D. Choudhari, Kiran R.
Bagade, described a basic blocks of RISC Processor with
Keywords— Reduced Instruction Set Computer; Von- RTL. SeungPyo Jung, JingzheXu, Donghoon Lee, Ju Sung
Neumann architecture; Verilog HDl, Vedic Mathematics, Park, Kang-jookim, Koon-shik Cho [3], Presented a design
Urdhva-Tiryagbhyam Sutra. uses Harvard architecture and 5-stage pipeline structure. The
16-bit RISC Processor is designed and verification of the
I. INTRODUCTION processor is done in 3-stages.In [4], Abhyarthana Bisoyil,
The Reduced Instruction Set Computer (RISC) is a MituBaratl, Manoja Kumar presented a comparison of 32- bit
microprocessor CPU design in a computer with highly Vedic multiplier with a conventional binary multiplier.
optimized instructions, small and specialized instruction set The design of multipliers i.e. binary multiplier is done to
than that often found in other architecture like Complex find the product of two n-bit binary numbers and then
Instruction Set Computer (CISC). The main difference implement it on a Nexys 3, Spartan 6 FPGA board. After
between the features of CISC and RISC architecture is implementation the 32 bit multiplier is compared with the
RISC processor is optimized with large number of registers conventional multiplier based on their summary report. In [6],
and an instruction pipelining, also allows low number of Mr. Nishant G. Deshpande, Prof. Rashmi Mahajan presented
clock cycles per instruction. Also, the main feature in RISC an Ancient Indian Vedic Mathematics based Multiplier Design
is LOAD/STORE architecture. In CISC the controller for High Speed and Low Power Processor. The multipliers,
design is complex and also performance wise it was not with low power requirement and maximum speed, give
upto the expectation. That’s the reason why any typical information of “Urdhva-Tiryagbhyam” algorithm of ancient
RISC architecture has very few instructions, where Indian Vedic mathematics, which has utilized for
processor asked data from memory probably not other than multiplication to improve speed, area. In [8], Pravin S. Mane,
Load and Store. Indra Gupta, M.K. Vasatha presented Implementation of RISC
Processor on FPGA. In this paper the simulation of five-stage

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pipelined is designed of 16-bit Microprocessor without operands in memory then assigning a command to a processor
Interlocked Pipeline Stages (MIPS) which is RISC. to execute the instruction.
II. PROPOSED METHODOLOGY This is done with the help of control unit which generates
the timing signals that controls the various processing
A. RISC Processor System: elements which involves in execution of the instruction.
This section gives the outline for the RISC Processor
4) Program Counter (PC):
architecture and working of the system which utilizes the
Program Counter points to the next instruction to be
synchronous execution of the instructions and hence allows
executed. In the complete instruction cycle, the instruction is
the processor to work effectively. As per the requirements
loaded into the instruction register after the processor fetches
of the organization for the power or speed, the architecture/
it from the memory location which is pointed by the program
design are chosen according to the various parameters for
counter.
the application. The function of the processor is to execute
each and every instruction set efficiently as per the machine 5) Control Unit:
language. Control Unit is an essential part of any kind of computer or
systems because this circuits generates the timing and control
signals for the operations which is performed by the CPU.
Here, the communication is between the ALU and the main
memory as it controls the transmission of signals between the
processor, memory and various buses.
6) Memory Address Register (MAR):
The MAR is also called as address buffer; the address in
the program counter is applied to memory so after the
increment in PC to the next address the current instruction is
stored in the Memory location. The MAR is completely
loaded with Binary words which point the location of the word
in RAM. This location stores the instruction in it.
7) Multiplexer (MUX):
The multiplexer block works as input selector. It can
Fig. 1. Block Diagram of Processor
control wires which act as select lines. It is a circuit which
takes multiple inputs and gives the single output.
Fig.1. shows the block diagram of the processor. The
blocks of the proposed system are as follows: 8) Instruction Set Architecture:
Instruction Set Architecture (ISA) provides the
1) Arithmetic Logic Unit (ALU):
information to write the program in machine language. It also
ALU is the combinational circuit which means
allows translating a high level program language to machine
Arithmetic and Logical Unit. This unit is designed to
language.
perform various numbers using various instruction sets. In
Processor, ALU inputs consist of instruction (machine
word) which is operation code (opcode) and some
operands. So the opcode tells the ALU which and what
operation is to be performed then these operands are used in
the operation.
Fig. 2. Instruction Set Format
2) Register Bank:
There is a small set of data holding place that is known In above figure it is a 16 bit instruction frame where
as Register bank. The ALU stores the result of operation in starting 12 bits (0-11 bits) indicate an address. Next 3 bits
accumulator which later on is placed in a storage register from (12-14 bits) specify operation code (opcode). Left one bit
and it checks the bits and indicates whether the operation i.e. (15th bit) is an addressing mode I bit. The following table
was performed successfully. If not successfully executed shows instructions and corresponding codes considered while
then some type of status will be shown i.e. even known as designing the instruction set in this work.
Z-Flag or status register. Its function is to execute programs
and operate efficiently for the data stored in memory. TABLE I. INSTRUCTION SET
Instruction
3) Instruction Register (IR): Instruction
Code
Operation
A processor has a set of instructions which is nothing Addition 0000 Out=a+b
but a command to perform a task in a computer. The control Subtraction 0001 Out=a-b
unit holds the instruction to be executed. In CPU, the Multiplication 0010 Out=a*b
registers such as address register, data register and an Division 0011 Out= a/b
instruction register is present. The performance of the CPU NOT 0100 NOT R0, R0 = !R0
is to fetch , decode and execute the operations on memory Read 0101 RD FECH_ADDR
R2 xxx R2 = M[xxx]
according to the registers. The task of IR includes the Write 0110 WR R3 xxx, -
decoding the op-code, determining the instruction, M[xxx] = R3
determining which operands are in memory, retrieving the Branch 0111 BR loop1
Branch-Zero 1000 BRZ Exit1

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 (BRZ) Following table shows the performance parameters
IOSTS 1011 IOSTS R1; R1 = obtained from the simulation of MAC
IO_STU
Shift Left 1100 R0, R0 = R0<<1 TABLE II. VALUES OBTAINED FOR MAC USING URDHVA-
Shift Right 1101 R0, R0 = R0>>1 TIRYAGBHYAM SUTRA
ADRI 1110 ADRI BYMEM;
Addr = *p(raw_addr) Parameters Urdhva Tiryagbhyam
*Vedic Mult 1111 rawnum(*); -> value This Work (MAC) Existing MAC[9]
Sutra may change by Number of Slices
main() 363 1243
LUTs
Number of IOB 64 66
B. Vedic Mathematics Sutra: Delays(nS) 21.55 38.82
Power (mW) 48.5 86.91
All the signal processing applications require
multiplication as a basic operation. As study reflects
multipliers require more silicon area, also they consume B. ALU using UrdhvaTriyagbhyam:
more power due to switching activity so they create longest The 16-Bit ALU schematic consist of circuitry blocks consisting
path via adders and carry. This limits the maximum speed of reversible Full Adder designed using gates.
in processor. So to overcome the limitation of critical path
The design of ALU requires four 8-Bit Multiplier and 2 adders.
and power in processors, Vedic Multipliers are designed Here the simulation is based on UrdhvaTriyagbhyam Sutra which
using various sutra for different multiply algorithm. Hence, simulates the basic operations of Arithmetic Logic Unit. This
Vedic Multiplier has proved to be more efficient using technique uses less number of computational steps for designing and
different Vedic sutra which reduces both critical path and obtaining the results of Multiplier.
dynamic power. The sutra used in design of multiplication
for the proposed system is “UrdhvaTriyakbhyam” sutra.
The UrdhvaTriyakbhyam sutra is applied to multiplication
which follows the vertically and crosswise pattern.
Therefore, the detailed study of designing the multiplier and
comparison using various sutra is performed using Vedic
mathematics algorithm.[1]
III. SIMULATION RESULTS
A. MAC using UrdhvaTriyagbhyam Sutra:
The following simulation result of 16-Bit Multiplier is
the output of Vedic multiplier using UrdhvaTriyagbhyam
sutra. It is the execution of MAC operations performed with Fig. 5. RTL Schematic of 16-Bit ALU
two inputs as a=252 and b=846 giving an output value as
c=213192.
As the number of bits increases, the delay and area of
gate increases very slowly as compared to other multipliers.
This makes the processor speed, power and time efficient.

Fig. 6. ALU using Urdhva-Tiryagbhyam Sutra for Multiplication

TABLE III. VALUES OBTAINED FOR ALU USING URDHVA-

TIRYAGBHYAM SUTRA
Parameters Vedic ALU Conventional
ALU
Number of
502 1086
Slices LUTs
Fig. 3. RTL Schematic of MAC using UrdhvaTriyakbhyam Sutra
Number of IOBs 64 68
Delays (ns) 4.305 6.665
Power (mW) 29.41 33.2

C. Simulation Results of Various Arithmetic Operations:

The below simulation shown is the Arithmetic Operation
on 16-bit of data which consist of operations like Addition,
Subtraction, Multiplication and Division. These simulations
are carried out using UrdhvaTriyagbhyam sutra for multiplier
operation. To perform these basic Arithmetic operation the
Fig. 4. Simulation for 16-Bit Multiplier input select lines given through multiplexer is of 4-bit.

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 the instruction execution which controls the operations. The
below simulation figure is the control signal for the instruction
of 0011 which performs the division operation and the data is
performing on left shift operation.

Fig. 7. Addition Operation

Fig. 12. Simulation of Control Signals

F. Processing Unit:
As the processor design consist of basic blocks for the
Fig. 8. Subtraction Operation implementation of hardware on processor. So the complete
processing unit consist of Storage Register File, Instruction
Register, Control Signal and various multiplexer select lines.
The processor has the limitation in speed, power, delay etc. so
to overcome the limitations the integration of vedic multiplier
with the processor design is implemented.

Fig. 9. Multiplication Operation

Fig. 13. Simulation of Vedic Multiplier in Processing Unit

Fig. 10. Division Operation
The Fig.13.shows the simulation of 16-bit processing unit,
D. Instruction Set: which is the integration of Vedic multiplier block in ALU for
The simulation is the execution of instruction which performing multiplier operation and all other normal
the complete cycle of instruction set of 16-bit which shows operations similar to conventional ALU. The multiplication is
the data getting Read i.e. instruction code 0101 from the performed using UrdhvaTriyagbhyam Sutra. Hence, the main
input and Left Shift operation i.e. Instruction code 0011 is task of the integration of Vedic ALU with proposed system of
performed. processor design is achieved. This RISC processor design [9]
is compared with the implemented system of Vedic multiplier
through synthesis report generated.
IV. VERIFICATION RESULTS
Verification is the process used to demonstrate the
functional correctness of a design. It is the act of ensuring that
the logic design confirms to the given specification.
Verification depends on the test bench functionality. The
purpose of the test bench is to determine the correctness of the
design under test (DUT). The 16-bit processing module is
integrated with Vedic multiplier designed and the output is
verified for the given instruction set. The verification results
Fig. 11. Simulation of Instruction Set Execution are presented for complete processing unit with integration of
ALU.
E. Control Unit:
It controls the data bits and interrupts the instructions
and dataflow inside the processor. The simulation shows

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 Fig. 17. Verification of 16 bit Vedic Multiplier.

TABLE V. COMPARISON OF VEDIC PROCESSOR AND CONVENTIONAL

PROCESSOR
Parameters Existing
Vedic Processor
Processor
Fig. 14. Verification of ALU with Processing Units.
No. of LUTs
1,293 2,123
The above figure shows the successful compilation of Required
ALU with processing unit. The below verification result
shows the simulation of 16 bit ALU operations. This Delay(nS) 10.80 16.33
simulation is carried out using Vedic sutra to perform these
basic arithmetic operations the input given through select Power (W) 0.098 0.87
lines is of 4-bit.
V. CONCLUSION
Vedic Multipliers are used for multiplication to improve
the speed and reduce the area and power budget of the
Multipliers. In this work, Vedic processor is designed using
Vedic MAC and Vedic ALU along with other conventional
blocks in processor. The instruction set architecture of 14
instructions using register addressing modes is implemented
using instruction register and 1-bit Z flag register which
checks the status of the arithmetic group instructions. The
Fig. 15. Results of ALU with Verification Environment. comparison of simulation result of Vedic ALU and MAC
design is done with the existing ALU and MAC results. It is
The above figure shows the 16 bit operations performed observed that there is 44% savings in power in case of MAC
with ALU instructions. and that of 12% in case of ALU is achieved compared to
conventional ALU and MAC respectively. Also the delay is
reduced by 45% in case of MAC and that of 35% in case of
ALU in comparison with conventional ALU and MAC
correspondingly. The 16-bit Vedic processor reduces the delay
by 34% and saves around 88% power compared to
conventional processor. Hence the improvement in speed of
operation, reduction in power utilization and less area
utilization are the key features of designed RISC processor.
This Vedic processor is implemented using Xilinx ISE 14.7
Design Suite in Verilog and the verification of the processor is
performed using QuestaSim of Mentor Graphics.
Fig. 16. Transcript window results for matched conditions of ALU.
REFERENCES
The following figure shows transcript window results [1] S. Lad and V. S. Bendre, "Design and Comparison of Multiplier using
for ALU showing all the matched conditions. The Vedic Sutras," 2019 5th International Conference On Computing,
Communication, Control And Automation (ICCUBEA), Pune, India,
multiplier operation is performed which is integrated in 2019, pp. 1-5
processing module .The Multiplication operation is verified [2] Balpande Vishwas V, Abhishek B. Pande, Meeta J. Walke, Bhavna D.
and matched with transcript data. Choudhari and Kiran R. Bagade. “Design and Implementation of 16 Bit
Processor on FPGA.” (2015).
TABLE IV. RESOURCES UTILIZATION BY VEDIC PROCESSOR [3] Seung Pyo Jung, Jingzhe Xu, Donghoon Lee, Ju Sung Park, Kang-joo
Slice Logic Used Available Utilization Kim and Koon-shik Cho, "Design & verification of 16 bit RISC
processor," 2008 International SoC Design Conference, Busan, 2008,
Utilization pp. III-13-III-14, doi: 10.1109/SOCDC.2008.4815726.
Number of Slice 242 126,800 1%
[4] F. Adamec and T. Fryza, "Design — Time configurable processor basic
Register structure," 13th IEEE Symposium on Design and Diagnostics of
Number of Slice 1,080 63,400 1% Electronic Circuits and Systems, Vienna, 2010, pp. 119-120, doi:
LUTs 10.1109/DDECS.2010.5491804.
Number of 320 15,850 2% [5] A. Bisoyi, M. Baral and M. K. Senapati, "Comparison of a 32-bit Vedic
occupied Slices multiplier with a conventional binary multiplier," 2014 IEEE

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 International Conference on Advanced Communications, Control [8] P. S. Mane, I. Gupta and M. K. Vasantha, "Implementation of RISC
and Computing Technologies, Ramanathapuram, 2014, pp. 1757- Processor on FPGA," 2006 IEEE International Conference on Industrial
1760, doi: 10.1109/ICACCCT.2014.7019410. Technology, Mumbai, 2006, pp. 2096-2100, doi:
[6] Mr. Nishant G. Deshpande, Prof. Rashmi Mahajan, “Ancient Indian 10.1109/ICIT.2006.372448.
Vedic Mathematics based Multiplier Design for High Speed and [9] Ram, G. & Lakshmanna, Y. & Rani, D. & Kandula, Bala. (2016). Area
Low Power Processor”, IJAREEIE, Pune, 2014 efficient modified vedic multiplier. 1-5.
[7] Priyanka jain, Dr. G. S. Virdi, : Multiplier-Accumulator (MAC) 10.1109/ICCPCT.2016.7530294.
Unit: International Journal of Digital Application & Contemporary
Research ,Volume 5, Issue 3, October 2016

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