Scribd
Upload
24 views4 pages

Ca 4

This document appears to be a summary of assignments for a course on computer architecture. It includes 10 multiple choice questions related to ARM and x86 assembly language instructions, addressing modes, register sizes, and memory models. The questions cover topics like register values after a loop, the purpose of branch instructions, valid reasons for ISA compatibility across processors, and advantages of segmented memory models.

Uploaded by

iwyjqkebd
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
24 views4 pages

Ca 4

This document appears to be a summary of assignments for a course on computer architecture. It includes 10 multiple choice questions related to ARM and x86 assembly language instructions, addressing modes, register sizes, and memory models. The questions cover topics like register values after a loop, the purpose of branch instructions, valid reasons for ISA compatibility across processors, and advantages of segmented memory models.

Uploaded by

iwyjqkebd
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Week 11 ()

Week 12 ()

Text Transcripts ()

Download Videos ()

Books ()

Week 4 : Assignment 4
The due date for submitting this assignment has passed.
Due on 2023-08-23, 23:59 IST.

Assignment submitted on 2023-08-23, 21:08 IST


1) Consider the following ARM assembly program: 1 point

mov r1, #0
mov r0, #0

.loop: add r0, r0, r1


add r1, r1, #1
cmp r1, #10
ble .loop

What are the values in the registers r1 and r0, respectively, after the execution of the program?

10 and 10

9 and 50

11 and 55

9 and 10

Yes, the answer is correct.


Score: 1
Accepted Answers:
11 and 55

2) What is the function of the bl instruction in the ARM assembly language? Choose the 1 point
most appropriate answer.
Only jump unconditionally to a function

Only save the value PC + 4 in the lr register

Both jump unconditionally to a function and save the value PC + 4 in the lr register

Only stop the execution of the current program

Yes, the answer is correct.


Score: 1
Accepted Answers:
Both jump unconditionally to a function and save the value PC + 4 in the lr register

3) Consider the following load instruction and select the correct addressing mode used. 1 point

ldr r1, [r0, #9]

Register-indirect

Base-offset

Base-index

Base-scaled-index

Yes, the answer is correct.


Score: 1
Accepted Answers:
Base-offset

4) Which of the following ARM assembly instructions are used to spill a set of registers 1 point
and save it on the stack?

stmfd

ldmfd

str

addstk

Yes, the answer is correct.


Score: 1
Accepted Answers:
stmfd

5) Which of the following ARM assembly branch instructions jumps to a specified address 1 point
if and only if the negative flag (N ) is clear, that is, the number in question is positive?

ble

bpl

bve

beq
Yes, the answer is correct.
Score: 1
Accepted Answers:
bpl

6) Which of the following is a valid reason to justify the ISA compatibility of modern 64-bit 1 point
Intel machines with the older 32-bit or 16-bit processors?

Market requirements of customers running older code

16-bit processors are faster than the rest

Technological limitations of the x86 architecture

None of the options

Yes, the answer is correct.


Score: 1
Accepted Answers:
Market requirements of customers running older code

7) What is the size of the eax register in the x86 ISA? 1 point

8 bits

16 bits

32 bits

64 bits

Yes, the answer is correct.


Score: 1
Accepted Answers:
32 bits

8) What is the purpose of the Segment Descriptor Cache in an x86 processor? 1 point

Store a copy of spilled registers

Store a copy of recently accessed memory addresses

Store a copy of the relevant entries in the GDT

Store a copy of the pages currently in use

Yes, the answer is correct.


Score: 1
Accepted Answers:
Store a copy of the relevant entries in the GDT

9) Which of the following is not a rule for operands in x86 assembly instructions? 1 point

Both operands can be registers

At most one of them can be an immediate

Both the operands can be memory locations


A memory operand is encapsulated in []

Yes, the answer is correct.


Score: 1
Accepted Answers:
Both the operands can be memory locations

10) Which of the following is an advantage of a segmented memory model? 1 point

The contents of the segment registers can be changed by the OS at runtime

Easier to implement as compared to a linear memory model

Faster memory access compared to a linear memory model

All the options

Yes, the answer is correct.


Score: 1
Accepted Answers:
The contents of the segment registers can be changed by the OS at runtime

You might also like