Development of a Fully Implantable Recording

System for ECoG Signals

Jonas Pistor∗ , Janpeter Hoeffmann∗ , David Rotermund† , Elena Tolstosheeva‡ , Tim Schellenberg§ ,
Dmitriy Boll‡ , Victor Gordillo-Gonzalez¶ , Sunita Mandon¶ , Dagmar Peters-Drolshagen∗ ,
Andreas Kreiter¶ , Martin Schneider§ , Walter Lang‡ , Klaus Pawelzik† and Steffen Paul∗
∗ Institute of Electrodynamics and Microelectronics (ITEM.me), University of Bremen, Germany
Email: [email protected]
† Institute for Theoretical Physics, University of Bremen, Germany
‡ Institute for Microsensors, -actuators and -systems (IMSAS), University of Bremen, Germany
§ RF & Microwave Engineering Laboratory, University of Bremen, Germany
¶ Institute of Brain Research, University of Bremen, Germany

Abstract—This paper presents a fully implantable neural

recording system for the simultaneous recording of 128 channels.
The electrocorticography (ECoG) signals are sensed with 128 gold
electrodes embedded in a 10 µm thick polyimide foil. The signals
are picked up by eight amplifier array ICs and digitized with
a resolution of 16 bit at 10 kHz. The digitized measurement
data is processed in a reconfigurable digital ASIC, which is
fabricated in a 0.35 µm CMOS technology and occupies an area
of 2.8 × 2.8 mm2 . After data reduction, the measurement data
is fed into a transceiver IC, which transmits the data with up Fig. 1. Components of the neural recording system
to 495 kbit/s to a base station, using an RF loop antenna on
a flexible PCB. The power consumption of 84 mW is delivered
via inductive coupling from the base station.
available, which can be used as building blocks for different
I. I NTRODUCTION kinds of implantable systems [5], [6]. In contrast to a fully
Multichannel electrophysiological measurements of neural integrated system where all functions are integrated in a single
activity are a fundamental method in neural research and in chip, a building block approach allows combining highly
medical applications. advanced components into a complete recording system. Nev-
For example, observing the activity in a great number of ertheless, the design of a fully functional system is challenging
simultaneously measured channels is necessary for under- in terms of system integration, because all components have to
standing the functions of the visual cortex [1], where the co-operate and the design space (size, power) is very limited.
signals from many millions of neurons represent the first stages In this paper, we present three important aspects for the de-
of creating our visual perceptions. In this context, a 10x10 velopment of a neural recording system as shown in Fig. 1: (1)
electrode array, resulting in 100 channels, is still very small The design environment for the development and verification,
compared to the vast number and density of available neuronal (2) a digital ASIC as controller for all components and (3)
signal sources. In the medical sector, electrode arrays are used the integration down to an implantable system including the
to localize the source of epileptic seizures and later remove design of a flexible electrode array as interface to the brain.
these parts from the brain during a surgical intervention. The The following sections describe our approach to develop
higher the spatial resolution of the array, the less healthy such a system from selected components and are ordered
tissue needs to be removed from the brain. Today’s electrode as follows: In section II the design environment and test
arrays are mostly connected via cables through the skull which of the neural recording system is presented with exemplary
always brings the risk of infections and thus leads to the approaches for typical problems in the design phase. In section
demand for wireless systems. III single components of the neural recording system will
Many research groups developed highly specialized and be described in detail. Besides the power supply and the
efficient ASICs for different tasks in biomedical environments, multielectrode array, we present the digital ASIC which was
such as transceivers [2], neural amplifiers [3] and stimulation designed by our group. Section IV is about the integration of
circuits [4]. all components in a working PCB-based system and provides
In parallel, a growing number of commercial ASICs for an outlook on a fully implantable system on a flexible and
biomedical applications (neural protheses and diagnostics) are foldable foil.
978-3-9815370-0-0/DATE13/ c 2013 EDAA
Fig. 2. Prototype of the neural measurement system with all components,
wireless energy transfer and data transmission and additional debug features
for functional verification (right part of the picture shows the primary coil of
the bqTESLA bq500210EVM-689-System)[9].

II. D ESIGN E NVIRONMENT AND T EST

Fig. 3. The top diagram shows the achieved sampling interval for 10000
consecutive received data packets (each packet contains all 78 channels for
This section describes our approach of getting a working one point in time). The bottom diagram shows the number of occurrences the
system from a number of single components. It was a key sorted sample intervals from the above diagram. The correct 2.5 ms intervals
challenge to develop the interfaces between the digital ASIC are not taken into account. The highest peak is located at 5 ms, representing
the 1800 intervals of 200Hz in the top diagram.
and periphery components like the measurement front-end as
well as the RF-transceiver since no simulation models were
available. Hence, it was neccessary to develop the simulation B. SPI Decoder
models manually based on the datasheets. As there was no
While the debugging capabilities of the FPGA prototype
formal way to verify the correctness of the models, we used
are very rich, it is hard to find the cause for problems in the
an FPGA-based prototype to check wheather the running sim-
final system equipped with the ASIC. Typical test structures
ulation would result in a running hardware system. In addition
like scan chains and JTAG interfaces do not help for real time
to the FPGA-based prototype, we used a similar board holding
debugging when a high level transceiver IC is added to the
the ASIC. The peripheral components like the amplifier array
system, which creates a non-deterministic environment. In our
(RHA2116) [7] and the RF-transceiver ZL70102 [8] were put
case, a useful tool for debugging is an SPI decoder fitted to
on daughter boards and can thus be reused. Fig. 2 shows
the data structures which are interchanged between the ASIC
the prototyping system with the digital ASIC. In the picture,
and the RF-transceiver. We developed such a tool using a four
only one of the four slots is equipped with the RHA2116
channel oscilloscope and a Windows PC running LabView.
daughter board, holding two amplifier arrays and one Omnetics
Compared to other solutions the advantage of our decoder
connector for 32 electrodes.
is the usage of the deep memory and 8-bit sampling of the
oscilloscope and the comfort of analyzing the waveforms on a
A. Tcl-Enhanced Simulation Test Bench desktop PC. The software allows to browse the analogue SPI
waveforms and to have simultaneously a view on the decoded
The system test bench includes the ASIC design, models addresses with the written or read data bytes.
of the data aquisition ICs (RHA2116) and the transceiver
(ZL70102), a block generating inputs for the 128 analogue C. Real Time Data Transfer
input channels (each 16 bit) and a block which represents An advantage of using a high level RF transceiver like
the base station, sending commands to the transceiver IC the ZL70102 is that one does not have to worry about data
and receiving the measurement data. For the development integrity. The ZL70102 uses Cyclic Redundancy Check (CRC)
process it turned out to be useful to have an interactive and Reed-Solomon coding to ensure correct data transmission.
access to the simulation instead of a static set of stimuli. Corrupt data blocks are retransmitted and practically no data
Thus we developed a set of Tcl functions interacting with gets lost. Nevertheless, there is no way to control the precise
the simulation. These Tcl functions control the base station timing of the data transfer, which is one of the reasons for
model in order to write new commands into the RX-Buffer of putting a timestamp in each measurement packet as described
the implant-side transceiver. In addition, the Tcl functions can in III-B. Measurements with our prototyping setup showed that
be used to modify the test signals for the 128 input channels, transmission rates of 495 kbit/s could be achieved as long as
e.g. to generate checkerboard patterns. This approach allows the TX-Buffer in the transceiver IC is continuously filled. In
writing of verification procedures in a sequential programming our case, the first version of the digital ASIC was equipped
language with the ability to access the whole design, e.g. for with a buffer for only one set of samples (128 channels) at
testing fault cases. one point of time. It became apparent that due to the unsteady
Fig. 4. Basic measurement results from the prototyping system showing data Fig. 5. Left: Implanted ECoG array with flexible recording site and
from nine active channels. 128 electrodes (300nm thick). Right: Photo of the digital ASIC with a
side length of 2.8 mm, produced in a 350 nm standard CMOS process at
Austriamicrosystems (AMS350).

data transmission, the TX-buffer on the implant side could run

full at higher data rates. The ASIC reacts by skipping sample
events (resulting in a data loss). With an evaluation of the models not only in the test bench for verification, but also
timestamps, we analyzed the statistics of the breaks. in our ASIC and FPGA. Combined with some ramp counters,
Fig. 3 shows the analysis of a measurement with 78 ac- we obtained a build-in test mode for the ASIC, which allows
tive channels sampled at 400 Hz, resulting in a data rate of testing the data transmission of measurement data of 128 active
573.6 kbit/s. This rate is above the maximum rate of the channels without a single RHA chip attached to the system and
transceiver and was only selected to analyze the data loss. without the need to generate 128 channels of analog stimulus
In this case, 16.4% of all measurement packets are lost due to data with sub-microvolt resolution.
a full TX-buffer. The sample interval of 2.5 ms (400Hz) drops
F. System Test
to multiples of 2.5 ms. In a sequence of 10000 sample points
the longest interval of 37.5 ms occured once and the shortest Using the system prototype shown in Fig. 2, we did some
interval (except for the wanted 2.5ms) of 5ms occurred 1800 basic tests. A sinusoidal wave with 35 Hz was applied to 16
times. The short breaks could not be prevented, as the data input channels and was sampled with 1 kHz and a resolution of
rate is too high. The user could only lower the resolution or 10 bit, demonstrating system functionality of the base station,
exclude some channels from the measurement. The long break contactless power supply, contactless data transmission, clock
of 35ms was relevant for the dimensioning of the buffer, as it generation, digital ASIC and amplifier arrays. Fig. 4 shows
could be catched with a buffer of 2.3kB. Later we configured the received data from the contactless measurement.
the ZL70102 to include more synchronization words in the
data packets which lead to better results with shorter breaks III. C OMPONENTS
in our situation. With the new results we decided to integrate a A. Multielectrode Array
2 kB buffer for the redesigned ASIC, using an SRAM module
provided by the foundry. If for any reason this buffer still For acquisition of electrophysiological activity, it is crucial
runs full during a measurement, the controller reacts on this to design a multielectrode array, suited to the measurement
situation and prevents a corruption of the measurement packets task. The presented epidural multielectrode grid was designed
and thus also prevents the waste of transfer rate due to invalid to aquire ECoG signals. This electrode array was tested in pri-
data. mary visual cortex of a non-human primate (Macaca mulatta)
measuring neural population activity with a high spatial and
D. FPGA-Co-Design temporal resolution. The multi-/microelectrode array presented
To keep the FPGA design as close as possible to the in this work consists of 128 embedded gold electrodes with
ASIC design, we set up a design framework based on the diameters of 100 µm, 300 µm and 500 µm [10]. The surface
Cadence AMS Designer Command Line Flow. The differences electrodes are sandwiched between two 5 µm thick polyimide
between FPGA and ASIC in terms of memories, IO-Cells and thin-films. This makes the electrode array very flexible in
incompatibilities due to the prototyping platform were handled order to adapt to the surface of the brain. The active area
with Verilog compile switches inside the code. Shell scripts covered with recording sites has a size of 135 mm2 . The
were used to generate a repeatable environment for simulation spatial arrangement of the electrodes as depicted in Fig. 5
and synthesis of different design configurations. allows grouping of equidistant electrodes for analysis of the
spatial spectrum. Furthermore, the hexagonally shaped outline
E. Test Features of the electrode area ensures symmetry. The array is designed
The simulation models of the RHA front ends were designed for chronic implantation. During implantation the reference
as synthesizable RTL code. This enabled us to place the electrode is folded on top of the backside of the array.
 Fig. 6. Architecture of the digital ASIC. Fig. 7. Test board for the power supply, data transmission and clock
generation.

B. Digital ASIC
With this set of commands the user is able to adapt the
Since area and power is a hard constraint for brain implants, system to many different measurement situations in the field
the use of an ASIC which is exactly designed for its task is a of neural prostheses and medical diagnostics.
better solution than using oversized FPGAs, microcontrollers In Fig. 6 a block diagram of the architecture of the digital
or DSPs. Furthermore, some of the external components could ASIC is shown. The measurement data enters the ASIC on
be integrated in our ASIC in the future, which also decreases eight serial data lines, each carrying 16 channels of digitized
the size and increases the reliablity. raw data (25 bit-data-frame/channel) with a resolution of 16
The architecture of our ASIC and the implementation as an bit and a fixed sample rate of 10 kS/s/channel. The measure-
FPGA based prototype was described in detail in [11]. Later, ment interface reduces the incoming data rate in a flexible
we also published the results of the first implementation in 150 combination of resolution, sample rate and number of active
nm CMOS technology [12], missing some important features channels, according to the desired measurement task, stored
like the interface to the RF-transceiver which are included in in the register bank.
the current version. The protocol builder buffers the filtered data of the last sample
Our ASIC collects digitized recording data at a data rate of point, adds a header with timestamp and configuration data
20.48 Mbit/s in total. The RF-transceiver (ZL70102) reaches and combines the eight serial lines to one single measurement
average data rates of 495 kbit/s in our test setup and is packet, containing all selected and sorted channels in the
connected to the ASIC via an SPI-interface. In comparing desired resolution and sample rate. The measurement packet is
the data rate of the incoming measurement data with the fed into the transceiver interface, which controls the medical
data rate of the RF-transceiver, it becomes obvious that the RF-transceiver ZL70102 and maps the data to blocks of 14
direct copy of the raw data can not be transmitted. To address Bytes as needed by the ZL70102 for high data rate transmis-
this restriction, the ASIC is equipped with a reconfigurable sions. It also manages the transfer of incoming commands to
data path allowing runtime reconfiguration in order to exploit the controller, which sets the system to the configuration given
the limited transceiver data rate in a way best suited for the by the operator.
particular application. Fig. 5 shows a photo of the fabricated ASIC in the AMS
The ASIC supports the following commands: 350 nm process with an area of (2.8 × 2.8) mm2 . At 3.3 V the
• enable/disable: Activation/deactivation of the data trans- power consumption is 10.5 mW. Most of the area and power
fer from the implant to the external base station. is taken by the data buffer, which is currently implemented as
• samplerate: Configures the sample rate in 256 steps from D-Flip-flops.
10 kSamples/s/channel down to 39 Samples/s/channel.
• channelmask: Allows the user to select a subset from the C. Power Supply and Telemetry
available 128 channels to be transmitted to the external The power supply of the implant is realized with the
base station. BQ51013YFF (from the Texas Instruments wireless power
• resolution: The amplitude resolution of all active chan- solution bqTESLA[9]) and a Torex XCL205 DC/DC converter
nels can be adjusted between 1 bit and 16 bit. to obtain a stabilized 3.3 V DC voltage with high efficiency on
• filter: The ASIC has the ability to modify the cutoff the implant side, which is necessary to keep the heating of the
frequencies of the RHA2116 analogue bandpass filter brain tissue low. In the datasheet of the bq25046EVM-687[9]
using external components. Four values for the low pass which served as base for our design, the efficiency is given
frequency between 10 Hz and 100 kHz and four values with 70%.
for the high pass frequency between 0.02 Hz and 1 kHz The data transmission is performed by the ZL70102
are selectable. transceiver [8], using the Medical Implant Communication
 between the transceiver IC ZL70102 and a Linux or Windows
Host PC providing the user interface is realized using an
FPGA module with Ethernet port (Orange Tree Technolo-
gies ZestET1). The ZestET1 contains a Xilinx Spartan 3A
(XC3S1400A) FPGA which is programmed with the firmware
by the base station software via the Ethernet connection in the
initialization phase. The firmware, written in VHDL, contains
an SPI interface to access the registers of the ZL70102
transceiver. In the connect phase, the firmware configures the
ZL70102 according to the configuration on the implant side,
transmission mode is set to 4-FSK, the channel number is
set and an 48 bit ID is programmed, which serves as key to
connect only to the fitting transceiver module on the implant
side. In a handshaking mechanism the base station polls the
ZL70102 until a connection to the implant is established. This
coupling is persistent, even if the transceiver antennas leave
Fig. 8. Measured load behavior and efficiency of the inductive power supply. their range. After the connection sequence, the digital ASIC
Efficiency value is calculated by the ratio of DC output power at the implant of the implant is configured as described in III-B. In our lab
side and DC input power for the base station.
setup, the management of the base station is performed by
a set of simple command line tools. This allows the use of
Service (MICS) at frequencies of 401 − 406 MHz. For the adapted shell scripts which make a repeatable batch testing
implant, we developed a loop antenna with a diameter of effortless. These binaries use a TCP/IP connection for sending
5 mm and matched it to the impedance of the transceiver. As command strings to the network buffer of the ZestET1. The
described in II-C, data rates with approximately 500 kbit/s on-board FPGA decodes these network packages and writes
could be achieved over a distance of 5 cm using this antenna on the corresponding data into the TX register of the transceiver
the implant side and a similar but square shaped loop antenna via the SPI interface. As soon as the ASIC on the implant
at the base station. is fully configured and the measurement is started, the base
In the design phase, we developed a flexible PCB with the station polls the level of the transceiver RX buffer via SPI.
approximate size of the final implant containing the power It reads out the RX buffer of the ZL70102 transceiver in
supply IC, the quartz crystal for the system clock, the ZL70102 blocks of 14 bytes and stores this data in the network buffer,
transceiver, the loop antenna for the ZL and the coil for the from where is is read by the base station software. The
inductive coupling. This module (shown in Fig. 7) was used base station software is written in C++ and currently uses
to check the concurrent operation of both ZL transceiver and the Matlab API to visualize the measurement data, which is
inductive link in a measurement task with the ASIC and the simultaneously written to the hard disc. The FPGA on the
amplifier arrays. We performed a load test using a source- base station adds to every package of received measurement
measure unit which shows that the stabilized DC output at data an additional timestamp and 16 binary trigger channels.
the implant site keeps around 3.3 V in a range suitable for all This allows synchronization with other external devices like
components. The efficiency shown in Fig. 8 is calculated for stimulus generators. The software is currently intended for
the overall system and thus includes the uncritical losses at the engineering purpose, but it can also be adapted to fit into
base station. The test was performed at a distance of 2.4 mm existing EEG/ECoG applications. The firmware in the FPGA
between the primary and the secondary coil. The secondary and the use of the network interface provides operation-
coil is constructed by 16 turns of litz wire on an area of 2 × system-independent accessibility.
2 cm2 as shown in Fig. 7.
IV. S YSTEM I NTEGRATION
TABLE I With the PCB-system presented in Fig. 2 we are able to
P OWER DISSIPATION OF IMPLANT COMPONENTS
test the system, especially the functional compability of all
Component ASIC ZL70102 8*RHA2116 Quartz Sum components without negative influences between inductive
Power /mW 10.5 17 40 16.5 84 power supply and RF transmission in a very small space.
For the analysis of the signal quality referred to the electrode
inputs we developed a prototype (Fig. 9) with small outlines
D. Base Station which is currently in production. The small size even allows
The base station provides inductive power supply, wireless for implantation on the cortex to test the system in the targeted
data transmission and a user interface for control and visuali- environment before the final design with the electrode array
sation/recording. described in III-A will be started.
The contactless power supply currently works independently This implantable prototype is divided into four sections
and is described in III-C. A bidirectional data transmission enabling the flexible PCB to be folded to an area of (2.4 ×
 operation, it is possible to adapt the system at any time and
to track possible changes in the neural activity patterns.
ACKNOWLEDGMENT
This work was supported by the Bundesministerium fuer
Bildung und Forschung, Grant 01 EZ 0867 (Innovationswet-
tbewerb Medizintechnik) and Forschungsschwerpunkt Neu-
rotechnologie Universitaet Bremen. This research was con-
ducted as part of a BMBF research and development project.
Beside the University of Bremen, the company Brain Products
GmbH and the University Hospital of Bonn (Department of
Epileptology) are part of this research association.

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