@shraddha_pawankar Date 17/08/23

Que 1) How do you model combinational logic using concurrent blocks in Verilog?

Method 1: Continuous Assignments with "assign"

module combinational_logic(input wire A, input wire B, input wire C, output wire Y);

// Continuous assignment using assign statement

assign Y = (A & B) | (~C); // Y is the output of the combinational logic

endmodule

Method 2: Combinational Procedural Block with "always_comb"

module CombinationalLogicUsingAlwaysComb(input wire A, input wire B, input wire C, output

wire Y);

// Combinational logic using always_comb block

always_comb begin

Y = (A & B) | (~C); // Y is the output of the combinational logic

end

endmodule

Que 2) How do you model sequential logic using procedural blocks in Verilog?

In Verilog, we can model sequential logic using procedural blocks with the "always" keyword.

Ex:

module DFlipFlop(input wire clk, input wire reset, input wire D, output reg Q);
always @(posedge clk or posedge reset) begin
if (reset) begin

Q <= 0; // Asynchronous reset: Q is set to 0 when reset is asserted.

end else begin
Q <= D; // Synchronous update: Q takes the value of D on the rising edge of the clock.
end
end

endmodule

Que 3) What is the importance of sensitivity lists in concurrent blocks?

@shraddha_pawankar Date 17/08/23

In Verilog, there are two types of sensitivity lists commonly used in concurrent blocks:

Sensitivity Lists for Continuous Assignments:

module CombinationalLogic(input wire A, input wire B, output reg Y);

// Continuous assignment with sensitivity list (A and B)

assign Y = A & B;

endmodule

Sensitivity Lists for Procedural Blocks:

module EdgeDetector(input wire clk, input wire reset, input wire data, output reg
posedge_detected);

// Procedural block with sensitivity list (posedge clk, data, reset)

always @(posedge clk or posedge reset or data) begin

if (reset) begin
posedge_detected <= 0;
end else if (data && !posedge_detected) begin
posedge_detected <= 1;

end
end

endmodule

Que 3) How do you create a clocked sequential block in Verilog?

To create a clocked sequential block in Verilog, we typically use an "always" block sensitive to
the positive edge (posedge) or negative edge (negedge) of a clock signal.

Ex: always@(posedge clk) or always@(negedge clk)

module DFlipFlop(input wire clk, input wire reset, input wire D, output reg Q);

// Clocked sequential block sensitive to the positive edge of the clock

always @(posedge clk) begin
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if (reset) begin
Q <= 0; // Asynchronous reset: Q is set to 0 when reset is asserted.
end else begin

Q <= D; // Synchronous update: Q takes the value of D on the rising edge of the clock.
end
end

endmodule

Que 4) What are the best practices for writing synthesizable Verilog code inside
procedural blocks?

Avoid Inferring Latches:

Example (Undesirable):

always @(posedge clk) begin

if (reset)

data_out <= 0; // Data_out not assigned in the else branch, leads to a latch.

End

Example (Preferred):

always @(posedge clk) begin

if (reset)
data_out <= 0;
else

data_out <= data_in;

end

Use Non-Blocking Assignments for Flip-Flops:

always @(posedge clk) begin

if (reset)
data_out <= 0;
else
data_out <= data_in;
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end

Use Blocking Assignments for Combinational Logic:

always @(data_in) begin

if (data_in == 4'b1010)
result = 1; // Blocking assignment for combinational logic.
else
result = 0;

end

Avoid Mixed Combinational and Sequential Blocks:

always @(posedge clk) begin

if (reset)

data_out <= 0;
else
data_out <= data_in;

if (data_in == 4'b1010)

result = 1; // Mixing sequential and combinational logic.

else
result = 0;
end

Que 4) What is the purpose of the "posedge" and "negedge" keywords in procedural
blocks?

The "posedge" and "negedge" keywords in procedural blocks in Verilog are used to specify
sensitivity to the positive edge (rising edge) and negative edge (falling edge) of a signal,
respectively

posedge:

The "posedge" keyword is used to indicate sensitivity to the positive edge (rising edge) of a
clock

"posedge" transitions from low (0) to high (1), the block is triggered and executed.

negedge:
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The "negedge" keyword is used to indicate sensitivity to the negative edge (falling edge) of a
clock

"negedge" transitions from high (1) to low (0), the block is triggered and executed.

Que 6) Can you explain the concept of "fork" and "join" in procedural blocks?

In Verilog, "fork" and "join" are used to create concurrent execution regions within
procedural blocks.

These keywords are often used together to execute multiple blocks of code concurrently,
enabling parallelism and improving simulation speed.

Que 7) Can you provide examples of using "wait" statements in procedural blocks?

In Verilog, "wait" statements are used in testbenches to introduce timing delays during
simulation.

They are not synthesizable and should only be used in testbench code for simulation
purposes.

"wait" statements can be useful for controlling the timing of events, such as stimulus
generation

Que 8) How do you use "disable" statements in procedural blocks?

In Verilog, the "disable" statement is used to terminate or disable procedural blocks.

The "disable" statement is not synthesizable and should only be used in testbench code for
simulation purposes.

The "disable" statement is particularly useful when we want to stop specific processes or
sequences early during simulation

Que 9) How do you handle tri-state logic in Verilog using concurrent blocks?

in Verilog, you can handle tri-state logic using concurrent blocks by using the assign
statement with the trireg data type.

The trireg data type is used to model tri-state signals in Verilog.

Ex:

module TriStateBuffer(

input wire enable,

input wire [7:0] data_in,

output trireg [7:0] data_out

);
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assign data_out = enable ? data_in : 8'bz; // Tri-state buffer implementation

endmodule

Que 10) How do you use "for" loops inside concurrent blocks?

Ex:

module BitwiseAndExample(input wire [3:0] A, input wire [3:0] B, output wire [3:0] result);

always_comb begin

for (int i = 0; i < 4; i = i + 1)

result[i] = A[i] & B[i]; // Parallel bitwise AND operation

end

endmodule

Que 11) Can you describe the concept of "logic" data types in Verilog inside procedural
blocks?

The "logic" data type can store four values: 0, 1, Z (high-impedance), and X (unknown). It is
an efficient data type for representing digital logic values and is recommended over "reg" for
synthesizable and non-synthesizable code.

Ex:

module CounterExample;

always @(posedge clk) begin

logic [3:0] count;

count = count + 1; // Incrementing the count

$display("Count: %d", count);

end

endmodule

Que 12) Explain the difference between procedural continuous assignment and
concurrent continuous assignment

Procedural Continuous Assignment:

Procedural continuous assignment is defined inside a procedural block, such as an "initial" or

"always" block
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the assignment is triggered by events in the procedural block, and it is executed sequentially
within that block.

Example:

module ProceduralContinuousAssignmentExample(input wire A, input wire B, output wire

Y);

always @(A or B) begin //always@(A or B) Procedural continuous block

if (A & B)

Y = 1;

else if (A | B)

Y = 0;

else

Y = 1'bZ;

end

endmodule

Concurrent Continuous Assignment:

Concurrent continuous assignment is defined outside any procedural block, typically at the
module level

Ex:

module ConcurrentContinuousAssignmentExample(input wire A, input wire B, output wire

Y);

assign Y = (A & B) ? 1 : ((A | B) ? 0 : 1'bz); //concurrent continuous assignment block

endmodule

Comparison:

 Procedural Continuous Assignment: Used inside procedural blocks,

triggered by events in the block, sequential execution, suitable for modeling
combinational logic in a procedural manner.

 Concurrent Continuous Assignment: Used at the module level, continuous

concurrent execution, suitable for pure combinational logic, where outputs
depend only on the inputs.

Que 13) How do you handle metastability in Verilog using concurrent and procedural
blocks?
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Metastability occurs when an asynchronous input signal changes close to the clock edge,
and there is a possibility of the flip-flop or register entering an unpredictable state.

Synchronizers:

Asynchronous Reset:

Handshaking:

Que 14) How do you handle clock enable signals in Verilog using concurrent and
procedural blocks?

. Concurrent Block:

use an "always_ff" block with an additional enable condition to control the clocking of
registers or flip-flops.

Procedural Block:

Use always block

Que 15) How do you implement a combinational circuit with multiple outputs in
Verilog?

To implement a combinational circuit with multiple outputs in Verilog, we can use a

concurrent "always_comb" block to describe the combinational logic.

module Decoder2to4(

input wire [1:0] input,

output wire [3:0] output

);

always_comb begin

case (input)

2'b00: output = 4'b0001;

2'b01: output = 4'b0010;

2'b10: output = 4'b0100;

2'b11: output = 4'b1000;

default: output = 4'b0000; // Default output when input does not match any case

endcase

end
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endmodule

Que 16) Explain the concept of "always_latch" with "posedge" and "negedge"
conditions.

In Verilog, the "always_latch" block is a unique type of hardware modeling block that
represents a latch. A latch is a level-sensitive memory element, different from a flip-flop
which is edge-sensitive

The "always_latch" block is not recommended for use in synthesis due to its level-sensitive
behavior, as it can lead to undesirable behavior and potential race conditions in hardware

designs. Instead, flip-flops or registers should be used for sequential elements.

Ex: Level-Sensitive Latch with "posedge" and "negedge" Conditions:

module LatchExample(

input wire enable,

input wire data,

output reg latch_output

);

always_latch

begin

if (enable) begin

latch_output <= data; // Level-sensitive latch behavior when enable is asserted

end

end

endmodule

Que 17) How do you model a RAM (Random Access Memory) in Verilog using
concurrent and procedural blocks?

Example: RAM with Concurrent and Procedural Blocks

verilog
module RAMExample(
input wire clk,
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input wire [7:0] address,

input wire write_enable,
input wire [7:0] data_in,

output reg [7:0] data_out

);

// RAM with 256 8-bit words (size of 256x8 bits)

reg [7:0] ram [0:255];

always_comb begin
data_out = ram[address]; // Read operation: Output data from RAM based on the address
end

always_ff @(posedge clk) begin

if (write_enable) begin
ram[address] <= data_in; // Write operation: Store data_in into the RAM at the specified
address
end
end

endmodule

RAM with Procedural Block

module RAMSimulationExample;

// RAM with 256 8-bit words (size of 256x8 bits)

reg [7:0] ram [0:255];

initial begin
// Initialize RAM contents with some test data

for (int i = 0; i < 256; i = i + 1) begin

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ram[i] = i; // Store the value of 'i' in each word of RAM

end

// Perform read and write operations

#10;
$display("Data at address 42: %d", ram[42]); // Read data at address 42

#10;

ram[100] = 255; // Write data 255 at address 100

#10;
$display("Data at address 100 after write: %d", ram[100]); // Read data at address 100
after write

#10;

$finish; // End the simulation

end

endmodule

Que 18) What are the best practices for designing testbenches with procedural and
concurrent blocks?

Testbenches can be designed using both procedural and concurrent blocks.

Use Concurrent Blocks for Stimulus Generation:

use concurrent blocks (e.g., "initial" or "always_comb") to generate stimulus for the design
under test (DUT).

Use Procedural Blocks for Testbench Control:

Procedural blocks (e.g., "initial" or "always") are well-suited for controlling the overall
testbench behavior, such as initialization, stimulus generation sequence, and test completion.

Que 19) What are the implications of using "always_comb" in sequential logic designs?

The "always_comb" block is intended for combinational logic, and using it in sequential logic
designs can result in incorrect hardware implementation and unpredictable results.
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To design proper sequential logic, use "always_ff" or "always @(posedge clk)" blocks for state
updates and output assignments.

Use "always_comb" for combinational logic, where the outputs are entirely determined by
the inputs without any clocked elements.

Que 20) Explain the implications of using "always_ff" in combinational logic designs.
"always_ff" in combinational logic designs can lead to incorrect hardware implementation
and unpredictable behavior

It infer latch

Que 21) How are procedural blocks used in Verilog?

Procedural blocks are used in Verilog to define the behavior of a design through the use of
procedural statements.

Procedural blocks are used to model sequential logic, timing delays,

initial blocks:

An "initial" block is executed only once at the beginning of the simulation. It is typically used
for initializing variables, generating stimuli, and setting up the test environment.

always blocks:

An "always" block is executed continuously based on its sensitivity list. There are different
types of "always" blocks in Verilog, including "always @*", "always @(posedge clk)", and
"always @(negedge clk)" among others.

final blocks:

A "final" block is executed only once at the end of the simulation. It is typically used for
performing cleanup operations and generating final reports.

Que 22) How are concurrent blocks used in Verilog?

Concurrent blocks in Verilog are used to describe hardware behavior that occurs
concurrently, meaning the statements inside these blocks are executed in parallel.

There are two main types of concurrent blocks in Verilog: "always_comb" and "always_ff."

always_comb:

The "always_comb" block is used for modeling combinational logic

always_comb for Combinational Logic:

module CombinationalLogic(

input wire a,

input wire b,
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output reg y

);

always_comb begin

y = a & b; // Combinational AND logic using always_comb

end

endmodule

always_ff for Sequential Logic:

always_ff:

The "always_ff" block is used for modeling sequential logic that is clocked by a specific clock
signal

module SequentialLogic(

input wire clk,

input wire reset,

input wire data_in,

output reg data_out

);

always_ff @(posedge clk) begin

if (reset) begin

data_out <= 0; // Synchronous reset to 0 on the positive clock edge

end else begin

data_out <= data_in; // Synchronous assignment of data_in on positive clock edge

end

end

endmodule

Que 23) Explain the usage of "posedge" and "negedge" with "if" conditions in procedural
blocks.
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Using "posedge" in an "always" Block:

module PosedgeExample(

input wire clk,

input wire data_in,

output reg data_out

);

always @(posedge clk) begin

if (data_in) begin

data_out <= data_in; // Assign data_in to data_out on the rising edge of clk

end

end

endmodule

Using "negedge" in an "always" Block:

module negedgeExample(

input wire clk,

input wire data_in,

output reg data_out

);

always @(negedge clk) begin

if (data_in) begin

data_out <= data_in; // Assign data_in to data_out on the falling edge of clk

end

end

endmodule
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