Proceedings of the Fifth International Conference on Communication and Electronics Systems (ICCES 2020)

IEEE Conference Record # 48766; IEEE Xplore ISBN: 978-1-7281-5371-1

Design of UART Module using ASMD

Technique
Sowmya K B Shreyans Gomes Vishnusai Reddy Tadiparthi
Department of Electronics and Department of Electronics and Department of Electronics and
Communication Engineering Communication Engineering Communication Engineering
R.V college of Engineering R.V college of Engineering R.V college of Engineering
Bangalore, India. Bangalore, India. Bangalore, India.
[email protected] [email protected] [email protected]

Abstract - Universal Asynchronous Receiver Transmitter the transmitter. The first bit is called Start bit, which is ‘0’,
(UART) is an integrated circuit, which is commonly included in and the bits which follow the start bits are data bits, whose
microcontrollers and it is usually operated at a baud rate of length ranges between 5 and 7 bits. The ensuing bit is the
20Mbps, which is usually achieved by using a clock of 20MHz. parity bit. It is added as a checksum to check for any data
Due to its advantages such as high reliability, long-distance
range, and low cost, it is widely used in the data communication corruption while it travels through a channel, In the end, a stop
process, especially in serial communications over a computer or bit of ‘1’ is added to indicate the end of the frame. The data
peripheral device serial port. As indicated or hinted by the travels in a frame in the above format through a channel. The
designation of the term ‘universal’, the format and transmission data, which is captured at the receiver end, is sampled at a rate
speeds of data are configurable to achieve the required operating of 11 clock cycles per second. The captured data is then
condition(s). FIFO (First-In-First-Out) technique is used to store transferred to a shift register for accumulation. These both
the data temporarily during high-speed transmissions and it is receiver and transmitter architectures are helpful in the
also used for synchronization. Usually, the data is serially successful implementation of the UART. It may also include
transmitted one by one into the channel. The output is taken at a
different techniques to control the data flow such as the baud
sampling period of 10 clock cycles and parallel stored as the data
arrives. The results obtained from this experiment indicate that rate generator. Data conversion in UART happens at very high
the working of the proposed model can be correlated to or is speed without loss of data. The data exchanged is of American
similar to the results obtained from the theoretical approach in Standard Code for Information Interchange (ASCII) format.
the form of frame arrangement and stacking of data. This paper Besides RS-232, RS-422 and RS-485 standards have been
proposes a change in the frame format to involving the commonly applied to UART chips nowadays. This paper
microcontroller or microprocessor, which will control the proposed a modified frame format, where it made use of
operation of UART based on the extra bit(s) in the frame, to hamming code for error detection and flags for indicating the
achieve option(s) for power saving. To design such a circuit at a required action to microprocessor like resend data or stop
gate level is tedious and consumes a large amount of time due to
sending data etc. Di stands for data bit i, while Pi stands for
the increasing complexity of integrated circuit technology, hence
the use of hardware description language such as Verilog HDL is parity bit i. P3 is the extra parity bit. The frame format is as
becoming popular because it makes it easy to design a circuit of shown below:
any complexity. Verilog is pretty different from VHDL. Verilog is
not as verbose as VHDL, so that is why it is more compact and
hardware modeling is better in it than VHDL, even though it has Start P P D P D D D P er en ack Stop
a lower level of programming constructs than VHDL. bit 0 1 0 2 1 2 3 3 bit

Keywords – UART, Transmitter, Receiver, Control unit, Fig.1. T he frame format for UART
Datapath unit.

I. INT RODUCT ION The bits en, ack , and er are given as inputs by the
Data transmission is achieved through the use of UART via a microprocessor. The bit en is used by the receiver side to
serial port on the computer to transmit and receive data. indicate the transmitter to halt transmission. This doesn’t halt
Parallel-to-serial conversion is performed at the transmitter the transmission of data indefinitely. The microcontroller or
side and serial-to-parallel conversion is performed at the microprocessor will wait for time t, the time required to
receiver side. Buffer(s) are present at both the transmitter and transmit once from the transmitter to the receiver. This has to
receiver, which are used to contain data, that is the data is be coded into the microprocessor’s program. This may be due
accumulated here before being used for further processing. to various reasons, such as an error is detected or the rate of
Generally, an 8-bit long format is used to send the data from processing of data is slower than the rate of transmission and

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 Proceedings of the Fifth International Conference on Communication and Electronics Systems (ICCES 2020)
IEEE Conference Record # 48766; IEEE Xplore ISBN: 978-1-7281-5371-1

reception of data. The bit er is used to indicate that there was It works based on the ASMD chart. Here, the transmitter goes
an error in the transmitted data. Although a hamming code through three idle states, waiting and sending. These states are
generator is used to encode the data, there is still a chance that saved as 01, 11, and 10 respectively and the next state is
the data may be corrupted due to various factors, such as achieved by performing left shift operation on the current state
glitches or EMI, etc. At the receiver side, the program which once and the added bit, the last is the output of XOR operation
is running on the microprocessor will carry out the detection to the bits of the previous stage. When the active low reset
of errors, based on the output of the hamming code decoder. signal, rst_b, is asserted, the state machine enters an idle state,
The received data is sent back as a check to see if the received bi_count is flushed and T_shftreg is loaded with all 1’s. In this
state, if an active edge of Clock occurs while the rst_b is high,
data is correct and an acknowledgment is sent to the receiver
the system checks for Load_T_dreg. When this state is
side. The ack is used by the microprocessor to indicate the
asserted by the external host, the output signal Load_T_DR
transmitter that data is received properly without any error and will load the content of D_Bus into T_d_reg. After this, at the
that er bit is valid. The acknowledgment sent by the receiver positive edge of clock pulse the machine will check for
during the first transmission is in the form of this en and er By_ready signal. When the system asserts this signal at the
bits. positive edge of clock cycle machine enters into
Load_T_shftreg where the data register T_shftreg is filled with
II. LITERATURE SURVEY the data from T_dreg with an additional er, en and stop bit.
Implementation and working of UART and frame format are After that, the state is driven to waiting unless T_by is
important in retrieving the data bits after they are transmitted assessed at the positive edge of the clock the state remains the
into the channel [2]. Understanding of UART at the circuit same. Once T_by is asserted at the positive edge of the clock
level, the inclusion of various flags to determine the status of the state is driven to sending before which a start action will
data bits was also a motivation behind this paper [6]. The take place and data is continuously transmitted until the
operation of transmitter and receiver and utilization of the counter reaches BC_lt_BCmax (maximum allowable value).
clock dividing technique was also implemented [2]. Power Once this maximum value is reached, the stop bit is appended
analysis of a circuit helped us to understand the need of using and the registers are flushed while the state is returned to idle
minimal power when it is implemented on FPGA [1]. The (as shown in figure 3).
different number of bits and its usage in UART frame format
helped us to utilize its flexibility as much as possible [3].

III. TRANSMITTER ARCHITECTURE

The processor provides the input signal and the output in a
serial data stream, a status signal, and two error signals. The
transmitter architecture is composed of a hamming code
generator, a control unit, a data register, a data shift register,
and a status register which is used to keep track of the number
of bits that are transmitted and it is included in the datapath
unit. The controller has two types of inputs namely external
input and internal input. Load_T_dreg, By_ready, T_by,
Clock, rst_b are classified as external inputs, while
BC_lt_BCmax is an internal input. The outputs of this control
unit namely Load_T_DR, Load_T_shftreg, start, shift, and
clear are purely internal, and they serve as internal inputs to
datapath unit while D_Bus serves as an external input to
datapath unit with Serial_out being the external output. This
output is the one that transmits the parallel data into the
channel in a serial fashion (as shown in figure 2).

Fig.3. ASMD flow diagram for T ransmitter architecture

Fig.2. T ransmitt er Architecture Block Diagram

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 Proceedings of the Fifth International Conference on Communication and Electronics Systems (ICCES 2020)
IEEE Conference Record # 48766; IEEE Xplore ISBN: 978-1-7281-5371-1

IV. RECEIVER ARCHITECTURE

The UART receiver receives the serial bit stream of data,
removes the Start bit, reads the flag bits, decodes the hamming
code and transfers the received data in a parallel format to a
storage register connected to the host data bus and the rest of
the outputs, such a syndrome vector and en and er to the
microcontroller. There must be separate Clock and reset signal
at the receiver side, which must be synchronized with the
transmitter’s clock. This can be done in various ways. One
such method is the use of a Phase-locked loop. Here, the data
is taken as samples by sampling the received data stream at a
regular interval of time. The sampling rate is 11 times the
clock period. It also has a control unit and a datapath unit. The
control unit has external inputs which are Samp_clock, rst_b,
read_not_ready_in. The outputs of this control unit, which are
clr_Samp_counter, inc_Samp_counter, clr_b_counter,
inc_b_counter, shift, and load, serve as inputs to the datapath
unit, which also has an external input called Serial_in. The
output from the datapath unit is Ser_in, SC_eq, SC_lt, and
BC_eq. Along with this it also has an external output named
RCV_dreg, which gives the data output in parallel form (as
shown in figure 4). The RCV_dreg is sent to the hamming
code decoder and the output syndrome vector and the received
data and outputs are sent to the microprocessor.
It also has three states like three transmitter side and they are
operated similarly. They are named as idle, starting and
receiving. In the idle state when rst_b is not equal to 0 and
SC_in is 1, the state machine enters the starting state, where it
checks for continuous 0’s. When 4 consecutive 0 appears, the
machine recognizes it as a start bit and enters the receiving
state. This can be handled by inc_Samp_counter. Once it
enters receiving state, clr_Samp_counter is enabled to clear
the sample counter and bits are taken after every 11 clock
cycles, this can be handled by inc_Samp_counter and
clr_Samp_counter. To check the number of bits received
inc_bi_counter is used to increment a counter and shift the bits
in RCV_shftreg. Along with this, BC_eq is used to count the
number of bits received Fig.5. ASMD flow diagram for Receiver architecture

Once 11 bits are received it checks for signal from the host. If
read_not_ready_in is enabled an error signal, Error1, is
asserted and the state machine moves to the idle state. If it is
not 1 and if Ser_in is 1 an error signal, Error2, is asserted, the
state machine also moves to the idle state. If Ser_in is also
zero then load signal will be asserted and the parallel data will
be loaded into RCV_dreg which is the output passed to the
processor and the state machine moves into the idle state (as
shown in figure 5).

V. RESULT ANALYSIS
A. Transmitter Output
Here, it is observed that, when rst_b is 0 the system enters
Fig.4. Receiver Architecture Block Diagram
into reset mode where everything is set to initial condition.
When Load_T_Dreg is 1 and rst_b is 1 during a positive

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 Proceedings of the Fifth International Conference on Communication and Electronics Systems (ICCES 2020)
IEEE Conference Record # 48766; IEEE Xplore ISBN: 978-1-7281-5371-1

edge of the clock the system checks for By_ready. regarding the resources utilized for the implementation of
Similarly, when By_ready is 1 and rst_b is 1 at the positive transmitter and receiver architectures. Also, they provide us
edge of the clock, system checks for T_by and when T_by the insight on minimum required cells, ports, nets, LUTs
is 1 and rst_b is 1 at the positive edge of the clock the (Lookup tables), etc.
system starts transmitting data. The required data is
encoded using a hamming code generator and is passed
onto d_bus. The data present on the d_bus is transmitted
serially on serial_out. The input is represented by d_bus.
At 40ns a start bit of value 0 is sent followed by the data in
the d_bus serially. After sending the data it is observed that
a stop bit of 1 is sent to signal the end of the frame (as
shown in figure 6). A slightly modified version of the
ASMD diagram was used for testing of this ASMD
diagram since the testing was done using software tools
and no hardware was used.

Fig.7. Receiver Output

Fig.6. T ransmitter Output

B. Receiver Output
In the receiver end, when a data is received at Serial_in it
checks for 4 continuous 0’s which will signal that a start bit
received. The Sample_clk takes the input data at every 10th
clock cycle. The data received is obtained serially at the input.
RCV_datareg shows the loading of serially obtained data into
parallel form by shifting it towards LSB bit by bit. This
process takes place until the BC_eq_8 becomes 1 and passes it
to the next state. It is also seen that, when all the bits are
transmitted it sends a signal read_not_ready_out to the host
processor to stop sending data for a while. At the same time,
an Error2 signal is asserted for a while since the Serial_in data
are 0. The zero-bit received at the end is stop bit which signals
the end of the frame (as shown in figure 7). This data is sent to
a hamming code decoder which will decode the data and send
it to a microprocessor or microcontroller for further use.

VI. RTL DIAGRAM AND SYNTHESIS

The RTL view for Transmitter and Receiver is generated
and various information on design such as nets, cells , and I/O Fig.8. RT L Schematic of the hamming code generator
ports are tabulated. These values give us information

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 Proceedings of the Fifth International Conference on Communication and Electronics Systems (ICCES 2020)
IEEE Conference Record # 48766; IEEE Xplore ISBN: 978-1-7281-5371-1

Fig. 11. Pin details of T ransmitter’s Control unit

Fig.9. RT L Schematic of T ransmitter

Fig.12. Pin details of T ransmitter’s Datapath Unit

Fig.10. RT L Schematic of Receiver

Fig. 13. Pin details of transmitter

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 Proceedings of the Fifth International Conference on Communication and Electronics Systems (ICCES 2020)
IEEE Conference Record # 48766; IEEE Xplore ISBN: 978-1-7281-5371-1

VII. CONCLUSION
The obtained result is quite similar to that of the theoretical
approach. In the theoretical approach, the frame consists of
one start bit, followed by 5-7 data bits, one parity bit, and one-
stop bit. Here, the data are transmitted serially in almost the
same fashion but with slightly more complex architecture(s)
and frame format. On the receiver end similar to the
theoretical approach the start bit and stop bit are dropped and
the data is loaded parallelly into the receiver data register. The
microprocessor is more involved in this design than in the
general design. This design is not optimized for low power
Fig.14. RT L Schematic of hamming code decoder
mode or power saving. The testing of the code should be done
using hardware by making use of devices like FPGA. Further,
The following table gives information on cells, nets, I/O there is more involvement of the microprocessor, so there is
ports, LUTs and FFs used in Transmitter and Receiver more load on the microprocessor. This implies that there is a
architecture. Pin details and RTL schematic of the receiver’s need for microprocessors that have higher load handling
datapath and control unit are complicated and thus it’s capabilities or external peripherals that can handle this task.
inclusion in this paper is not desirable, but the details These modifications ensure that the data corruption is less and
regarding the cells, nets, I/O ports, LUTs and FFs are shown that the transmitter side and receiver side can send data and
in TABLE 1. halt the transmission of data if required.

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