Fpga IITK
Fpga IITK
Fpga IITK
FPGA
AVI SINGH
Prerequisites
Digital Circuit Design - Logic Gates, FlipFlops, Counters, Mux-
Demux
Way 2:
module 4029(clk, out, reset, enable);
Way 2:
input clk;
input reset;
input enable;
output [3:0] out;
Types of Ports
We need drivers for this module in order to interact with other
modules
In Verilog, a driver which can store a value is called reg and the one
which cannot is called wire
Drivers for 4029 modules
Ports defined as wires?
◦ clk
◦ reset
◦ enable
Way 2:
wire clk;
wire reset;
wire enable;
reg [3:0] out;
Complete definition of module
module 4029( clk, out, reset, enable);
input wire clk;
input wire reset;
input wire enable;
output reg [3:0] out;
endmodule
Wire Vs Reg
reg can store a value, wire simply connects
Most of the times, inputs are wire and outputs are reg
assign sum = a & ~b & ~cin | ~a & b & ~cin |~a & ~b &
cin | a & b & cin; assign { carry, sum } = a+b+cin;
initial
OUT <= 0;
endmodule
Blocking and Non-blocking
statement
Non-blocking assignments happen in parallel.
always @ ( #sensitivity list # ) begin
B <= A ;
C <= B ; // (A,B) = (1,2) -> (B,C) = (1,2)
end
begin
begin
end
end
endmodule
Xilinx Virtex V
Hobbyist Friendly Boards
Papilio Pro
Mojo v3/v2
How to get started?
First of all download Xilinx ISE WebPack, with a free licence.
Create a simple project, and learn to write test benches (or directly create
them on the ISE), and start using the ISim tool.
Do the ‘Verilog in a Day’ exercises found here
http://www.asic-world.com/
Check if Mojo boards are available in club.
Go here: http://embeddedmicro.com/tutorials/mojo/
See your code in action!