Comms Reviewer
Comms Reviewer
Hartley’s Law
𝑪 ∝ 𝑩×𝑻
A/D Converter - converts analog signal to digital signal C is directly proportional to B
- periodically, sampling the input C = information capacity (bps)
- quantizing B = Bandwidth (Hz)
Source Encoder/Decoder - human observer T = transmission time (s)
- source codec
Channel Encoder - controls the error characteristics of For noiseless condition,
digital channel 𝑪 = 𝒌𝑩 × 𝑻
Channel Decoder - processes the digital signal and 𝑪 = 𝟐𝑩 (maximum theoretical bit capacity)
produces the received bitstream b
Shannon-Hartley Theorem
Digital Communications - high-frequency analog For noisy condition,
carriers are modulated by relatively low-frequency digital 𝑺
𝑪 = 𝑩𝒍𝒐𝒈𝟐 (𝟏 + 𝑵) 𝒅𝑩 = 𝟏𝟎𝒍𝒐𝒈𝟏𝟎 𝑷
information signals (digital radio) and systems involving
𝑺 𝑺
the transmission of digital pulses (digital transmission) 𝑪 = 𝟑. 𝟑𝟐𝑩𝒍𝒐𝒈𝟏𝟎 (𝟏 + 𝑵) 𝑷 = 𝑵 (𝑢𝑛𝑖𝑡𝑙𝑒𝑠𝑠)
e. baud (symbols/s)
𝑓𝑎 = 𝑓𝑏 = 1 𝑘𝐻𝑧
𝐵𝑎𝑢𝑑 = 𝑓𝑏
𝑩𝒂𝒖𝒅 = 𝟏𝟎𝟎𝟎 𝒔𝒚𝒎𝒃𝒐𝒍𝒔/𝒔
FSK Transmitter
- center or carrier frequency is shifted (deviated) by the
binary input data
- Consequently, the output of a BFSK modulator is a step
function in the time domain.
- With BFSK, there is a change in the output frequency
Total Bandwidth each time the logic condition of the binary input signal
𝑻𝒐𝒕𝒂𝒍 𝑩𝑾 = 𝒇𝒎𝒂𝒙 − 𝒇𝒎𝒊𝒏 changes
𝒇𝒎𝒂𝒙 = 𝒇𝒎 + 𝒇𝒃 𝒇𝒎𝒊𝒏 = 𝒇𝒔 − 𝒇𝒃
𝑩𝑾 = 𝟐(∆𝒇 + 𝒇𝒃 ) FSK Receiver
BW = total BW; minimum BW Phase-Locked Loop (PLL)
fmax = maximum frequency - most common circuit used for demodulating BFSK
fmin = minimum frequency signals
- As the input to the PLL shifts between the mark and
Baud space frequencies, the dc error voltage at the output of the
For BFSK, there are only 2 signal frequency shifts use, so, phase follows the frequency shift.
𝑓𝑏 𝑓𝑏
𝑏𝑎𝑢𝑑 = =
𝑙𝑜𝑔2 (2) 1
𝒃𝒂𝒖𝒅 = 𝒇𝒃
VCO - Voltage Controlled Oscillator
Modulation of BFSK
Capture Range - range of input frequencies around the
VCO center frequency onto which the loop can lock when
starting from the unlocked condition.
Example 3
Non-coherent Demodulation Using a Bessel table, determine the minimum bandwidth
for the same FSK signal described in Example 1 with a
mark frequency of 49 kHz, a space frequency of 51 kHz,
and an input bit rate of 2 kbps.
Given:
𝑓𝑚 = 49 𝑘𝐻𝑧 𝑓𝑠 = 51 𝑘𝐻𝑧 𝑓𝑏 = 2 𝑘𝑏𝑝𝑠
Solution:
|𝑓𝑚 − 𝑓𝑠 | |49 − 51|
𝑀𝐼 = = = 1.0 (3 𝑠𝑒𝑡𝑠 𝑜𝑓 𝑠𝑖𝑑𝑒𝑏𝑎𝑛𝑑𝑠)
Example 1 𝑓𝑏 2
Determine (a) the peak frequency deviation, (b) minimum |𝑓𝑚 − 𝑓𝑠 | |49 𝑘𝐻𝑧 − 51 𝑘𝐻𝑧|
bandwidth, and (c) baud for a binary FSK signal with a ∆𝑓 = = = 1 𝑘𝐻𝑧
2 2
mark frequency of 49 kHz, a space frequency of 51 kHz, 𝐵𝑊 = 2 (𝑛𝑜. 𝑜𝑓 𝑠𝑖𝑑𝑒𝑏𝑎𝑛𝑑 × ∆𝑓) = 2 (3 × 1 𝑘𝐻𝑧)
and an input bit rate of 2 kbps. 𝑩𝑾 = 𝟔 𝒌𝑯𝒛
Given:
𝑓𝑚 = 49 𝑘𝐻𝑧 𝑓𝑠 = 51 𝑘𝐻𝑧 𝑓𝑏 = 2 𝑘𝑏𝑝𝑠 Phase Shift Keying (PSK)
Solution: -another form of angle-modulated
(a) the peak frequency deviation -constant-amplitude digital modulation
|𝑓𝑚 − 𝑓𝑠 | |49 𝑘𝐻𝑧 − 51 𝑘𝐻𝑧| -phase of the carrier signal is varied by the digital message
∆𝑓 = = signal
2 2
∆𝒇 = 𝟏 𝒌𝑯𝒛 -input signal is a binary digital signal
-limited number of output phases are possible
(b) minimum bandwidth 𝒗(𝒕) = 𝑽𝒔𝒊𝒏(𝟐𝝅𝒇𝒕 + 𝜽)
𝐵𝑊 = 2(∆𝑓 + 𝑓𝑏 ) = 2(1 𝑘𝐻𝑧 + 2 𝑘𝑏𝑝𝑠)
Modulation of PSK
𝑩𝑾 = 𝟔 𝒌𝑯𝒛
Example 2
For a binary FSK modulator with space, rest, and mark
frequencies of 60, 70, and 80 MHz, respectively, and an BPSK Transmitter
input bit rate of 20 Mbps, determine the modulation index,
output baud, and the minimum required bandwidth.
Given:
𝑓𝑠 = 60 𝑀𝐻𝑧 𝑓𝑚 = 80 𝑀𝐻𝑧
𝑓𝑐 = 70 𝑀𝐻𝑧 𝑓𝑏 = 20 𝑀𝑏𝑝𝑠
Solution:
(a) modulation index
|𝑓𝑚 − 𝑓𝑠 | |80 𝑀𝐻𝑧 − 60 𝑀𝐻𝑧|
𝑀𝐼 = =
𝑓𝑏 20 𝑀𝑏𝑝𝑠 Balanced Modulator - acts like a phase reversing switch
𝑴𝑰 = 𝟏. 𝟎
BPSK Modulation
(b) baud for BFSK Truth Table
𝑏𝑎𝑢𝑑 = 𝑓𝑏 = 20 𝑀𝑏𝑝𝑠
𝒃𝒂𝒖𝒅 = 𝟐𝟎 𝟎𝟎𝟎 𝟎𝟎𝟎 𝒔𝒚𝒎𝒃𝒐𝒍𝒔/𝒔
Phasor Diagram Constellation Diagram
QPSK Transmitter
QPSK Modulation
16-PSK
- N = 4 bits M = 16 possible outputs
8-QAM
- N = 3 bits M = 8 possible outputs 16-QAM
- N = 4 bits M = 16 possible outputs
8-QAM Transmitter
16-QAM Transmitter
Error performance - rate in which errors occur
- expected or an empirical value
Probability 0f Error (P[e]) - theoretical (mathematical)
Bit Error Rate (BER) – actual
Error Detection
Redundancy - form of error detection that duplicates each
data unit for the purpose of detecting errors
- effective but rather costly
Redundancy Checking - adding bits for the sole purpose
of detecting errors
Checksum Creation
1. Break the original message into ‘k’ number of blocks
with ‘n’ number of bits for each block.
2. Sum all the ‘k’ data blocks.
3. Add the carry to the sum, if any.
4. Do 1’s Complement to the sum = Checksum.
Checksum Validation
1. Collect all the data blocks including the checksum
value.
2. Sum all the data blocks and validate the checksum
value.
3. If the resulting value of the validation is all 1’s, data is
ACCEPTED; Else, REJECTED.
Performance of Checksum
The checksum detects all errors involving odd numbers of
bits.
It detects most errors involving an even number of bits.
If one or more bits of a segment are damaged and the
corresponding bit or bits of opposite value in a second
segment are also damaged, the sums of those columns
will not change and the receiver will not detect error(s).
𝑮(𝒙)
= 𝑸(𝒙) + 𝑹(𝒙)
𝑷(𝒙)
G(x) = message data unit / polynomial
P(x) = generator polynomial (divisor)
Q(x) = quotient
R(x) = remainder (CRC code)
2. Determine the center frequency and the peak shift of b. Modulated ASK OFF signal equation
the carrier if it is to be modulated using BFSK with a 𝑉𝑚 = −1 𝑉
modulation index of 1.5, an input bit rate of 2000 bits per 𝐴
second and a maximum frequency of 7500 Hz. Express 𝑉𝑎𝑠𝑘 (𝑡) = [1 + 𝑉𝑚 (𝑡)][ 𝑐𝑜𝑠𝜔𝑐 𝑡]
2
your answer in hertz. 5
𝑉𝑎𝑠𝑘 (𝑡) = [1 + (−1)][ 𝑐𝑜𝑠2𝜋(49 𝑘𝐻𝑧)𝑡]
Given: 2
𝑀𝐼 = 1.5 𝑓𝑏 = 2000 𝑏𝑝𝑠 𝑓𝑚𝑎𝑥 = 7500 𝐻𝑧 𝑽𝒂𝒔𝒌 (𝒕) = 𝟎
Solution: c. Modulation Index
𝑓𝑏 2000 𝑉𝑚𝑎𝑥 − 𝑉𝑚𝑖𝑛 5 − 0
𝑓𝑎 = = = 1000 𝑏𝑝𝑠 𝑀𝐼 = =
2 2 𝑉𝑚𝑎𝑥 + 𝑉𝑚𝑖𝑛 5 + 0
𝑴𝑰 = 𝟏