FUNDAMENTALS OF MECHATRONICS (CUME218) CLASS TEST

ATTEMPT ALL THE QUESTIONS

1. a) Table Q.1 is the memory address decoding table of an MC6809 microprocessor based system. Draw the
corresponding memory map to scale and determine the size of each range and the range of addresses for each
memory and Input/Output device. Synthesize the memory address decoding logic using discrete logic gates: NAND,
NOR, AND, OR and NOT. Which devices are selected by addresses: $D589, $BF3C, $6A14, $970E? [20]

b) Draw the circuit diagram of an FPGA which will implement the memory address decoding more compactly. [5]

Table Q.1 Memory Address Decoding Table A

A15 A14 A13 A12 A11 DEVICE
0 X X X X RAM B
1 0 0 0 X ACIA
1 0 0 1 0 PIA_0
C
1 0 0 1 1 PIA_1 D
1 0 1 X X EEPROM
1 1 X X X EPROM Figure Q.2 Received Frames

2.a) A serial link is using 9600 bits per second for the transfer of a large binary file at 8 bits per character, even parity and
1 stop bit. Draw timing diagrams on both the TTL side and the RS232 side for the transfer of the two bytes: $B6 and
$7D. Determine the maximum byte transfer rate and the link utilization efficiency. [10]

b) For the byte character frames in Figure Q.2, which use the same serial configuration, determine the types of errors in
the frames. For the error free frames determine the received bytes. [8]

c) Draw the diagram of two JZ881 radio transceivers which are being used on the serial link and clearly state the
advantages of using the radio module compared to wired transmission. [4]

d) Draw clear separate diagrams which show the use of XON and XOFF and also the use of hardware handshake
signals to control the flow of data from a fast data sender to a slow data receiver. [3]

3 a) An MC68HC11 microcontroller is driven by a 4.9152 MHz crystal. The configuration register BAUD is initialised
with the byte $24 after hardware RESET. Calculate the baud rate used by the SCI subsystem. [4]

b) The MC6809 microprocessor has the following processor state:

PC: C980, IX: 9000 IY: 3000 SP: 8000 US: 7000 DPR: 00 ACCA: 41

ACCB: 1A CCR: 96

The following stack operations then take place in the indicated order:

(i) PSHS A,Y (ii) PSHU B,X (iii) PSHS C,P,U (iv) PSHU D,S

(v) PULS A,X (vii) PULU C (viii) PULS D (ix) PULU B,Y

1
 Draw two memory fragment diagrams showing the states of the Hardware Stack and the User Stack after the first
four push operations. Write down the processor state after the execution of the remaining four pull operations. An
IRQ interrupt then takes place. Draw the diagram of the hardware stack after control has been passed to the IRQ
interrupt service routine. [12]

PUSH/PULL POSTBYTE

PC SP/US IY IX DPR ACCB ACCA CCR

b) Express the two decimal numbers: 2387 and 9145 in Binary Coded Decimal (BCD) form and explain showing all the
steps how the two decimal numbers can be added together on a two’s complement processor. [5]

c) The objective is to save on I/O pins of the MC68HC11 microcontroller. Draw a diagram which shows how four
general purpose I/O port pins can be used to interface to an LCD matrix display using an 8-bit bus with the use of an
external 74LS374 chip operating as a shift register. (Two of the pins simulate part of the SPI interface in software)
The LCD R/W signal permanently grounded. Describe the programming required to send commands and data to the
LCD matrix display. See the pin configuration of the 74LS3734 chip shown below. [4]

4 a) Listing Q.4 shows an MC6809 assembly language program. Assemble the program by hand into machine code using
the listing format used by most assemblers . Write down the Intel hex format and Motorola S format records and the
corresponding end of file (EOF) records. [25]

ACIA1 EQU 4000

ACIA1_RDR EQU ACIA1
ACIA1_TDR EQU ACIA1
ACIA1_STATUS EQU ACIA1 + 1
ACIA2 EQU 4800
ACIA2_RDR EQU ACIA2
ACIA2_TDR EQU ACIA2
ACIA2_STATUS EQU ACIA2 + 1
ACIA_RDRF EQU $08
ACIA_TDRE EQU $10

; Acts as a serial bridge between two serial devices

ORG $D800
SERIAL_BRIDGE LDB ACIA1_STATUS

BITB #ACIA_RDRF

BEQ CHECK_ACIA2

SEND_TO_ACIA2 LDA ACIA1_RDR

WAIT2 LDB ACIA2_STATUS

BITB #ACIA_TDRE

BEQ WAIT2

STA ACIA2_TDR

2
 CHECK_ACIA2 LDB ACIA2_STATUS

BITB #ACIA_RDRF

BEQ SERIAL_BRIDGE

SEND_TO_ACIA1 LDA ACIA2_RDR

WAIT1 LDB ACIA1_STATUS

BITB #ACIA_TDRE

BEQ WAIT1

STA ACIA1_TDR

BRA SERIAL_BRIDGE

Listing Q.4

BAUD $102B

TCLR SCP2 SCP1 SCP0 RCKB SCR2 SCR1 SCR0

SCI PRESCALE FACTOR (P) SCI RATE SELECT FACTOR (R)

E/16 divided by prescale factor (P) PRESCALER output divided by rate factor (R)

SCP2 SCP1 SCP0 Factor SCR2 SCR1 SCR0 Factor

X 0 0 1 0 0 0 1

0 0 1 3 0 0 1 2

X 1 0 4 0 1 0 4
X 1 1 13 0 1 1 8

1 0 1 9 1 0 0 16

1 0 1 32
1 1 0 64

1 1 1 128