NXP Semiconductors Document Number: B4860

Data Sheet: Technical Data Rev. 4, 08/2017

B4860
B4860 QorIQ Qonverge Data
Sheet FC-PBGA–1020
33 mm x 33 mm

This B4860 QorIQ Qonverge chip is a NXP high-end of order transactions with prioritization and bandwidth
heterogeneous multicore SoC based on StarCore, Power allocation amongst CoreNet endpoints.
Architecture®, CoreNet, MAPLE, and DPAA technologies. • Data Path Acceleration Architecture, which includes:
The chip targets the emerging broadband wireless – Frame Manager (FMan), which supports in-line packet
infrastructure and builds upon the proven success of NXP’s parsing and general classification to enable policing and
existing multicore DSPs and CPUs. It is designed to bolster QoS-based packet distribution
the rapidly changing and expanding wireless base station – Queue Manager (QMan) and Buffer Manager (BMan),
markets, such as 3G-LTE (FDD and TDD), LTE-Advanced, which allow offloading of queue management, task
TD-SCDMA, GSM and WCDMA. management, load distribution, flow ordering, buffer
management, and allocation tasks from the cores
This chip can be used for combined control, data path, and
– Security engine (SEC 5.3)—crypto-acceleration for
application layer processing in base stations and in
protocols such as IPsec, SSL and 802.16
general-purpose embedded computing systems. Its high level
• Large internal cache memory with snooping and stashing
of integration offers performance benefits compared to
capabilities for bandwidth saving and high utilization of
multiple discrete devices, while also simplifying board
processor elements. The 9856 KB internal memory space
design.This chip includes these functions and features:
includes the following:
• Six fully-programmable StarCore SC3900 FVP core – 32 KB L1 ICache per e6500/SC3900 core
subsystems, divided into three clusters—each core runs up – 32 KB L1 DCache per e6500/SC3900 core
to 1.2 GHz, with an architecture highly optimized for – 2048 KB unified L2 cache for each SC3900 FVP cluster
wireless base station applications – 2048 KB unified L2 cache for e6500 cluster
• Four dual-thread e6500 Power Architecture processors – Two 512 KB shared L3 CoreNet platform caches (CPC)
organized in one cluster—each core runs up to 1.6 GHz • Sixteen 10 Gbps SerDes lanes serving:
• Two 64-bits DDR3/3L controllers for high-speed, – Two Serial RapidIO controllers each with four lanes
industry-standard memory interfaces running up to running at up to 5 GT/s
1866 MT/s – Eight lanes common public radio interface (CPRI V4.2)
• MAPLE-B3 hardware acceleration—for forward error controller for glueless antenna connection running at up
correction schemes including Turbo or Viterbi decoding, to 9.8 GT/s
Turbo encoding and rate matching, MIMO MMSE – Two 10 GT/s Ethernet controllers (10GbE) for network
equalization scheme, matrix operations, CRC insertion and communications
check, DFT/iDFT and FFT/iFFT calculations, – Six 1 GT/s/2.5 GT/s Ethernet controllers for network
PUSCH/PDSCH acceleration, and UMTS chip rate communications
acceleration – Four lanes PCI Express controller running at up to
• CoreNet fabric supports coherency using MESI protocol 5 GT/s
between the e6500 cores, SC3900 FVP cores, memories – Eight2.5 GT/s/3.125 GT/s/5 GT/s Debug (Aurora)
and external interfaces. CoreNet fabric interconnect runs at • Two OCeaN DMAs
up to 667 MHz and supports coherent and non-coherent out • Various system peripherals
• 118 32-bit timers

NXP reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.

© 2015-2017 NXP B.V.

 Table of Contents
1 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2.18 I2C interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
1.1 1020 FC-PBGA ball layout diagrams . . . . . . . . . . . . . . .3 2.19 GPIO interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
1.2 Pinout list by bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.20 Timers interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
1.3 Pinout list by package pin number . . . . . . . . . . . . . . . .47 2.21 Asynchronous signal timing. . . . . . . . . . . . . . . . . . . . 101
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.22 CPRI interface signals . . . . . . . . . . . . . . . . . . . . . . . . 101
2.1 Overall DC electrical characteristics . . . . . . . . . . . . . . .62 2.23 High-speed serial interfaces (HSSI) . . . . . . . . . . . . . 102
2.2 Power sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 3 Hardware design considerations . . . . . . . . . . . . . . . . . . . . . 141
2.3 Power-down requirements . . . . . . . . . . . . . . . . . . . . . .69 3.1 System clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
2.4 Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .70 3.2 Power supply design . . . . . . . . . . . . . . . . . . . . . . . . . 145
2.5 Power-on ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . .70 3.3 Decoupling recommendations . . . . . . . . . . . . . . . . . . 150
2.6 Input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 3.4 SerDes block power supply decoupling
2.7 RESET initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .73 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.8 DDR3 and DDR3L SDRAM controller. . . . . . . . . . . . . .74 3.5 Connection recommendations for unused pins . . . . . 150
2.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . .80 3.6 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
2.10 eSPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 3.7 Thermal management information. . . . . . . . . . . . . . . 159
2.11 DUART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 3.8 Temperature diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 161
2.12 Ethernet interface, Ethernet management interface 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
1 and 2, IEEE Std 1588™. . . . . . . . . . . . . . . . . . . . . . .83 4.1 Package parameters for the FC-PBGA . . . . . . . . . . . 161
2.13 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 4.2 Mechanical dimensions of the B4860 FC-PBGA. . . . 162
2.14 Integrated flash controller . . . . . . . . . . . . . . . . . . . . . . .90 5 Security fuse processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
2.15 Enhanced secure digital host controller (eSDHC) . . . .92 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
2.16 Multicore programmable interrupt controller 6.1 Part numbering nomenclature . . . . . . . . . . . . . . . . . . 163
(MPIC) specifications . . . . . . . . . . . . . . . . . . . . . . . . . .94 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
2.17 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

B4860 QorIQ Qonverge Data Sheet, Rev. 4

2 NXP Semiconductors
 Pin assignments

This figure shows the major functional units of the chip.

Power Architecture Power Architecture

e6500 e6500
dual-thread core dual-thread core
StarCore StarCore 32 KB 32 KB 64-bit 64-bit
Sc3900 FCP core Sc3900 FVP core
Starcore 32 KB I-Cache
32 KB 32 KB I-Cache
32 KB DDR3/3L DDR3/3L
32 KB Sc3900 StarcoreFVP32 KB
core L1 D-cache L1 I-cache L1 D-cache L1 I-cache memory memory
32 KB I-Cache
32 KB 32 Sc3900
KB 32 I-Cache
32core
KB KB 32 KB 2048 KB controller controller
FVP L2 Cache
32I-Cache
KB 32L1
L1 D-cache 32I-Cache
KBI-cache32L1KB KB 32L1
D-cache KBI-cache Power Architecture Power Architecture
I-Cache
L1KB
32 I-Cache L1
32 I-Cache
D-Cache
KB L1KB
32 I-Cache e6500 e6500
2048 KB dual-thread core dual-thread core 512-KB 512-KB
L1 I-CacheL1 D-Cache
L2 cache
L1 I-Cache 32 KB 32 KB
32 KB I-Cache
32 KB 32 KB I-Cache
32 KB L3/M3 cache L3/M3 cache
L1 D-cache L1 I-cache L1 D-cache L1 I-cache

CoreNet
Coherency fabric

Security
MAPLE-B3 Frame Manager (FMan) monitor
USB Test
baseband Parse, classify, distribute QMan
port/
accelerator DMA DMA Power mgmt
RapidIO Message

SAP

Debug (Aurora)
Manager (RMan)

2x EQPE2
1588™ support OpenPIC
eSDHC
2x DEPE BMan Pre eSPI
2.5G/ 2.5/ boot
2x eTVPE2 1Gbs 1Gbps OCeaN
IFC loader 44 GPIO
8x eFTPE 2.5/ 2.5/ sRIO PCIE
10Gbps 1Gbps 4x I2C
2x PUPE2 1Gbps sRIO SEC
5.3 2x DUART
2x PDPE2 2.5/ 2.5/
10Gbps 1Gbps 1Gbps
1x CRPE Clocks/Reset
1x TCPE
Timers
x1
x1

x1

x4

x4

x4

x8
x1
x4/x1

x1
x1
x4/x1

CPRI B4860
x8

16-lane 10-Gbps SerDes

Figure 1. Block diagram

1 Pin assignments
1.1 1020 FC-PBGA ball layout diagrams
These figures show the B4860 FC-PBGA ball map.

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 3
Pin assignments

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND AVDD_ SGND SD2_ SD2_ SGND SD2_ SD2_ SGND SD2_ SD2_ SGND SD2_ SD2_ SD2_ SGND SD1_ SD1_ SGND SD1_ SGND SD1_ SGND SD1_ SD1_ SGND SD1_
A SGND SD1_ SGND
[A2] CGA1 [A4] RX7 RX6 [A7] RX5 RX4 [A10] RX3 RX2 [A13] REF1_ [A15] RX1 RX0 [A18] RX0 RX1 [A21] REF1_ [A23] RX2 [A23] RX3 RX4 [A28] RX5 RX6 [A31]
A
CLK_B CLK_B

AVDD_ AVDD_ SD2_ SD2_ SD2_ SD2_ SGND SD2_ SD2_ SGND SD2_ SD2_ SD1_ SD1_ SGND SD1_
B GND SGND SGND SGND SD2_ SGND SD1_ SGND SGND SD1_ SD1_ SGND SD1_ SD1_ SGND NC_ B
CGB1 PLAT RX7_B RX6_B RX5_B RX4_B [B10] RX3_B RX2_B [B13] REF1_ RX0_B RX1_B REF1_ [B23] RX3_B
[B1] [B4] [B7] CLK [B15] RX1_B [B18] RX0_B [B21] CLK [B23] RX2_B RX4_B [B28] RX5_B RX6_B [B31] DET

AVDD_ GND AVDD_ SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SD1_ SD1_
C CGA2 [C2] CGB2 [C13] [C15] [C23] [C24] [C25] [C26] RX7_B RX7
C
[C4] [C5] [C6] [C7] C8] [C9] [C10] [C11] [C12] [C14 [C16] [C17] [C18] [C19] [C20] [C21] [C22] [C27] [C28] [C29] [C30]

NC_ SGND SD2_ SD2_ SD2_ SD2_ SD2_ SD2_ SD2_ SD1_ SD1_ SD1_ SD1_
D GND GND XGND XGND SD1_
SD2_ XGND XGND SD2_ XGND SD1_ SD1_ XGND SD1_ SD1_ XGND XGND XGND SGND SGND
[D1] D2 [D3] [D4]
REF2_ [D6] TX7 TX6 [D9] TX5 TX4 [D12] TX3 TX2 [D15] TX1 TX0 [D18] TX0 TX1 [D21] TX2 TX3 [D24] TX4 TX5 [D27] TX6 TX7 [D30] [D31]
D
CLK_B TX5 [D32]
PO QVDD SD2_ SD1_ SD1_ SD1_
NC_ SGND XGND SD2_ SD2_ XGND SD1_
SD2_ SD2_ XGND SD2_ SD2_ XGND SD2_ SD2_ XGND SD1_ SD1_ XGND SD1_ SD1_ SD1_ XGND SD1_ SD1_ XGND
E RESET_ E3 [E5] REF2_ [E6] TX7_B TX6_B [E9] TX4_B [E12] TX3_B TX2_B [E15] TX1_B TX0_B TX0_B TX1_B [E18]
XGND
TX4_B TX5_B [E27] TX6_B TX7_B [E30] REF2_ REF2_ E
[E2] CLK TX5
TX5_B [E18] TX2_B TX3_B [E24] CLK CLK_B
B
QVDD GND NC SGND SGND SGND SGND XVDD SGND SGND XVDD SGND SGND XVDD SGND XVDD XGND XVDD SGND XVDD SGND SGND XVDD SGND SGND XVDD SGND SGND XVDD SGND SGND
F SYSCLK [F3] [F4] [F6] [F7] [F9] [F12] [F15]
DD
[F17] [F18] [F19] [F20] [F21] [F22] [F23] [F24] [F25] [F26] [F27] [F28] [F29] [F30] [F31] [F32] F
[F2] [F5] [F8] [F10] [F11] [F13] [F14] [F16]

SD1_
GND D1_ D1_ D1_ NC_ GND GND GND SD1_
SGND SD2_IMP_ SGND SGND NC_ AGND_
SGND NC_ SGND SD2_ SGND SD1_ SGND NC_ SGND AGND_ NC_ SGND NC_G28
NC_ D2_ D2_ D2_ GND
G [G1] MDQ59 MDQ56 MDQ58 G5 [G6] [G7] [G8] TX5 [G11] [G12] G13 SRDS2_ G16 [G17] IMP_CAL [G19] IMP_CAL [G21] G22 [G21] SRDS1_ G25 IMP_CAL
[G27] G28 MDQ58 MDQ56 MDQ59 [G32] G
[G9] CAL_TX [G15] _RX _RX _TX
PLL2 PLL2

H D1_ D1_ D1_

MDQ51 MDQ52 MDQ55
GND
[H4]
D1_ D1_
MDQ60 MDQ63
SEE DETAIL A
NC_
H7
GND
[H8]
QVDD
[H9]
SGND
[H10]
POVDD
SGND
[H12]
SGND AVDD_
[H13] SRDS2_
NC_
H15
NC_
H16
AVDD_ AGND_
SRDS2_ SRDS2_
PLL1 PLL1
SGND
[H19]
AGND_ AVDD_
SRDS1_ SRDS1_
PLL1 PLL1
NC_
H22
NC_
H23
AVDD_ SGND
SRDS1_ [H25]
SGND
[H26]
D2_ D2_
MDQ63 MDQ60
GND
[H29]
D2_
MDQ55
D2_ D2_
MDQ52 MDQ51 H
PLL2 PLL2

J
D1_ D1_ D1_ D1_
MDQS6 MDQS6 MDM6 MDQS7
D1_
MDQS7
GND
[J6]
TD_
[J7]
ANODE
TD_
[J8]
CATHODE
SENSE-
GND1
VDD
[J10]
GND
[J11]
VDD
[J12]
GND
[J13]
SGND
[J14]
SGND
[J15]
SGND
[J16]
SGND
[J17]
SGND
[J18]
SGND
[J19]
SGND
[J20]
SGND
[J21]
SGNDSEE DETAIL B
[J22]
SGND
[J23]
SGND
[J24]
GND
[J25]
TH_
VDD
GND
[J27]
D2_ D2_
MDQS7 MDQS7
D2_
MDM6
D2_ D2_
MDQS6 MDQS6 J
_B _B _B _B
D1_ D1_ D1_ D1_ D1_ D1_ D1_ SENSE-
SD1_ VDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD GND D2_ D2_ D2_ D2_ D2_ D2_ GND D2_
K GND GND VDD GND GND SVDD SVDD
MDQ50 [K2] MDQ53 MDQ54 MDM7 MDQ57 MDQ61 MODT1 VDD1
TX5 [K10] [K11] [K12] [K13] [K14] [K15] [K17] [K18] [K18] [K20] [K21] [K22] [K23] [K24] MODT1 MDQ61 MDQ57 MDM7 MDQ54 MDQ53 [G32] MDQ50 K
[K16]

D1_ D1_ D1_ GND D1_ D1_ D1_ G1VDD D1_ VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND D2_ D2_ D2_ D2_ GND D2_ D2_ D2_
L MDQ48 MDQ49 MDQ43 [L4] MDQ47 MDQ45 MDQ62 [L8] MCS3 [L10] [L11] [L12] [L13] [L14] [L15] [L17] [L18] [L19] [L20] [L21] [L22] [L23] MCS3
G2VDD
MDQ62 MDQ45 MDQ47 [L29] MDQ43 MDQ49 MDQ48 L
[L16]
_B _B
D1_ D1_ D1_ D1_ D1_ D1_ D1_ VDD VDD VDD VDD VDD VDD VDD D2_ D2_ D2_ D2_ D2_ D2_ D2_
M GND GND GND GND GND GND GND GND GND GND GND
MDQ35 MDQ34 MDQ37 MDQ41 MDQ42 [M6] MODT0 MODT3 [M9] [M10] [M11] [M12] [M13] [M14] [M15] [M16] [M17] [M18] [M19] [M20] [M21] [M22] [M23] [M24] MODT3 MODT0 [M27] MDQ42 MDQ41 MDQ37 MDQ34 MDQ35 M

D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ VDD VDD VDD D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
GND VDD GND VDD GND VDD GND VDD GND GND GND GND GND
N MDQ33 [N2] MDM4 MDQS5 MDQS5 MDM5 MWE_ MODT2 MA13 [N10] [N11] [N12] [N13] [N14] [N15] [N17] [N18] [N19] [N20] [N21] [N22] [N23] MA13 MODT2 MWE_ MDM5 MDQS5 MDQS5 MDM4 [N31] MDQ33 N
_B [N16] _B
B B
D1_ D1_ D1_ D1_ D1_ D1_ D1_ GND VDD VDD D2_ D2_ D2_ D2_ D2_ D2_ D2_
GND G1VDD G1V VDD GND VDD GND VDD GND GND GND VDD GND VDD G2VDD GND
P MDQS4 MDQS4 MDQ39 [P4] MDQ40 MDQ46 [P7] MRAS MCS1_
DD
[P10]
[P10] [P11] [P12] [P13] [P14] [P15] [P16] [P17] [P18] [P19] [P20] [P21] [P22] [P23] MCS1_ MRAS [P26] MDQ46 MDQ40 [P29] MDQ39 MDQS4 MDQS4 P
_B _B B B _B _B

D1_ D1_ D1_ D1_ D1_ D1_ VDD VDD VDD VDD G2VDD D2_ D2_ D2_ D2_ D2_ D2_
GND GND G1VDD GND VDD GND VDD GND VDD GND GND GND GND GND GND
R MDQ32 [R2] MDQ36 MDQ38 MDQ44 [R6] MCS2 MCAS
[R9] [R10] [R11] [R12] [R14] [R15] [R16] [R17] [R18] [R19] [R20] [R21] [R22] [R23] [R24] MCAS_ MCS2_ [R27] MDQ44 MDQ38 MDQ36 [R31] MDQ32 R
_B _B [R13] B
B
D1_ D1_ D2_ D2_
D1_ D1_ D1_ D1_ D2_ D2_ D2_ D2_ D2_ D2_
T G1VDD MAPAR_ D1_ D1_
MCS0
G1VDD VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND G2VDD
MCS0 MAPAR G2VDD
T
[T1] MA05 ERR_B MA02 MBA1 MA01 MAPAR MBA0 [T10] [T11] [T12] [T13] [T14] [T15] [T16] [T17] [T18] [T19] [T20] [T21] [T22] [T23] MBA0 MAPAR MA01 MBA1 MA02 ERR_B MA05 [T32]
_OUT _B _B _OUT
D1_ D1_ D1_ D1_ D2_ D2_ D2_ D2_
D1_ G1VDD D1_ G1VDD G1VDD GND GND VDD GND VDD VDD GND VDD GND VDD GND VDD GND G2VDD G2VDD D2_ G2VDD D2_
U MCK2 MCK3 MA00 MA10 GND MA10 MA00 U
MCK2 [U3] MCK3 [U6] [U9] [U10] [U11] [U12] [U13] [U14] [U15] [U16] [U17] [U18] [U19] [U20] [U21] [U22] [U23] [U24] [U27] MCK3_ MCK3 [U30] MCK2_ MCK2
_B _B B B
D1_ D1_ D1_ D1_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
MCK0 G1VDD G1VDD D1_ D1_ D1_ G1VDD VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND G2VDD G2VDD G2VDD
V MCK0
_B [V3]
MCK1 MCK1
[V6] MDIC1 MA04 MA03 [V10] [V11] [V12] [V13] [V14] [V15] [V16] [V17] [V18] [V19] [V20] [V21] [V22] [V23] MA03 MA04 MDIC1 [V27] MCK1 MCK1 [V30] MCK0 MCK0 V
_B _B _B

G1VDD D1_ D1_ D1_ D1_ D1_ D1_ D1_ G1VDD GND GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND G2VDD D2_ D2_ D2_ D2_ D2_ D2_ D2_ G2VDD
W [W1] MDIC0 MA08 MA06 MA07 MA09 MA12 MA11 [W9] [W10] [W11] [W12] [W13] [W14] [W15] [W16] [W17] [W18] [W19] [W20] [W21] [W22] [W23] [W24] MA11 MA12 MA09 MA07 MA06 MA08 MDIC0 [W32]
W

D1_ GND D1_ GND D1_ D1_ G1VDD D1_ D1_ G1VDD VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND G2VDD D2_ D2_ G2VDD D2_ D2_ GND D2_ GND D2_
Y MECC3 [Y2] MECC7 [Y4] MECC0 MCKE3 [Y7] MCKE2 MA15 [Y10] [Y11] [Y12] [Y13] [Y14] [Y15] [Y16] [Y17] [Y18] [Y19] [Y20] [Y21] [Y22] [Y23] MA15 MCKE2 [Y26] MCKE3 MECC0 [Y29] MECC7 [Y31] MECC3 Y
D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ G1VDD G2VDD D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD
AA MDQS8_ MDQS8 MECC6 MDQ30 MDM3 MBA2 MCKE0 MCKE1 MA14 [AA10] [AA11] [AA12] [AA13] [AA15] [AA16] [AA17] [AA18] [AA19] [AA21] [AA22] [AA23] MA14 MCKE1 MCKE0 MBA2 MDM3 MDQ30 MECC6 MDQS8 MDQS8_ AA
B [AA14] [AA20]
B
D1_ GND D1_ D1_ GND D1_ D1_ GND GND GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND GND GND GND D2_ D2_ GND D2_ D2_ GND D2_
AB MDM8 [AB2] MECC2 MDQ29 [AB5] MDQ27 MDQ26 [AB8] [AB9] [AB10]
[AB10] [AB11] [AB12] [AB13] [AB14] [AB16] [AB17] [AB18] [AB19] [AB20] [AB22] [AB23] [AB24] [AB25] MDQ26 MDQ27 [AB28] MDQ29 MECC2 [AB31] MDM8 AB
[AB15] [AB21]
D1_ D1_ D2_
D1_ D1_ D1_ D1_ GND AVDD_ GND GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND M2VREF AVDD_ GND D2_ D2_ D2_ D2_ D2_
AC MDQS3 MDQS3 M1VREF [AC10] MDQS3 MDQS3 MDQ31 MECC1 MECC4 MECC5 AC
MECC5 MECC4 MECC1 MDQ31 _B DDR2 [AC26]

D1_ D1_ D1_ D1_ D1_

SEE DETAIL C
D1_
[AC7] DDR1 [AC11] [AC12] [AC13] [AC14] [AC15] [AC16] [AC17] [AC18] [AC19] [AC20]

D2_
[AC21] [AC22] [AC23]

SEE DETAIL D D2_ D2_ D2_

_B
D2_ D2_ D2_
AD GND GND GND NC_ SENSE- D1_ OVDD GND OVDD GND OVDD GND DVDD GND GND NC_ GND GND GND
AD
MDM2 MDQ19 MDQ22 [AD4] MDQ28 MDQ24 MDQ25 [AD8] [AD9] AD10 GND2 DDRCLK [AD13] [AD14] [AD15] [AD16] [AD17] [AD18] [AD19] [AD20] DDRCLK [AD22] AD23 [AD24] [AD25] MDQ25 MDQ24 MDQ28 [AD29] MDQ22 MDQ19 MDM2

D1_ D1_ D1_ D1_ D1_ D1_ TSEC_ TSEC_ D2_ D2_ D2_ D2_
GND IIC2_ UART1_ IIC4_ D2_ D2_
AE 1588_ EVT0 EVT1 SENSE- GND OVDD GND OVDD GND OVDD GND DVDD GND GND GND
AE
MDQ21 [AE2] MDQ23 MDQS0 MDQS0 MDQ04 MDQ01 CLK_OUT1588_TRIG _B SDA MDQ01 MDQ04 MDQS0 MDQS0 MDQ23 [AE31] MDQ21
_B _IN1 _B VDD2 [AE13] [AE14] [AE15] [AE16] [AE17] [AE18] [AE19] [AE20] [AE21] [AE22] SCL CTS_B
_B
D1_ D1_ D1_ D1_ D1_ D1_ TSEC_ TSEC_ TMP_ SDHC_ D2_ D2_ D2_
GND USB_ 1588_ 1588_TRIG CP_ UART2_ D2_ D2_ D2_
AF MDQS2 MDQS2
EVT4 IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_
DETECT IRQ01 IRQ00 UART1_ GND AF
MDQ16 MDQ03 [AF5] MDQ06 MDQ00 D0 PULSE_ _IN2 SYNC1 _B AD02 AD08 AD09 AD10 AD12 AD13 AD03 DAT3 RTS_B SOUT MDQ00 MDQ06 [AF28] MDQ03 MDQ16 MDQS2 MDQS2
_B OUT1 _B _B
D1_ D1_ D1_ D1_ D1_ D1_ TSEC_ IIC2_ D2_ D2_
USB_ GND CP_ GND IFC_ IFC_ GND IFC_ IFC_ GND IFC_ IFC_ GND SPI_ SDHC_ GND UART2_ GND D2_ D2_ D2_ D2_
AG MDQ20 MDQ18 MDQ17 MDM0 MDQ05 MDQ02 D1 [AG8]
1588_
ALARM_ SYNC2 [AG11] AD00 AD01 [AG14] A16 [AG17] A15 A21 [AG20] [AG20] SDA RTS_B [AG26] MDQ02 MDQ05 MDM0 MDQ17 MDQ18 MDQ20 AG
OUT1
A18 CLK DAT0

D1_ D1_ D1_ D1_ TSEC_

GND USB_ USB_ 1588_ CP_ CP_ EVT2 IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ SPI_ SDHC_ IIC1_ UART2_ IIC1_ D2_ D2_ D2_ GND D2_
AH MDM1 [AH2] MDQ13 MDQ08 MDQ07 STP D2 ALARM_ SYNC7 SYNC3 _B A24 PAR0 A17 AD04 AD11 A20 AD19 AD14
IRQ02 IRQ03 IRQ04
SDA SIN SCL MDQ07 MDQ08 MDQ13 [AH31] MDM1 AH
OUT2 CS2_B DAT1

D1_ D1_ D1_ D1_ GND USB_ GND EMI2_ CP_ GND EVT3 IFC_ GND IFC_ IFC_ GND IFC_ IFC_ GND IFC_ SPI_ GND IRQ_ GND EMI1_ IIC4_ GND D2_ D2_ D2_ D2_
AJ MDQ11 MDQ14 MDQ12 MDQ09 [AJ5] D3 [AJ7] MDIO SYNC0 [AJ9] _B PAR1 [AJ12] A25 A26 [AJ12] A27 CS3_B [AJ19] A22 CS0_B [AJ22] OUT_B
IRQ10
[AJ25] MDC SCL [AJ28] MDQ09 MDQ12 MDQ14 MDQ11 AJ

D1_ D1_ D1_ USB_ USB_ USB_

TSEC_
1588_ CP_ CP_ CKSTP_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ SPI_ SDHC_ TRST EMI1_ CP_ UART2_ IIC3_ D2_ D2_ D2_
AK MDQS1 MDQS1 MDQ10 D7 D4 D5 PULSE_ SYNC5 SYNC6 ASLEEP OUT_ WE_0 CS1_B CS2_B CS0_B OE_B A23 AD07 CS1_B CMD
IRQ06 IRQ08 IRQ05 IRQ07
_B _
MDIO LOS1 CTS_B SDA MDQ10 MDQS1 MDQS1 AK
_B OUT2 B _B _B

GND D1_ GND USB_ USB_ GND DMA1_ CP_ GND CP_ CP_ GND IFC_ IFC_ GND IFC_ IFC_ GND IFC_ SPI_ GND SDHC_ GND CP_ UART1_ GND D2_ GND
IRQ11 GND AL
AL [AL1] MDQ15 [AL3] CLK NXT [AL6] DACK0 SYNC4 [AL9] RCLK0 RCLK1 [AL12] AD05 WP0_B [AL15] BCTL AD06 [AL18] AVD MISO [AL21] DAT2 [AL24] TDO TCK
[AL27] LOS3 SOUT [AL30] MDQ15 [AL32]
_B
TSEC_ DMA1_ DMA1_
GND 1588_ USB_ USB_ EMI2_ RESET_ CP_ CP_ HRESET IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ SPI_ SPI_ SDHC_ CP_ UART1_ CP_ IIC3_ GND
AM DREQ0 DDONE0 MDC REQ_B RCLK0_B RCLK1_B _B CLK_OUT CLE RTC IRQ09 TMS TDI AM
[AM2] CLK_IN D6 DIR RB0_B TE RB1_ B CLK0 CLK1 CS3_B MOSI CLK LOS2 SIN LOS0 SCL [AM31]
_B _B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Signal groups

QVDD AVDD_ SENSE-

OVDD I/O supply voltage I/O supply voltage SRDSn SerDes n PLL supply voltage VDD1 Core group 1 voltage sense GND Ground

GnVDD AVDD_ SENSE-

SVDD SerDes core power supply DDR1/DDR2 I/O supply Platform PLL supply voltage VDD2 Core group 2 voltage sense SGND SerDes core ground supply
PLAT

POVDD AVDD_
XVDD SerDes transmitter pad supply Fuse I/O supply Core group x, n supply voltage XGND SerDes transceivers ground
CGxn

DVDD AVDD_ DDR n PLL supply voltage

I/O supply voltage DDRn

Figure 2. 1020 BGA ball map diagram (top view)

B4860 QorIQ Qonverge Data Sheet, Rev. 4

4 NXP Semiconductors
 Pin assignments

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GND AVDD_ SGND SD2_ SD2_ SGND SD2_ SD2_ SGND SD2_ SD2_ SGND SD2_ SGND SD2_
A [A2] CGA1 RX5 [A10] REF1_
[A4] RX7 RX6 [A7] RX4 RX3 RX2 [A13] CLK_B [A15] RX1

AVDD_ AVDD_ SGND SD2_ SD2_ SGND SD2_ SD2_ SGND SD2_ SD2_ SGND SD2_ SGND SD2_
B GND
[B1] CGB1 PLAT [B4] RX7_B RX6_B [B7] RX5_B RX4_B [B10] RX3_B RX2_B [B13] REF1_ [B15] RX1_B
CLK

AVDD_ GND AVDD_ SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND
C CGA2 CGB2
[C2] [C4] [C5] [C6] [C7] C8] [C9] [C10] [C11] [C12] [C13] [C14 [C15] [C16]

NC_ SD2_ SD2_ SD2_ SD2_ SD2_ SD2_ SD2_

D GND GND SGND XGND XGND SD1_
SD2_ XGND XGND
[D1] D2 [D3] REF2_ [D6] TX7 TX6 [D9] TX4 [D12] TX3 TX2 [D15] TX1
[D4] CLK_B TX5
TX5
PO QVDD SD2_
E NC_ SGND XGND SD2_ SD2_ XGND SD1_
SD2_ SD2_ XGND SD2_ SD2_ XGND SD2_
RESET_ E3 REF2_ [E6] [E12] TX1_B
[E2] [E5] TX7_B TX6_B [E9] TX5
TX5_B TX4_B TX3_B TX2_B [E15]
B CLK

QVDD GND NC_ SGND SGND SGND SGND XVDD SGND SGND XVDD SGND SGND XVDD SGND
F SYSCLK [F3]
[F2] F4 [F5] [F6] [F7] [F8] [F9] [F10] [F11] [F12] [F13] [F14] [F15] [F16]

D1_ D1_ D1_ NC_ GND GND GND SD1_ SGND SGND NC_ AGND_
G GND SGND SD2_IMP_ SGND NC_
[G1] MDQ59 MDQ56 MDQ58 G5 [G6] [G7] [G8] TX5 [G11] [G12] G13 SRDS2_ G16
[G9] CAL_TX [G15]
PLL2

H D1_ D1_ D1_ GND D1_ D1_ NC_ GND QVDD SGND SGND SGND AVDD_ NC_ NC_
POVDD
MDQ51 MDQ52 MDQ55 [H4] MDQ60 MDQ63 H7 [H8] [H9] [H10] [H12] [H13] SRDS2_ H15 H16
PLL2
D1_ D1_ D1_ D1_ TD_
GND GND GND
J D1_ GND NC_ TD_ NC_ SENSE- VDD VDD GND SGND SGND SGND
MDQS6 MDQS6 MDM6 MDQS7 MDQS7 [J7] CATHODE
ANODE [J8] [J11]
[J6] J7 J8 GND1 [J10] [J12] [J13] [J14] [J15] [J16]
_B _B
D1_ GND D1_ D1_ D1_ D1_ D1_ D1_ SENSE-
SD1_ GND VDD GND VDD GND SVDD SVDD
K MDQ50 MDQ53 MDQ54 MDM7 MDQ57 MDQ61 MODT1 VDD1
TX5 [K12]
[K2] [K10] [K11] [K13] [K14] [K15] [K16]

D1_ D1_ D1_ GND D1_ D1_ D1_ G1VDD D1_ VDD GND VDD GND VDD GND VDD
L MDQ48 MDQ49 MDQ43 MDQ47 MDQ45 MDQ62 MCS3
[L4] [L8] [L10] [L11] [L12] [L13] [L14] [L15] [L16]
_B
D1_ D1_ D1_ D1_ D1_ GND D1_ D1_ GND GND VDD GND VDD GND VDD GND
M MDQ35 MDQ34 MDQ37 MDQ41 MDQ42 MODT0 MODT3 [M9] [M10] [M12]
[M6] [M11] [M13] [M14] [M15] [M16]

D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ VDD VDD GND VDD VDD
N GND GND GND
MDQ33 [N2] MDM4 MDQS5 MDQS5 MDM5 MWE MODT2 MA13 [N10] [N11] [N12] [N13] [N14] [N15] [N16]
_B _B
D1_ D1_ D1_ D1_ D1_ G1VDD D1_ D1_ GND
G1V VDD VDD VDD
P GND DD GND GND GND
MDQS4 MDQS4 MDQ39 [P4] MDQ40 MDQ46 [P7] MRAS MCS1_ [P10] [P12] [P14] [P16]
_B [P10] [P11] [P13] [P15]
_B B
D1_ D1_ D1_ D1_ D1_ D1_ VDD
R GND GND G1VDD GND GND VDD GND VDD GND VDD
MDQ32 MDQ36 MDQ38 MDQ44 [R6] MCS2 MCAS
[R2] _B _B [R9] [R10]
[R10] [R11] [R12] [R13] [R14] [R15] [R16]
D1_ D1_ D1_
G1VDD D1_ MAPAR_ D1_ D1_ D1_ MAPAR_ D1_ G1VDD VDD GND VDD GND VDD GND
T MA05 MA01 MBA0 MCS0
[T1] ERR_B MA02 MBA1 OUT _B [T10] [T11] [T12] [T13] [T14] [T15] [T16]

DETAIL A

Figure 3. 1020 BGA ball map diagram (detail view A)

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 5
Pin assignments

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SD2_ SGND SD1_ SD1_ SGND SD1_ SGND SD1_ SGND SD1_ SD1_ SGND SD1_
SD1_ SGND
RX0 [A18] RX0 RX1 [A21] REF1_ [A23] RX2 [A23] RX3 RX4 [A28] RX5 RX6 [A31]
A
CLK_B

SD2_ SGND SD1_ SD1_ SGND SD1_ SGND SD1_ SGND SD1_ SD1_ SD1_ SD1_
SGND SGND NC_
RX0_B [B18] RX0_B RX1_B [B21] REF1_ [B23] RX2_B [B23] RX3_B RX4_B [B28] RX5_B RX6_B [B31] DET
B
CLK_B

SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SGND SD1_ SD1_
[C17] [C18] [C19] [C20] [C21] [C22] [C23] [C24] [C25] [C26] [C27] [C28] [C29] [C30] RX7_B RX7
C

SD2_ XGND SD1_ SD1_ XGND SD1_ SD1_ XGND SD1_ SD1_ XGND SD1_ SD1_ XGND SGND SGND
TX0 [D18] TX0 TX1 [D21] TX2 TX3 [D24] TX4 TX5 [D27] TX6 TX7 [D30] [D31]
D
[D32]

SD2_ SD1_ SD1_ SD1_ SD1_ SD1_ SD1_ SD1_ SD1_ SD1_ SD1_
XGND XGND XGND XGND XGND E
TX0_B [E18] TX0_B TX1_B [E18] TX2_B TX3_B TX4_B TX5_B [E27] TX6_B TX7_B [E30] REF2_ REF2_
[E24] CLK CLK_B

XVDD XGND XVDD SGND XVDD SGND SGND XVDD SGND SGND XVDD SGND SGND XVDD SGND SGND
[F17] [F18] [F19] [F20] [F21] [F22] [F23] [F24] [F25] [F26] [F27] [F28] [F29] [F30] [F31] [F32] F

AGND_ SD1_
SGND SD2_ SGND SD1_ SGND NC_ SGND NC_ SGND NC_ D2_ D2_ D2_ GND
[G17] IMP_CAL [G19] IMP_CAL [G21] G22 [G21]
SRDS1_ G25 IMP_CAL
[G27] G28 MDQ58 MDQ56 MDQ59 [G32] G
_RX _RX PLL2 _TX

AVDD_ AGND_ SGND

AGND_ AVDD_
NC_ NC_ AVDD_ SGND SGND D2_ D2_ D2_ D2_ D2_
GND H
SRDS2_ SRDS2_ [H19]
SRDS1_ SRDS1_ H22 H23 SRDS1_ [H25] [H26] MDQ63 MDQ60 [H29] MDQ55 MDQ52 MDQ51
PLL1 PLL1 PLL1 PLL1 PLL2
D2_ D2_ D2_
SGND SGND SGND SGND SGND SGND SGND SGND GND TH_ GND D2_ D2_
[J17] [J18] [J19] [J20] [J21] [J22] [J23] [J24] [J25] [J27]
MDQS7 MDQS7
MDM6 MDQS6 MDQS6 J
VDD _B _B

SVDD SVDD SVDD SVDD SVDD SVDD SVDD GND D2_ D2_ D2_ D2_ D2_ D2_ GND D2_
[K17] [K18] [K18] [K20] [K21] [K22] [K23] [K24] MODT1 MDQ61 MDQ57 MDM7 MDQ54 MDQ53 [G32] MDQ50 K

D2_
GND VDD GND VDD GND VDD GND MCS3 D2_ D2_ D2_ GND D2_ D2_ D2_
[L17] [L18] [L19] [L20] [L21] [L22] [L23]
G2VDD
MDQ62 MDQ45 MDQ47 [L29] MDQ43 MDQ49 MDQ48 L
_B

VDD VDD VDD VDD D2_ D2_ D2_ D2_ D2_ D2_ D2_
GND GND GND GND GND M
[M17] [M18] [M19] [M20] [M21] [M22] [M23] [M24] MODT3 MODT0 [M27] MDQ42 MDQ41 MDQ37 MDQ34 MDQ35

VDD VDD VDD D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
GND GND GND GND GND N
[N17] [N18] [N19] [N20] [N21] [N22] [N23] MA13 MODT2 MWE_ MDM5 MDQS5 MDQS5 MDM4 [N31] MDQ33
B _B
D2_ D2_ D2_
VDD GND VDD GND VDD GND VDD D2_ G2VDD D2_ D2_ GND D2_ MDQS4
[P17] [P18] [P19] [P20] [P21] [P22] [P23] MCS1_ MRAS [P26] MDQ46 MDQ40 [P29] MDQ39 _B MDQS4 P
B _B

VDD VDD VDD G2VDD D2_ D2_ D2_ D2_ D2_ D2_
GND GND GND GND GND GND R
[R17] [R18] [R19] [R20] [R21] [R22] [R23] [R24] MCAS_ MCS2_ [R27] MDQ44 MDQ38 MDQ36 [R31] MDQ32
B B
D2_ D2_ D2_
VDD GND VDD GND VDD GND G2VDD D2_ D2_ D2_ D2_ MAPAR_ D2_ G2VDD
MCS0 MAPAR T
[T17] [T18] [T19] [T20] [T21] [T22] [T23] MBA0 _OUT MA01 MBA1 MA02 ERR_B MA05 [T32]
_B

DETAIL B
Figure 4. 1020 BGA ball map diagram (detail view B)

B4860 QorIQ Qonverge Data Sheet, Rev. 4

6 NXP Semiconductors
 Pin assignments

DETAIL C
D1_ D1_ D1_
MCK2 G1VDD D1_ MCK3 G1VDD D1_ D1_ G1VDD GND GND VDD GND VDD GND VDD
U MCK2
_B [U3] MCK3 _B [U6] MA00 MA10 [U9] [U10] [U11] [U12] [U13] [U14] [U15] [U16]
D1_ D1_ D1_ D1_
V G1VDD MCK1 G1VDD D1_ D1_ D1_ G1VDD VDD GND VDD GND VDD GND
MCK0 MCK0 MCK1
_B [V3] _B [V6] MDIC1 MA04 MA03 [V10] [V11] [V12] [V13] [V14] [V15] [V16]

W G1VDD D1_ D1_ D1_ D1_ D1_ D1_ D1_ G1VDD GND GND VDD GND VDD GND VDD
[W1] MDIC0 MA08 MA06 MA07 MA09 MA12 MA11 [W9] [W10] [W11] [W12] [W13] [W14] [W15] [W16]

Y D1_ GND D1_ GND D1_ D1_ G1VDD D1_ D1_ G1VDD VDD GND VDD GND VDD GND
MECC3 [Y2] MECC7 [Y4] MECC0 MCKE3 [Y7] MCKE2 MA15 [Y10] [Y11] [Y12] [Y13] [Y14] [Y15] [Y16]

D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ G1VDD
AA MDQS8_ MDQS8
GND VDD GND VDD GND VDD
MECC6 MDQ30 MDM3 MBA2 MCKE0 MCKE1 MA14 [AA10] [AA11] [AA12] [AA13] [AA14] [AA15] [AA16]
B

AB D1_ GND D1_ D1_ GND D1_ D1_ GND GND GND VDD GND VDD GND VDD GND
MDM8 [AB2] MECC2 MDQ29 [AB5] MDQ27 MDQ26 [AB8] [AB9] [AB10] [AB11] [AB12] [AB13] [AB14] [AB15] [AB16]

D1_ D1_
AC D1_ D1_ D1_ D1_ GND AVDD_ GND GND VDD GND VDD GND VDD
MDQS3 MDQS3 M1VREF [AC10]
MECC5 MECC4 MECC1 MDQ31 _B [AC7] DDR1 [AC11] [AC12] [AC13] [AC14] [AC15] [AC16]

AD D1_ D1_ D1_ GND D1_ D1_ D1_ GND GND NC_ SENSE- D1_ OVDD GND OVDD GND
MDM2 MDQ19 MDQ22 [AD4] MDQ28 MDQ24 MDQ25 [AD8] [AD9] AD10 GND2 DDRCLK [AD13] [AD14] [AD15] [AD16]

D1_ D1_ D1_ D1_ D1_ D1_ TSEC_ TSEC_

AE GND 1588_ EVT0 EVT1 SENSE- GND OVDD GND OVDD
MDQ21 [AE2] MDQ23 MDQS0 MDQS0 MDQ04 MDQ01 CLK_OUT1588_TRIG _B _B VDD2 [AE13] [AE14] [AE15] [AE16]
_B _IN1

D1_ D1_ D1_ D1_ D1_ D1_ TSEC_ TSEC_

AF GND USB_ 1588_ 1588_TRIG CP_ EVT4 IFC_ IFC_ IFC_ IFC_
MDQS2 MDQS2 MDQ16 MDQ03 [AF5] MDQ06 MDQ00 D0 PULSE_ SYNC1 _B AD02 AD08 AD09 AD10
_B OUT1 _IN2

D1_ D1_ D1_ D1_ D1_ D1_ TSEC_

AG USB_ GND 1588_ CP_ GND IFC_ IFC_ GND IFC_ IFC_
MDQ20 MDQ18 MDQ17 MDM0 MDQ05 MDQ02 D1 [AG8] ALARM_ SYNC2 [AG11] AD00 AD01 [AG14] A16 A18
OUT1

D1_ D1_ D1_ D1_ TSEC_

AH GND USB_ USB_ 1588_ CP_ CP_ EVT2 IFC_ IFC_ IFC_ IFC_ IFC_
MDM1 [AH2] MDQ13 MDQ08 MDQ07 STP D2 ALARM_ SYNC7 SYNC3 _B A24 PAR0 A17 AD04 AD11
OUT2

D1_ D1_ D1_ D1_ GND USB_ GND EMI2_ CP_ GND EVT3 IFC_ GND IFC_
AJ MDQ11 MDQ14 MDQ12 MDQ09 [AJ13]
IFC_ GND
[AJ5] D3 [AJ7] MDIO SYNC0 [AJ10] _B PAR1 A25 A26 [AJ16]

AK D1_ D1_ D1_ USB_ USB_ USB_

TSEC_
1588_ CP_ CP_ CKSTP_ IFC_ IFC_ IFC_ IFC_ IFC_
WE_0
MDQS1 MDQS1 MDQ10 D7 D4 D5 PULSE_ SYNC5 SYNC6 ASLEEP OUT_ CS1_B CS2_B CS0_B OE_B
_B OUT2 B _B
D1_ GND DMA1_ CP_9
AL GND
1 2 3 USB_
4 5USB_ 6 GND 7 8 GND
10 CP_
11 CP_
12 GND 14IFC_ 15 IFC_ 16 GND
13 IFC_
[AL1] MDQ15 [AL3] CLK NXT [AL6] DACK0 SYNC4 [AL9] RCLK0 RCLK1 [AL12] AD05 WP0_B [AL15] BCTL
_B
TSEC_ DMA1_ DMA1_
GND 1588_ USB_ USB_ EMI2_ RESET_ CP_ CP_ HRESET IFC_ IFC_ IFC_
AM [AM2] CLK_IN D6 DIR DREQ0 DDONE0 MDC REQ_B RCLK0_B RCLK1_B _B CLK_OUT CLE RB0_B TE
_B _B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 5. 1020 BGA ball map diagram (detail view C)

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 7
Pin assignments

DETAIL D

D2_ D2_ D2_ D2_ D2_

GND VDD GND VDD GND VDD GND G2VDD G2VDD D2_ G2VDD
MA10 MA00 MCK3 MCK3 MCK2 MCK2 U
[U17] [U18] [U19] [U20] [U21] [U22] [U23] [U24] [U27] [U30]
_B _B
D2_ D2_ D2_ D2_ D2_
VDD GND VDD GND VDD GND G2VDD D2_ D2_ G2VDD G2VDD MCK0
MA03 MA04 MDIC1 MCK1 MCK1 MCK0 V
[V17] [V18] [V19] [V20] [V21] [V22] [V23] [V27] _B [V30]
_B

GND VDD GND VDD GND VDD GND G2VDD D2_ D2_ D2_ D2_ D2_ D2_ D2_ G2VDD
[W17] [W18] [W19] [W20] [W21] [W22] [W23] [W24] MA11 MA12 MA09 MA07 MA06 MA08 MDIC0 [W32] W

VDD GND VDD GND VDD GND G2VDD D2_ D2_ G2VDD D2_ D2_ GND D2_ GND D2_
[Y17] [Y18] [Y19] [Y20] [Y21] [Y22] [Y23] MA15 MCKE2 [Y26] MCKE3 MECC0 [Y29] MECC7 [Y31] MECC3 Y

GND VDD GND GND VDD G2VDD D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
VDD
[AA17] [AA18] [AA19] [AA20] [AA21] [AA22] [AA23] MA14 MCKE1 MCKE0 MBA2 MDM3 MDQ30 MECC6 MDQS8 MDQS8_ AA
B

VDD GND VDD GND GND GND GND GND D2_ D2_ GND D2_ D2_ GND D2_
VDD
[AB17] [AB18] [AB19] [AB20] [AB21] [AB22] [AB23] [AB24] [AB25] MDQ26 MDQ27 [AB28] MDQ29 MECC2 [AB31] MDM8 AB

D2_ D2_ D2_ D2_ D2_ D2_

GND VDD GND VDD GND VDD GND M2VREF AVDD_ GND
[AC17] [AC19] [AC21] [AC23] DDR2 [AC26] MDQS3 MDQS3 MDQ31 MECC1 MECC4 MECC5 AC
[AC18] [AC20] [AC22] _B

OVDD GND DVDD GND D2_ GND NC_ GND GND D2_ D2_ D2_ GND D2_ D2_ D2_
[AD18] [AD19] [AD20] DDRCLK [AD22] AD23 [AD24] [AD25] MDQ25 MDQ24 MDQ28 [AD29] MDQ22 MDQ19 MDM2 AD
[AD17]
GND IIC2_ UART1_ IIC4_ D2_ D2_ D2_ D2_ D2_ D2_
GND OVDD GND DVDD GND GND
[AE17] [AE18] [AE19] [AE20] [AE21] [AE22] SCL CTS_B SDA MDQ01 MDQ04 MDQS0 MDQS0 MDQ23 [AE31] MDQ21 AE
_B
TMP_ SDHC_ UART2_ D2_ D2_ D2_ D2_ D2_ D2_
IFC_ IFC_ IFC_
DETECT IRQ01 IRQ00 UART1_ GND
AF
AD12 AD13 AD03 DAT3 RTS_B SOUT MDQ00 MDQ06 [AF28] MDQ03 MDQ16 MDQS2 MDQS2
_B _B

GND IFC_ IFC_ GND SPI_ SDHC_ GND IIC2_ UART2_ GND D2_ D2_ D2_ D2_ D2_ D2_
[AG17] A15 A21 [AG20] DAT0 [AG20] SDA RTS_B [AG26] MDQ02 MDQ05 MDM0 MDQ17 MDQ18 MDQ20 AG
CLK

IFC_ IFC_ IFC_ SPI_ SDHC_ IIC1_ UART2_ IIC1_ D2_ D2_ D2_ GND D2_
A20 AD19 AD14
IRQ02 IRQ03 IRQ04
SDA SIN SCL MDQ07 MDQ08 MDQ13 [AH31] MDM1 AH
CS2_B DAT1

IFC_ IFC_ GND IFC_ SPI_ GND IRQ_ GND EMI1_ IIC4_ GND D2_ D2_ D2_ D2_
IRQ10 MDQ09 MDQ12 MDQ14 MDQ11 AJ
A27 CS3_B [AJ19] A22 CS0_B [AJ22] OUT_B [AJ25] MDC SCL [AJ28]

IFC_ SDHC_ TRST EMI1_ CP_ UART2_ IIC3_ D2_ D2_ D2_
IFC_ IFC_ IRQ06 IRQ08 IRQ05 IRQ07 AK
A23 AD07 CS1_B CMD _B MDIO LOS1 CTS_B SDA MDQ10 MDQS1 MDQS1
_B

IFC_ GND IFC_ SPI_ GND SDHC_ GND GND CP_ UART1_ GND D2_ GND
IRQ11 TDO TCK AL
AD06 [AL18] AVD MISO [AL21] DAT2 [AL24] [AL27] LOS3 SOUT [AL30] MDQ15 [AL32]

IFC_ IFC_ IFC_ SPI_ SPI_ SDHC_ CP_ UART1_ CP_ IIC3_ GND
RTC IRQ09 TMS TDI AM
RB1_ B CLK0 CLK1 CS3_B MOSI CLK LOS2 SIN LOS0 SCL [AM31]

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 6. 1020 BGA ball map diagram (detail view D)

B4860 QorIQ Qonverge Data Sheet, Rev. 4

8 NXP Semiconductors
 Pin assignments

1.2 Pinout list by bus

This table provides the pinout list for the chip sorted by bus.
Table 1. Pinout list by bus

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

DDR SDRAM memory Interface 1

D1_MDQ00 Data AF7 IO G1VDD —

D1_MDQ01 Data AE7 IO G1VDD —
D1_MDQ02 Data AG6 IO G1VDD —
D1_MDQ03 Data AF4 IO G1VDD —
D1_MDQ04 Data AE6 IO G1VDD —
D1_MDQ05 Data AG5 IO G1VDD —
D1_MDQ06 Data AF6 IO G1VDD —
D1_MDQ07 Data AH5 IO G1VDD —
D1_MDQ08 Data AH4 IO G1VDD —
D1_MDQ09 Data AJ4 IO G1VDD —
D1_MDQ10 Data AK3 IO G1VDD —
D1_MDQ11 Data AJ1 IO G1VDD —
D1_MDQ12 Data AJ3 IO G1VDD —
D1_MDQ13 Data AH3 IO G1VDD —
D1_MDQ14 Data AJ2 IO G1VDD —
D1_MDQ15 Data AL2 IO G1VDD —
D1_MDQ16 Data AF3 IO G1VDD —
D1_MDQ17 Data AG3 IO G1VDD —
D1_MDQ18 Data AG2 IO G1VDD —
D1_MDQ19 Data AD2 IO G1VDD —
D1_MDQ20 Data AG1 IO G1VDD —
D1_MDQ21 Data AE1 IO G1VDD —
D1_MDQ22 Data AD3 IO G1VDD —
D1_MDQ23 Data AE3 IO G1VDD —
D1_MDQ24 Data AD6 IO G1VDD —
D1_MDQ25 Data AD7 IO G1VDD —
D1_MDQ26 Data AB7 IO G1VDD —
D1_MDQ27 Data AB6 IO G1VDD —
D1_MDQ28 Data AD5 IO G1VDD —
D1_MDQ29 Data AB4 IO G1VDD —
D1_MDQ30 Data AA4 IO G1VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 9
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

D1_MDQ31 Data AC4 IO G1VDD —

D1_MDQ32 Data R1 IO G1VDD —
D1_MDQ33 Data N1 IO G1VDD —
D1_MDQ34 Data M2 IO G1VDD —
D1_MDQ35 Data M1 IO G1VDD —
D1_MDQ36 Data R3 IO G1VDD —
D1_MDQ37 Data M3 IO G1VDD —
D1_MDQ38 Data R4 IO G1VDD —
D1_MDQ39 Data P3 IO G1VDD —
D1_MDQ40 Data P5 IO G1VDD —
D1_MDQ41 Data M4 IO G1VDD —
D1_MDQ42 Data M5 IO G1VDD —
D1_MDQ43 Data L3 IO G1VDD —
D1_MDQ44 Data R5 IO G1VDD —
D1_MDQ45 Data L6 IO G1VDD —
D1_MDQ46 Data P6 IO G1VDD —
D1_MDQ47 Data L5 IO G1VDD —
D1_MDQ48 Data L1 IO G1VDD —
D1_MDQ49 Data L2 IO G1VDD —
D1_MDQ50 Data K1 IO G1VDD —
D1_MDQ51 Data H1 IO G1VDD —
D1_MDQ52 Data H2 IO G1VDD —
D1_MDQ53 Data K3 IO G1VDD —
D1_MDQ54 Data K4 IO G1VDD —
D1_MDQ55 Data H3 IO G1VDD —
D1_MDQ56 Data G3 IO G1VDD —
D1_MDQ57 Data K6 IO G1VDD —
D1_MDQ58 Data G4 IO G1VDD —
D1_MDQ59 Data G2 IO G1VDD —
D1_MDQ60 Data H5 IO G1VDD —
D1_MDQ61 Data K7 IO G1VDD —
D1_MDQ62 Data L7 IO G1VDD —
D1_MDQ63 Data H6 IO G1VDD —
D1_MECC0 Error Correcting Code Y5 IO G1VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

10 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

D1_MECC1 Error Correcting Code AC3 IO G1VDD —

D1_MECC2 Error Correcting Code AB3 IO G1VDD —
D1_MECC3 Error Correcting Code Y1 IO G1VDD —
D1_MECC4 Error Correcting Code AC2 IO G1VDD —
D1_MECC5 Error Correcting Code AC1 IO G1VDD —
D1_MECC6 Error Correcting Code AA3 IO G1VDD —
D1_MECC7 Error Correcting Code Y3 IO G1VDD —
D1_MAPAR_ERR_B Address Parity Error T3 I G1VDD 2, 26
D1_MAPAR_OUT Address Parity Out T7 O G1VDD —
D1_MDM0 Data Mask AG4 O G1VDD 2
D1_MDM1 Data Mask AH1 O G1VDD 2
D1_MDM2 Data Mask AD1 O G1VDD 2
D1_MDM3 Data Mask AA5 O G1VDD 2
D1_MDM4 Data Mask N3 O G1VDD 2
D1_MDM5 Data Mask N6 O G1VDD 2
D1_MDM6 Data Mask J3 O G1VDD 2
D1_MDM7 Data Mask K5 O G1VDD 2
D1_MDM8 Data Mask AB1 O G1VDD 2
D1_MDQS0 Data Strobe AE5 IO G1VDD —
D1_MDQS1 Data Strobe AK2 IO G1VDD —
D1_MDQS2 Data Strobe AF2 IO G1VDD —
D1_MDQS3 Data Strobe AC6 IO G1VDD —
D1_MDQS4 Data Strobe P1 IO G1VDD —
D1_MDQS5 Data Strobe N4 IO G1VDD —
D1_MDQS6 Data Strobe J1 IO G1VDD —
D1_MDQS7 Data Strobe J4 IO G1VDD —
D1_MDQS8 Data Strobe AA2 IO G1VDD —
D1_MDQS0_B Data Strobe AE4 IO G1VDD —
D1_MDQS1_B Data Strobe AK1 IO G1VDD —
D1_MDQS2_B Data Strobe AF1 IO G1VDD —
D1_MDQS3_B Data Strobe AC5 IO G1VDD —
D1_MDQS4_B Data Strobe P2 IO G1VDD —
D1_MDQS5_B Data Strobe N5 IO G1VDD —
D1_MDQS6_B Data Strobe J2 IO G1VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 11
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

D1_MDQS7_B Data Strobe J5 IO G1VDD —

D1_MDQS8_B Data Strobe AA1 IO G1VDD —
D1_MBA0 Bank Select T8 O G1VDD —
D1_MBA1 Bank Select T5 O G1VDD —
D1_MBA2 Bank Select AA6 O G1VDD —
D1_MA00 Address U7 O G1VDD —
D1_MA01 Address T6 O G1VDD —
D1_MA02 Address T4 O G1VDD —
D1_MA03 Address V9 O G1VDD —
D1_MA04 Address V8 O G1VDD —
D1_MA05 Address T2 O G1VDD —
D1_MA06 Address W4 O G1VDD —
D1_MA07 Address W5 O G1VDD —
D1_MA08 Address W3 O G1VDD —
D1_MA09 Address W6 O G1VDD —
D1_MA10 Address U8 O G1VDD —
D1_MA11 Address W8 O G1VDD —
D1_MA12 Address W7 O G1VDD —
D1_MA13 Address N9 O G1VDD —
D1_MA14 Address AA9 O G1VDD —
D1_MA15 Address Y9 O G1VDD —
D1_MWE_B Write Enable N7 O G1VDD —
D1_MRAS_B Row Address Strobe P8 O G1VDD —
D1_MCAS_B Column Address Strobe R8 O G1VDD —
D1_MCS0_B Chip Select T9 O G1VDD —
D1_MCS1_B Chip Select P9 O G1VDD —
D1_MCS2_B Chip Select R7 O G1VDD —
D1_MCS3_B Chip Select L9 O G1VDD —
D1_MCKE0 Clock Enable AA7 O G1VDD 10
D1_MCKE1 Clock Enable AA8 O G1VDD 10
D1_MCKE2 Clock Enable Y8 O G1VDD 10
D1_MCKE3 Clock Enable Y6 O G1VDD 10
D1_MCK0 Clock V1 O G1VDD —
D1_MCK1 Clock V4 O G1VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

12 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

D1_MCK2 Clock U1 O G1VDD —

D1_MCK3 Clock U4 O G1VDD —
D1_MCK0_B Clock Complements V2 O G1VDD —
D1_MCK1_B Clock Complements V5 O G1VDD —
D1_MCK2_B Clock Complements U2 O G1VDD —
D1_MCK3_B Clock Complements U5 O G1VDD —
D1_DDRCLK DDR Clock - Controller 1 AD12 I OVDD —
D1_MODT0 On Die Termination M7 O G1VDD 10
D1_MODT1 On Die Termination K8 O G1VDD 10
D1_MODT2 On Die Termination N8 O G1VDD 10
D1_MODT3 On Die Termination M8 O G1VDD 10
D1_MDIC0 Driver Impedance Calibration W2 IO G1VDD 1
D1_MDIC1 Driver Impedance Calibration V7 IO G1VDD 1

DDR SDRAM memory Interface 2

D2_MDQ00 Data AF26 IO G2VDD —

D2_MDQ01 Data AE26 IO G2VDD —
D2_MDQ02 Data AG27 IO G2VDD —
D2_MDQ03 Data AF29 IO G2VDD —
D2_MDQ04 Data AE27 IO G2VDD —
D2_MDQ05 Data AG28 IO G2VDD —
D2_MDQ06 Data AF27 IO G2VDD —
D2_MDQ07 Data AH28 IO G2VDD —
D2_MDQ08 Data AH29 IO G2VDD —
D2_MDQ09 Data AJ29 IO G2VDD —
D2_MDQ10 Data AK30 IO G2VDD —
D2_MDQ11 Data AJ32 IO G2VDD —
D2_MDQ12 Data AJ30 IO G2VDD —
D2_MDQ13 Data AH30 IO G2VDD —
D2_MDQ14 Data AJ31 IO G2VDD —
D2_MDQ15 Data AL31 IO G2VDD —
D2_MDQ16 Data AF30 IO G2VDD —
D2_MDQ17 Data AG30 IO G2VDD —
D2_MDQ18 Data AG31 IO G2VDD —
D2_MDQ19 Data AD31 IO G2VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 13
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

D2_MDQ20 Data AG32 IO G2VDD —

D2_MDQ21 Data AE32 IO G2VDD —
D2_MDQ22 Data AD30 IO G2VDD —
D2_MDQ23 Data AE30 IO G2VDD —
D2_MDQ24 Data AD27 IO G2VDD —
D2_MDQ25 Data AD26 IO G2VDD —
D2_MDQ26 Data AB26 IO G2VDD —
D2_MDQ27 Data AB27 IO G2VDD —
D2_MDQ28 Data AD28 IO G2VDD —
D2_MDQ29 Data AB29 IO G2VDD —
D2_MDQ30 Data AA29 IO G2VDD —
D2_MDQ31 Data AC29 IO G2VDD —
D2_MDQ32 Data R32 IO G2VDD —
D2_MDQ33 Data N32 IO G2VDD —
D2_MDQ34 Data M31 IO G2VDD —
D2_MDQ35 Data M32 IO G2VDD —
D2_MDQ36 Data R30 IO G2VDD —
D2_MDQ37 Data M30 IO G2VDD —
D2_MDQ38 Data R29 IO G2VDD —
D2_MDQ39 Data P30 IO G2VDD —
D2_MDQ40 Data P28 IO G2VDD —
D2_MDQ41 Data M29 IO G2VDD —
D2_MDQ42 Data M28 IO G2VDD —
D2_MDQ43 Data L30 IO G2VDD —
D2_MDQ44 Data R28 IO G2VDD —
D2_MDQ45 Data L27 IO G2VDD —
D2_MDQ46 Data P27 IO G2VDD —
D2_MDQ47 Data L28 IO G2VDD —
D2_MDQ48 Data L32 IO G2VDD —
D2_MDQ49 Data L31 IO G2VDD —
D2_MDQ50 Data K32 IO G2VDD —
D2_MDQ51 Data H32 IO G2VDD —
D2_MDQ52 Data H31 IO G2VDD —
D2_MDQ53 Data K30 IO G2VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

14 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

D2_MDQ54 Data K29 IO G2VDD —

D2_MDQ55 Data H30 IO G2VDD —
D2_MDQ56 Data G30 IO G2VDD —
D2_MDQ57 Data K27 IO G2VDD —
D2_MDQ58 Data G29 IO G2VDD —
D2_MDQ59 Data G31 IO G2VDD —
D2_MDQ60 Data H28 IO G2VDD —
D2_MDQ61 Data K26 IO G2VDD —
D2_MDQ62 Data L26 IO G2VDD —
D2_MDQ63 Data H27 IO G2VDD —
D2_MECC0 Error Correcting Code Y28 IO G2VDD —
D2_MECC1 Error Correcting Code AC30 IO G2VDD —
D2_MECC2 Error Correcting Code AB30 IO G2VDD —
D2_MECC3 Error Correcting Code Y32 IO G2VDD —
D2_MECC4 Error Correcting Code AC31 IO G2VDD —
D2_MECC5 Error Correcting Code AC32 IO G2VDD —
D2_MECC6 Error Correcting Code AA30 IO G2VDD —
D2_MECC7 Error Correcting Code Y30 IO G2VDD —
D2_MAPAR_ERR_B Address Parity Error T30 I G2VDD 26
D2_MAPAR_OUT Address Parity Out T26 O G2VDD 2
D2_MDM0 Data Mask AG29 O G2VDD 2
D2_MDM1 Data Mask AH32 O G2VDD 2
D2_MDM2 Data Mask AD32 O G2VDD 2
D2_MDM3 Data Mask AA28 O G2VDD 2
D2_MDM4 Data Mask N30 O G2VDD 2
D2_MDM5 Data Mask N27 O G2VDD 2
D2_MDM6 Data Mask J30 O G2VDD 2
D2_MDM7 Data Mask K28 O G2VDD 2
D2_MDM8 Data Mask AB32 O G2VDD 2
D2_MDQS0 Data Strobe AE28 IO G2VDD —
D2_MDQS1 Data Strobe AK31 IO G2VDD —
D2_MDQS2 Data Strobe AF31 IO G2VDD —
D2_MDQS3 Data Strobe AC27 IO G2VDD —
D2_MDQS4 Data Strobe P32 IO G2VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 15
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

D2_MDQS5 Data Strobe N29 IO G2VDD —

D2_MDQS6 Data Strobe J32 IO G2VDD —
D2_MDQS7 Data Strobe J29 IO G2VDD —
D2_MDQS8 Data Strobe AA31 IO G2VDD —
D2_MDQS0_B Data Strobe AE29 IO G2VDD —
D2_MDQS1_B Data Strobe AK32 IO G2VDD —
D2_MDQS2_B Data Strobe AF32 IO G2VDD —
D2_MDQS3_B Data Strobe AC28 IO G2VDD —
D2_MDQS4_B Data Strobe P31 IO G2VDD —
D2_MDQS5_B Data Strobe N28 IO G2VDD —
D2_MDQS6_B Data Strobe J31 IO G2VDD —
D2_MDQS7_B Data Strobe J28 IO G2VDD —
D2_MDQS8_B Data Strobe AA32 IO G2VDD —
D2_MBA0 Bank Select T25 O G2VDD —
D2_MBA1 Bank Select T28 O G2VDD —
D2_MBA2 Bank Select AA27 O G2VDD —
D2_MA00 Address U26 O G2VDD —
D2_MA01 Address T27 O G2VDD —
D2_MA02 Address T29 O G2VDD —
D2_MA03 Address V24 O G2VDD —
D2_MA04 Address V25 O G2VDD —
D2_MA05 Address T31 O G2VDD —
D2_MA06 Address W29 O G2VDD —
D2_MA07 Address W28 O G2VDD —
D2_MA08 Address W30 O G2VDD —
D2_MA09 Address W27 O G2VDD —
D2_MA10 Address U25 O G2VDD —
D2_MA11 Address W25 O G2VDD —
D2_MA12 Address W26 O G2VDD —
D2_MA13 Address N24 O G2VDD —
D2_MA14 Address AA24 O G2VDD —
D2_MA15 Address Y24 O G2VDD —
D2_MWE_B Write Enable N26 O G2VDD —
D2_MRAS_B Row Address Strobe P25 O G2VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

16 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

D2_MCAS_B Column Address Strobe R25 O G2VDD —

D2_MCS0_B Chip Select T24 O G2VDD —
D2_MCS1_B Chip Select P24 O G2VDD —
D2_MCS2_B Chip Select R26 O G2VDD —
D2_MCS3_B Chip Select L24 O G2VDD —
D2_MCKE0 Clock Enable AA26 O G2VDD 10
D2_MCKE1 Clock Enable AA25 O G2VDD 10
D2_MCKE2 Clock Enable Y25 O G2VDD 10
D2_MCKE3 Clock Enable Y27 O G2VDD 10
D2_MCK0 Clock V32 O G2VDD —
D2_MCK1 Clock V29 O G2VDD —
D2_MCK2 Clock U32 O G2VDD —
D2_MCK3 Clock U29 O G2VDD —
D2_MCK0_B Clock Complements V31 O G2VDD —
D2_MCK1_B Clock Complements V28 O G2VDD —
D2_MCK2_B Clock Complements U31 O G2VDD —
D2_MCK3_B Clock Complements U28 O G2VDD —
D2_DDRCLK DDR Clock–Controller 2 AD21 I OVDD —
D2_MODT0 On Die Termination M26 O G2VDD 10
D2_MODT1 On Die Termination K25 O G2VDD 10
D2_MODT2 On Die Termination N25 O G2VDD 10
D2_MODT3 On Die Termination M25 O G2VDD 10
D2_MDIC0 Driver Impedance Calibration W31 IO G2VDD 1
D2_MDIC1 Driver Impedance Calibration V26 IO G2VDD 1

Integrated Flash Controller Interface

IFC_AD00/CFG_GPINPUT0 Muxed Data/Address AG12 IO OVDD 22

IFC_AD01/CFG_GPINPUT1 Muxed Data/Address AG13 IO OVDD 22
IFC_AD02/CFG_GPINPUT2 Muxed Data/Address AF13 IO OVDD 22
IFC_AD03/CFG_GPINPUT3 Muxed Data/Address AF19 IO OVDD 22
IFC_AD04/CFG_GPINPUT4 Muxed Data/Address AH15 IO OVDD 22
IFC_AD05/CFG_GPINPUT5 Muxed Data/Address AL13 IO OVDD 22
IFC_AD06/CFG_GPINPUT6 Muxed Data/Address AL17 IO OVDD 22
IFC_AD07/CFG_GPINPUT7 Muxed Data/Address AK18 IO OVDD 22
IFC_AD08/CFG_RCW_SRC0 Muxed Data/Address AF14 IO OVDD 22

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 17
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

IFC_AD09/CFG_RCW_SRC1 Muxed Data/Address AF15 IO OVDD 22

IFC_AD10/CFG_RCW_SRC2 Muxed Data/Address AF16 IO OVDD 22
IFC_AD11/CFG_RCW_SRC3 Muxed Data/Address AH16 IO OVDD 22
IFC_AD12/CFG_RCW_SRC4 Muxed Data/Address AF17 IO OVDD 22
IFC_AD13/CFG_RCW_SRC5 Muxed Data/Address AF18 IO OVDD 22
IFC_AD14/CFG_RCW_SRC6 Muxed Data/Address AH19 IO OVDD 22
IFC_AD15/CFG_RCW_SRC7 Muxed Data/Address AG18 IO OVDD 22
IFC_A16 Address AG15 O OVDD 2, 8
IFC_A17 Address AH14 O OVDD 2, 8
IFC_A18 Address AG16 O OVDD 2, 8
IFC_A19 Address AH18 O OVDD 2, 8
IFC_A20 Address AH17 O OVDD 2, 8
IFC_A21/CFG_DRAM_TYPE Address AG19 O OVDD 2, 22,
23
IFC_A22/IFC_WP1_B Address AJ20 O OVDD 2,
IFC_A23/IFC_WP2_B Address AK17 O OVDD 2,
IFC_A24/IFC_WP3_B Address AH12 O OVDD 2,
IFC_A25/GPIO2[25]/ Address AJ14 O OVDD 2
IFC_RB2_B/IFC_FCTA2
IFC_A26/GPIO2[26]/ Address AJ15 O OVDD 2
IFC_RB3_B/IFC_FCTA3
IFC_A27/GPIO2[27] Address AJ17 O OVDD 2
IFC_PAR0/GPIO2[13] Data Parity / Address and Data AH13 IO OVDD —
Parity for byte 0
IFC_PAR1/GPIO2[14] Data Parity / Address and Data AJ12 IO OVDD —
Parity for byte 1
IFC_CS0_B Chip Select AK15 O OVDD 2, 27
IFC_CS1_B/GPIO2[10] Chip Select AK13 O OVDD 2, 27
IFC_CS2_B/GPIO2[11] Chip Select AK14 O OVDD 2, 27
IFC_CS3_B/GPIO2[12] Chip Select AJ18 O OVDD 2, 27
IFC_WE_B/IFC_WBE0 Write Enable (NAND/NOR) AK12 IO OVDD 2, 8
IFC_WE_B/IFC_WBE0 Write byte 0 enable (GPCM) AK12 IO OVDD 2, 8
IFC_CLE/IFC_WBE1/ Write byte 1 enable (GPCM) AM14 IO OVDD 22
CFG_RCW_SRC8
IFC_BCTL External Buffer control AL16 O OVDD 2
IFC_TE/CFG_IFC_TE External Transceiver Enable AM16 O OVDD 2, 22,
25

B4860 QorIQ Qonverge Data Sheet, Rev. 4

18 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

IFC_AVD/IFC_ALE/ Address Latch Enable– AL19 IO OVDD 22, 15

CFG_RSP_DIS NAND/NOR & GPCM (NAND)
IFC_AVD/IFC_ALE/ Address Valid Data for internal AL19 IO OVDD 22, 15
CFG_RSP_DIS latched based NOR
IFC_CLE/IFC_WBE1/ Command Latch Enable AM14 IO OVDD 22
CFG_RCW_SRC8 (NAND)
IFC_OE_B/IFC_RE_B Output Enable–NOR & GPCM AK16 IO OVDD 8
IFC_OE_B/IFC_RE_B Read Enable–NAND AK16 IO OVDD 8
IFC_WP0_B NAND write protect signal 0 AL14 O OVDD 8
IFC_A22/IFC_WP1_B NAND write protect signal 1 AJ20 IO OVDD —
IFC_A23/IFC_WP2_B NAND write protect signal 2 AK17 IO OVDD —
IFC_A24/IFC_WP3_B NAND write protect signal 3 AH12 IO OVDD —
IFC_RB0_B/IFC_FCTA0 CS0: NAND/NOR Flash AM15 I OVDD 2, 28
Ready Busy
IFC_RB1_B/IFC_FCTA1 CS1: NAND/NOR Flash AM17 I OVDD 2, 28
Ready Busy
IFC_A25/GPIO2[25]/ CS2: NAND/NOR Flash AJ14 I OVDD 2
IFC_RB2_B/IFC_FCTA2 Ready Busy
IFC_A26/GPIO2[26]/ CS3: NAND/NOR Flash AJ15 I OVDD 2
IFC_RB3_B/IFC_FCTA3 Ready Busy
IFC_RB0_B/IFC_FCTA0 CS0: GPCM External Access AM15 I OVDD 2, 28
Termination
IFC_RB1_B/IFC_FCTA1 CS1: GPCM External Access AM17 I OVDD 2, 28
Termination
IFC_A25/GPIO2[25]/ CS2: GPCM External Access AJ14 I OVDD 2
IFC_RB2_B/IFC_FCTA2 Termination
IFC_A26/GPIO2[26]/ CS3: GPCM External Access AJ15 I OVDD 2
IFC_RB3_B/IFC_FCTA3 Termination
IFC_CLK0 Clock AM18 O OVDD 2
IFC_CLK1 Clock AM19 O OVDD 2

DUART Interface

UART1_SOUT/GPIO1[15]/ Transmit Data AL29 O DVDD 2

CP_LOS4
UART1_SIN/GPIO1[17]/ Receive Data AM28 I DVDD 2
CP_LOS5
UART1_RTS_B/GPIO1[19]/ Ready to Send AF24 O DVDD 2
UART3_SOUT/CP_LOS6
UART1_CTS_B/GPIO1[21]/ Clear to Send AE24 I DVDD 2
UART3_SIN/CP_LOS7

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 19
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

UART2_SOUT/GPIO1[16] Transmit Data AF25 O DVDD 2

UART2_SIN/GPIO1[18] Receive Data AH26 I DVDD 2
UART2_RTS_B/GPIO1[20]/ Ready to Send AG25 O DVDD 2
UART4_SOUT
UART2_CTS_B/GPIO1[22]/ Clear to Send AK28 I DVDD 2
UART4_SIN
UART1_RTS_B/GPIO1[19]/ Transmit Data AF24 O DVDD 2
UART3_SOUT/CP_LOS6
UART1_CTS_B/GPIO1[21]/ Receive Data AE24 I DVDD 2
UART3_SIN/CP_LOS7
UART2_RTS_B/GPIO1[20]/ Transmit Data AG25 O DVDD 2
UART4_SOUT
UART2_CTS_B/GPIO1[22]/ Receive Data AK28 I DVDD 2
UART4_SIN

I2C Interface

IIC1_SCL Serial Clock (supports PBL) AH27 IO DVDD 4

IIC1_SDA Serial Data (supports PBL) AH25 IO DVDD 4
IIC2_SCL Serial Clock AE23 IO DVDD 4
IIC2_SDA Serial Data AG24 IO DVDD 4
IIC3_SCL/GPIO3[3] Serial Clock AM30 IO DVDD 4
IIC3_SDA/GPIO3[4] Serial Data AK29 IO DVDD 4
IIC4_SCL/GPIO3[5]/EVT5_B Serial Clock AJ27 IO DVDD 4
IIC4_SDA/GPIO3[6]/EVT6_B/ Serial Data AE25 IO DVDD 4
USB_PWRFAULT

eSPI Interface

SPI_MOSI Master Out Slave In AM21 IO OVDD —

SPI_MISO Master In Slave Out AL20 I OVDD —
SPI_CLK Clock AG21 O OVDD 2
SPI_CS0_B/GPIO2[0]/ Chip Select AJ21 O OVDD 2
SDHC_DAT4
SPI_CS1_B/GPIO2[1]/ Chip Select AK19 O OVDD 2
SDHC_DAT5
SPI_CS2_B/GPIO2[2]/ Chip Select AH20 O OVDD 2
SDHC_DAT6
SPI_CS3_B/GPIO2[3]/ Chip Select AM20 O OVDD 2
SDHC_DAT7

eSDHC Interface

B4860 QorIQ Qonverge Data Sheet, Rev. 4

20 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

SDHC_CMD/GPIO2[4] Command/Response AK20 IO OVDD 32

SDHC_DAT0/GPIO2[5] Data AG22 IO OVDD 32
SDHC_DAT1/GPIO2[6] Data AH21 IO OVDD 32
SDHC_DAT2/GPIO2[7] Data AL22 IO OVDD 32
SDHC_DAT3/GPIO2[8] Data AF21 IO OVDD 32
SPI_CS0_B/GPIO2[0]/ Data AJ21 IO OVDD 32
SDHC_DAT4
SPI_CS1_B/GPIO2[1]/ Data AK19 IO OVDD 32
SDHC_DAT5
SPI_CS2_B/GPIO2[2]/ Data AH20 IO OVDD 32
SDHC_DAT6
SPI_CS3_B/GPIO2[3]/ Data AM20 IO OVDD 32
SDHC_DAT7
SDHC_CLK/GPIO2[9] Host to Card Clock AM22 O OVDD 2

Programmable Interrupt Controller Interface

IRQ00 External Interrupts AF23 I OVDD 2

IRQ01 External Interrupts AF22 I OVDD 2
IRQ02 External Interrupts AH22 I OVDD 2
IRQ03/GPIO1[23] External Interrupts AH23 I OVDD 2
IRQ04/GPIO1[24] External Interrupts AH24 I OVDD 2
IRQ05/GPIO1[25] External Interrupts AK23 I OVDD 2
IRQ06/GPIO1[26]/TMR0 External Interrupts AK21 I OVDD 2
IRQ07/GPIO1[27]/TMR1 External Interrupts AK24 I OVDD 2
IRQ08/GPIO1[28]/TMR2 External Interrupts AK22 I OVDD 2
IRQ09/GPIO1[29]/TMR3 External Interrupts AM24 I OVDD 2
IRQ10/GPIO1[30]/TMR4 External Interrupts AJ24 I OVDD 2
IRQ11/GPIO1[31]/TMR5 External Interrupts AL23 I OVDD 2
IRQ_OUT_B/EVT9_B Interrupt Output AJ23 O OVDD 2, 5

Trust

TMP_DETECT_B Tamper Detect AF20 I OVDD 2, 6

System Control

PORESET_B Power On Reset E1 I QVDD 7

HRESET_B Hard Reset AM12 IO OVDD 3
RESET_REQ_B Reset Request (POR or Hard) AM9 O OVDD 2, 8

Power Management

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 21
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

ASLEEP/GPIO1[13]/CFG_XVDD_ Asleep AK10 O OVDD 2, 22,

SEL 24

Clock Signals

SYSCLK System Clock F1 I QVDD 7

RTC/GPIO1[14] Real Time Clock AM23 I OVDD 2

Debug Signals

EVT0_B Event 0 AE10 I OVDD 9

EVT1_B Event 1 AE11 IO OVDD —
EVT2_B Event 2 AH11 IO OVDD —
EVT3_B Event 3 AJ11 IO OVDD —
EVT4_B Event 4 AF12 IO OVDD —
IIC4_SCL/GPIO3[5]/EVT5_B Event 5 AJ27 IO DVDD —
IIC4_SDA/GPIO3[6]/EVT6_B/ Event 6 AE25 IO DVDD —
USB_PWRFAULT
DMA1_DACK0_B/GPIO3[1]/ Event 7 AL7 IO OVDD —
EVT7_B/TMR6
DMA1_DDONE0_B/GPIO3[2]/ Event 8 AM7 IO OVDD —
EVT8_B/TMR7
IRQ_OUT_B/EVT9_B Event 9 AJ23 IO OVDD —
CKSTP_OUT_B Checkstop Out AK11 O OVDD 2, 3
CLK_OUT Clock Out AM13 O OVDD 10

JTAG Signals

TCK Test Clock AL26 I OVDD —

TDI Test Data In AM26 I OVDD 9
TDO Test Data Out AL25 O OVDD 10
TMS Test Mode Select AM25 I OVDD 9
TRST_B Test Reset AK25 I OVDD 9

SerDes 1 (x8) CPRI, Aurora, 1GE, 2.5GE

SD1_TX0 SerDes Tx Data (pos) D19 O XVDD —

SD1_TX1 SerDes Tx Data (pos) D20 O XVDD —
SD1_TX2 SerDes Tx Data (pos) D22 O XVDD —
SD1_TX3 SerDes Tx Data (pos) D23 O XVDD —
SD1_TX4 SerDes Tx Data (pos) D25 O XVDD —
SD1_TX5 SerDes Tx Data (pos) D26 O XVDD —
SD1_TX6 SerDes Tx Data (pos) D28 O XVDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

22 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

SD1_TX7 SerDes Tx Data (pos) D29 O XVDD —

SD1_TX0_B SerDes Tx Data (neg) E19 O XVDD —
SD1_TX1_B SerDes Tx Data (neg) E20 O XVDD —
SD1_TX2_B SerDes Tx Data (neg) E22 O XVDD —
SD1_TX3_B SerDes Tx Data (neg) E23 O XVDD —
SD1_TX4_B SerDes Tx Data (neg) E25 O XVDD —
SD1_TX5_B SerDes Tx Data (neg) E26 O XVDD —
SD1_TX6_B SerDes Tx Data (neg) E28 O XVDD —
SD1_TX7_B SerDes Tx Data (neg) E29 O XVDD —
SD1_RX0 SerDes Rx Data (pos) A19 I SVDD —
SD1_RX1 SerDes Rx Data (pos) A20 I SVDD —
SD1_RX2 SerDes Rx Data (pos) A24 I SVDD —
SD1_RX3 SerDes Rx Data (pos) A26 I SVDD —
SD1_RX4 SerDes Rx Data (pos) A27 I SVDD —
SD1_RX5 SerDes Rx Data (pos) A29 I SVDD —
SD1_RX6 SerDes Rx Data (pos) A30 I SVDD —
SD1_RX7 SerDes Rx Data (pos) C32 I SVDD —
SD1_RX0_B SerDes Rx Data (neg) B19 I SVDD —
SD1_RX1_B SerDes Rx Data (neg) B20 I SVDD —
SD1_RX2_B SerDes Rx Data (neg) B24 I SVDD —
SD1_RX3_B SerDes Rx Data (neg) B26 I SVDD —
SD1_RX4_B SerDes Rx Data (neg) B27 I SVDD —
SD1_RX5_B SerDes Rx Data (neg) B29 I SVDD —
SD1_RX6_B SerDes Rx Data (neg) B30 I SVDD —
SD1_RX7_B SerDes Rx Data (neg) C31 I SVDD —
SD1_REF1_CLK SerDes PLL 1 Reference B22 I SVDD —
Clock
SD1_REF1_CLK_B SerDes PLL 1 Reference A22 I SVDD —
Clock Complement
SD1_REF2_CLK SerDes PLL 2 Reference E31 I SVDD —
Clock
SD1_REF2_CLK_B SerDes PLL 2 Reference E32 I SVDD —
Clock Complement
SD1_IMP_CAL_TX SerDes Tx Impedance G26 I XVDD 11
Calibration

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 23
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

SD1_IMP_CAL_RX SerDes Rx Impedance G20 I SVDD 12

Calibration

SerDes 2 (x8) PCIe, sRIO, Aurora, 10GE, 1GE, 2.5GE

SD2_TX0 SerDes Tx Data (pos) D17 O XVDD —

SD2_TX1 SerDes Tx Data (pos) D16 O XVDD —
SD2_TX2 SerDes Tx Data (pos) D14 O XVDD —
SD2_TX3 SerDes Tx Data (pos) D13 O XVDD —
SD2_TX4 SerDes Tx Data (pos) D11 O XVDD —
SD2_TX5 SerDes Tx Data (pos) D10 O XVDD —
SD2_TX6 SerDes Tx Data (pos) D8 O XVDD —
SD2_TX7 SerDes Tx Data (pos) D7 O XVDD —
SD2_TX0_B SerDes Tx Data (neg) E17 O XVDD —
SD2_TX1_B SerDes Tx Data (neg) E16 O XVDD —
SD2_TX2_B SerDes Tx Data (neg) E14 O XVDD —
SD2_TX3_B SerDes Tx Data (neg) E13 O XVDD —
SD2_TX4_B SerDes Tx Data (neg) E11 O XVDD —
SD2_TX5_B SerDes Tx Data (neg) E10 O XVDD —
SD2_TX6_B SerDes Tx Data (neg) E8 O XVDD —
SD2_TX7_B SerDes Tx Data (neg) E7 O XVDD —
SD2_RX0 SerDes Rx Data (pos) A17 I SVDD —
SD2_RX1 SerDes Rx Data (pos) A16 I SVDD —
SD2_RX2 SerDes Rx Data (pos) A12 I SVDD —
SD2_RX3 SerDes Rx Data (pos) A11 I SVDD —
SD2_RX4 SerDes Rx Data (pos) A9 I SVDD —
SD2_RX5 SerDes Rx Data (pos) A8 I SVDD —
SD2_RX6 SerDes Rx Data (pos) A6 I SVDD —
SD2_RX7 SerDes Rx Data (pos) A5 I SVDD —
SD2_RX0_B SerDes Rx Data (neg) B17 I SVDD —
SD2_RX1_B SerDes Rx Data (neg) B16 I SVDD —
SD2_RX2_B SerDes Rx Data (neg) B12 I SVDD —
SD2_RX3_B SerDes Rx Data (neg) B11 I SVDD —
SD2_RX4_B SerDes Rx Data (neg) B9 I SVDD —
SD2_RX5_B SerDes Rx Data (neg) B8 I SVDD —
SD2_RX6_B SerDes Rx Data (neg) B6 I SVDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

24 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

SD2_RX7_B SerDes Rx Data (neg) B5 I SVDD —

SD2_REF1_CLK SerDes PLL 1 Reference B14 I SVDD —
Clock
SD2_REF1_CLK_B SerDes PLL 1 Reference A14 I SVDD —
Clock Complement
SD2_REF2_CLK SerDes PLL 2 Reference E5 I SVDD —
Clock
SD2_REF2_CLK_B SerDes PLL 2 Reference D5 I SVDD —
Clock Complement
SD2_IMP_CAL_TX SerDes Tx Impedance G10 I XVDD 11
Calibration
SD2_IMP_CAL_RX SerDes Rx Impedance G18 I SVDD 12
Calibration

CPRI Interface

CP_SYNC0 Sync AJ9 IO OVDD —

CP_SYNC1 Sync AF11 IO OVDD —
CP_SYNC2 Sync AG10 IO OVDD —
CP_SYNC3 Sync AH10 IO OVDD —
CP_SYNC4 Sync AL8 IO OVDD —
CP_SYNC5 Sync AK8 IO OVDD —
CP_SYNC6 Sync AK9 IO OVDD —
CP_SYNC7 Sync AH9 IO OVDD —
CP_RCLK0 Reconstructed Clock AL10 O OVDD 2
CP_RCLK1 Reconstructed Clock AL11 O OVDD 2
CP_RCLK0_B Reconstructed Clock AM10 O OVDD 2
Complement
CP_RCLK1_B Reconstructed Clock AM11 O OVDD 2
Complement
CP_LOS0 Loss Of Signal AM29 I DVDD 2, 29
CP_LOS1 Loss Of Signal AK27 I DVDD 2, 29
CP_LOS2 Loss Of Signal AM27 I DVDD 2, 29
CP_LOS3 Loss Of Signal AL28 I DVDD 2, 29
UART1_SOUT/GPIO1[15]/ Loss Of Signal AL29 I DVDD 2, 30
CP_LOS4
UART1_SIN/GPIO1[17]/ Loss Of Signal AM28 I DVDD 2, 30
CP_LOS5
UART1_RTS_B/GPIO1[19]/ Loss Of Signal AF24 I DVDD 2, 30
UART3_SOUT/CP_LOS6

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 25
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

UART1_CTS_B/GPIO1[21]/ Loss Of Signal AE24 I DVDD 2, 30

UART3_SIN/CP_LOS7

IEEE 1588 Interface

TSEC_1588_CLK_IN Clock In AM3 I OVDD 2

TSEC_1588_TRIG_IN1 Trigger In 1 AE9 I OVDD 2
TSEC_1588_TRIG_IN2 Trigger In 2 AF10 I OVDD 2
TSEC_1588_ALARM_OUT1 Alarm Out 1 AG9 O OVDD 2
TSEC_1588_ALARM_OUT2 Alarm Out 2 AH8 O OVDD 2
TSEC_1588_CLK_OUT Clock Out AE8 O OVDD 2
TSEC_1588_PULSE_OUT1 Pulse Out 1 AF9 O OVDD 2
TSEC_1588_PULSE_OUT2 Pulse Out 2 AK7 O OVDD 2

Ethernet MII Management Interface 1

EMI1_MDC Management Data Clock AJ26 O DVDD 2

EMI1_MDIO Management Data In/Out AK26 IO DVDD 27

Ethernet MII Management Interface 2

EMI2_MDC Management Data Clock AM8 O OVDD 13, 14

EMI2_MDIO Management Data In/Out AJ8 IO OVDD 13, 14

USB ULPI Interface

USB_D7 Data AK4 IO OVDD —

USB_D6 Data AM4 IO OVDD —
USB_D5 Data AK6 IO OVDD —
USB_D4 Data AK5 IO OVDD —
USB_D3 Data AJ6 IO OVDD —
USB_D2 Data AH7 IO OVDD —
USB_D1 Data AG7 IO OVDD —
USB_D0 Data AF8 IO OVDD —
USB_STP Stop Data AH6 O OVDD 2
USB_CLK Clock AL4 I OVDD 2
USB_NXT Next Data AL5 I OVDD 2
USB_DIR Data Direction AM5 I OVDD 2
IIC4_SDA/GPIO3[6]/EVT6_B/ Overcurrent Status on VBUS AE25 I DVDD —
USB_PWRFAULT line

DMA Interface

DMA1_DREQ0_B/GPIO3[0] DMA1 channel 0 request AM6 I OVDD 2

B4860 QorIQ Qonverge Data Sheet, Rev. 4

26 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

DMA1_DACK0_B/GPIO3[1]/ DMA1 channel 0 acknowledge AL7 O OVDD 2

EVT7_B/TMR6
DMA1_DDONE0_B/GPIO3[2]/ DMA1 channel 0 done AM7 O OVDD 2
EVT8_B/TMR7

GPIO Signals

ASLEEP/GPIO1[13]/ General Purpose Output AK10 O OVDD 2

CFG_XVDD_SEL
RTC/GPIO1[14] General Purpose Input / AM23 IO OVDD —
Output
UART1_SOUT/GPIO1[15]/ General Purpose Input / AL29 IO DVDD —
CP_LOS4 Output
UART2_SOUT/GPIO1[16] General Purpose Input / AF25 IO DVDD —
Output
UART1_SIN/GPIO1[17]/ General Purpose Input / AM28 IO DVDD —
CP_LOS5 Output
UART2_SIN/GPIO1[18] General Purpose Input / AH26 IO DVDD —
Output
UART1_RTS_B/GPIO1[19]/ General Purpose Input / AF24 IO DVDD —
UART3_SOUT/CP_LOS6 Output
UART2_RTS_B/GPIO1[20]/ General Purpose Input / AG25 IO DVDD —
UART4_SOUT Output
UART1_CTS_B/GPIO1[21]/ General Purpose Input / AE24 IO DVDD —
UART3_SIN/CP_LOS7 Output
UART2_CTS_B/GPIO1[22]/ General Purpose Input / AK28 IO DVDD —
UART4_SIN Output
IRQ03/GPIO1[23] General Purpose Input / AH23 IO OVDD —
Output
IRQ04/GPIO1[24] General Purpose Input / AH24 IO OVDD —
Output
IRQ05/GPIO1[25] General Purpose Input / AK23 IO OVDD —
Output
IRQ06/GPIO1[26]/TMR0 General Purpose Input / AK21 IO OVDD —
Output
IRQ07/GPIO1[27]/TMR1 General Purpose Input / AK24 IO OVDD —
Output
IRQ08/GPIO1[28]/TMR2 General Purpose Input / AK22 IO OVDD —
Output
IRQ09/GPIO1[29]/TMR3 General Purpose Input / AM24 IO OVDD —
Output
IRQ10/GPIO1[30]/TMR4 General Purpose Input / AJ24 IO OVDD —
Output

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 27
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

IRQ11/GPIO1[31]/TMR5 General Purpose Input / AL23 IO OVDD —

Output
SPI_CS0_B/GPIO2[0]/ General Purpose Input / AJ21 IO OVDD —
SDHC_DAT4 Output
SPI_CS1_B/GPIO2[1]/ General Purpose Input / AK19 IO OVDD —
SDHC_DAT5 Output
SPI_CS2_B/GPIO2[2]/ General Purpose Input / AH20 IO OVDD —
SDHC_DAT6 Output
SPI_CS3_B/GPIO2[3]/ General Purpose Input / AM20 IO OVDD —
SDHC_DAT7 Output
SDHC_CMD/GPIO2[4] General Purpose Input / AK20 IO OVDD —
Output
SDHC_DAT0/GPIO2[5] General Purpose Input / AG22 IO OVDD —
Output
SDHC_DAT1/GPIO2[6] General Purpose Input / AH21 IO OVDD —
Output
SDHC_DAT2/GPIO2[7] General Purpose Input / AL22 IO OVDD —
Output
SDHC_DAT3/GPIO2[8] General Purpose Input / AF21 IO OVDD —
Output
SDHC_CLK/GPIO2[9] General Purpose Input / AM22 IO OVDD —
Output
IFC_CS1_B/GPIO2[10] General Purpose Input / AK13 IO OVDD —
Output
IFC_CS2_B/GPIO2[11] General Purpose Input / AK14 IO OVDD —
Output
IFC_CS3_B/GPIO2[12] General Purpose Input / AJ18 IO OVDD —
Output
IFC_PAR0/GPIO2[13] General Purpose Input / AH13 IO OVDD —
Output
IFC_PAR1/GPIO2[14] General Purpose Input / AJ12 IO OVDD —
Output
IFC_A25/GPIO2[25]/ General Purpose Input / AJ14 IO OVDD —
IFC_RB2_B/IFC_FCTA2 Output
IFC_A26/GPIO2[26]/ General Purpose Input / AJ15 IO OVDD —
IFC_RB3_B/IFC_FCTA3 Output
IFC_A27/GPIO2[27] General Purpose Input / AJ17 IO OVDD —
Output
DMA1_DREQ0_B/GPIO3[0] General Purpose Input / AM6 IO OVDD —
Output

B4860 QorIQ Qonverge Data Sheet, Rev. 4

28 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

DMA1_DACK0_B/GPIO3[1]/ General Purpose Input / AL7 IO OVDD —

EVT7_B/TMR6 Output
DMA1_DDONE0_B/GPIO3[2]/ General Purpose Input / AM7 IO OVDD —
EVT8_B/TMR7 Output
IIC3_SCL/GPIO3[3] General Purpose Input / AM30 IO DVDD —
Output
IIC3_SDA/GPIO3[4] General Purpose Input / AK29 IO DVDD —
Output
IIC4_SCL/GPIO3[5]/EVT5_B General Purpose Input / AJ27 IO DVDD —
Output
IIC4_SDA/GPIO3[6]/EVT6_B/ General Purpose Input / AE25 IO DVDD —
USB_PWRFAULT Output

Timer Signals

IRQ06/GPIO1[26]/TMR0 Timer Input / Output AK21 IO OVDD —

IRQ07/GPIO1[27]/TMR1 Timer Input / Output AK24 IO OVDD —
IRQ08/GPIO1[28]/TMR2 Timer Input / Output AK22 IO OVDD —
IRQ09/GPIO1[29]/TMR3 Timer Input / Output AM24 IO OVDD —
IRQ10/GPIO1[30]/TMR4 Timer Input / Output AJ24 IO OVDD —
IRQ11/GPIO1[31]/TMR5 Timer Input / Output AL23 IO OVDD —
DMA1_DACK0_B/GPIO3[1]/ Timer Input / Output AL7 IO OVDD —
EVT7_B/TMR6
DMA1_DDONE0_B/GPIO3[2]/ Timer Input / Output AM7 IO OVDD —
EVT8_B/TMR7

Analog Signals

TD_ANODE Thermal diode anode J7 — Internal diode 31

TD_CATHODE Thermal diode cathode J8 — Internal diode 31
M1VREF SSTL 1.35/1.5 Reference AC9 — G1VDD/2 —
Voltage
M2VREF SSTL 1.35/1.5 Reference AC24 — G2VDD/2 —
Voltage
POVDD Fuse Programming Override H11 — POVDD 16
Supply

Power-on-Reset Configuration Signals

IFC_AD00/CFG_GPINPUT0 General-Purpose Input, AG12 I OVDD 22

application defined
IFC_AD01/CFG_GPINPUT1 General-Purpose Input, AG13 I OVDD 22
application defined

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 29
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

IFC_AD02/CFG_GPINPUT2 General-Purpose Input, AF13 I OVDD 22

application defined
IFC_AD03/CFG_GPINPUT3 General-Purpose Input, AF19 I OVDD 22
application defined
IFC_AD04/CFG_GPINPUT4 General-Purpose Input, AH15 I OVDD 22
application defined
IFC_AD05/CFG_GPINPUT5 General-Purpose Input, AL13 I OVDD 22
application defined
IFC_AD06/CFG_GPINPUT6 General-Purpose Input, AL17 I OVDD 22
application defined
IFC_AD07/CFG_GPINPUT7 General-Purpose Input, AK18 I OVDD 22
application defined
IFC_AD08/CFG_RCW_SRC0 RCW Source AF14 I OVDD 22
IFC_AD09/CFG_RCW_SRC1 RCW Source AF15 I OVDD 22
IFC_AD10/CFG_RCW_SRC2 RCW Source AF16 I OVDD 22
IFC_AD11/CFG_RCW_SRC3 RCW Source AH16 I OVDD 22
IFC_AD12/CFG_RCW_SRC4 RCW Source AF17 I OVDD 22
IFC_AD13/CFG_RCW_SRC5 RCW Source AF18 I OVDD 22
IFC_AD14/CFG_RCW_SRC6 RCW Source AH19 I OVDD 22
IFC_AD15/CFG_RCW_SRC7 RCW Source AG18 I OVDD 22
IFC_CLE/IFC_WBE1/ RCW Source AM14 I OVDD 22
CFG_RCW_SRC8
IFC_AVD/IFC_ALE/ Reset Sequence Pause AL19 I OVDD 22, 15
CFG_RSP_DIS Disable
IFC_A21/CFG_DRAM_TYPE DRAM Type Select AG19 I OVDD 22, 23
ASLEEP/GPIO1[13]/ XVDD Voltage Select AK10 I OVDD 2, 22,
CFG_XVDD_SEL 24
IFC_TE/CFG_IFC_TE IFC External Transceiver AM16 I OVDD 22, 25
Enable Pin Polarity Select

Power and Ground Signals

AVDD_CGA1 Cluster Group A PLL1 supply A3 — AVDD_CGA1 —

AVDD_CGA2 Cluster Group A PLL2 supply C1 — AVDD_CGA2 —
AVDD_CGB1 Cluster Group B PLL1 supply B2 — AVDD_CGB1 —
AVDD_CGB2 Cluster Group B PLL2 supply C3 — AVDD_CGB2 —
AVDD_PLAT Platform PLL supply B3 — AVDD_PLAT —
AVDD_DDR1 DDR1 PLL supply AC8 — AVDD_DDR1 —
AVDD_DDR2 DDR2 PLL supply AC25 — AVDD_DDR2 —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

30 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

AVDD_SRDS1_PLL1 SerDes1 PLL 1 supply H21 — AVDD_SRDS1_PLL1 —

AVDD_SRDS1_PLL2 SerDes1 PLL 2 supply H24 — AVDD_SRDS1_PLL2 —
AVDD_SRDS2_PLL1 SerDes2 PLL 1 supply H17 — AVDD_SRDS2_PLL1 —
AVDD_SRDS2_PLL2 SerDes2 PLL 2 supply H14 — AVDD_SRDS2_PLL2 —
SENSEVDD1 VDD sense pin 1 K9 — — 17
SENSEVDD2 VDD sense pin 2 AE12 — — 17
AGND_SRDS1_PLL1 SerDes1 PLL 1 GND H20 — — —
AGND_SRDS1_PLL2 SerDes1 PLL 2 GND G24 — — —
AGND_SRDS2_PLL1 SerDes2 PLL 1 GND H18 — — —
AGND_SRDS2_PLL2 SerDes2 PLL 2 GND G14 — — —
SENSEGND1 Vss sense pin 1 J9 — — 17
SENSEGND2 Vss sense pin 2 AD11 — — 17
OVDD General I/O supply AD13 — OVDD —
OVDD General I/O supply AD15 — OVDD —
OVDD General I/O supply AD17 — OVDD —
OVDD General I/O supply AE14 — OVDD —
OVDD General I/O supply AE16 — OVDD —
OVDD General I/O supply AE18 — OVDD —
DVDD UART/I2C/CPRI_LOS I/O AD19 — DVDD —
supply
DVDD UART/I2C/CPRI_LOS I/O AE20 — DVDD —
supply
G1VDD DDR supply for port 1 L8 — G1VDD —
G1VDD DDR supply for port 1 P7 — G1VDD —
G1VDD DDR supply for port 1 R9 — G1VDD —
G1VDD DDR supply for port 1 T1 — G1VDD —
G1VDD DDR supply for port 1 T10 — G1VDD —
G1VDD DDR supply for port 1 U3 — G1VDD —
G1VDD DDR supply for port 1 U6 — G1VDD —
G1VDD DDR supply for port 1 U9 — G1VDD —
G1VDD DDR supply for port 1 V3 — G1VDD —
G1VDD DDR supply for port 1 V6 — G1VDD —
G1VDD DDR supply for port 1 V10 — G1VDD —
G1VDD DDR supply for port 1 W1 — G1VDD —
G1VDD DDR supply for port 1 W9 — G1VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 31
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

G1VDD DDR supply for port 1 Y7 — G1VDD —

G1VDD DDR supply for port 1 Y10 — G1VDD —
G1VDD DDR supply for port 1 AA10 — G1VDD —
G2VDD DDR supply for port 2 L25 — G2VDD —
G2VDD DDR supply for port 2 P26 — G2VDD —
G2VDD DDR supply for port 2 R24 — G2VDD —
G2VDD DDR supply for port 2 T23 — G2VDD —
G2VDD DDR supply for port 2 T32 — G2VDD —
G2VDD DDR supply for port 2 U24 — G2VDD —
G2VDD DDR supply for port 2 U27 — G2VDD —
G2VDD DDR supply for port 2 U30 — G2VDD —
G2VDD DDR supply for port 2 V23 — G2VDD —
G2VDD DDR supply for port 2 V27 — G2VDD —
G2VDD DDR supply for port 2 V30 — G2VDD —
G2VDD DDR supply for port 2 W24 — G2VDD —
G2VDD DDR supply for port 2 W32 — G2VDD —
G2VDD DDR supply for port 2 Y23 — G2VDD —
G2VDD DDR supply for port 2 Y26 — G2VDD —
G2VDD DDR supply for port 2 AA23 — G2VDD —
SVDD SerDes core logic supply K15 — SVDD —
SVDD SerDes core logic supply K16 — SVDD —
SVDD SerDes core logic supply K17 — SVDD —
SVDD SerDes core logic supply K18 — SVDD —
SVDD SerDes core logic supply K19 — SVDD —
SVDD SerDes core logic supply K20 — SVDD —
SVDD SerDes core logic supply K21 — SVDD —
SVDD SerDes core logic supply K22 — SVDD —
SVDD SerDes core logic supply K23 — SVDD —
TH_VDD Thermal Monitor Unit supply J26 — THVDD 21
XVDD SerDes transceiver supply F9 — XVDD —
XVDD SerDes transceiver supply F12 — XVDD —
XVDD SerDes transceiver supply F15 — XVDD —
XVDD SerDes transceiver supply F17 — XVDD —
XVDD SerDes transceiver supply F19 — XVDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

32 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

XVDD SerDes transceiver supply F21 — XVDD —

XVDD SerDes transceiver supply F24 — XVDD —
XVDD SerDes transceiver supply F27 — XVDD —
XVDD SerDes transceiver supply F30 — XVDD —
QVDD Quiet I/O supply E2 — QVDD 19
QVDD Quiet I/O supply F2 — QVDD 19
QVDD Quiet I/O supply H9 — QVDD 7
VDD Core and Platform supply J10 — VDD —
VDD Core and Platform supply J12 — VDD —
VDD Core and Platform supply K11 — VDD —
VDD Core and Platform supply K13 — VDD —
VDD Core and Platform supply L10 — VDD —
VDD Core and Platform supply L12 — VDD —
VDD Core and Platform supply L14 — VDD —
VDD Core and Platform supply L16 — VDD —
VDD Core and Platform supply L18 — VDD —
VDD Core and Platform supply L20 — VDD —
VDD Core and Platform supply L22 — VDD —
VDD Core and Platform supply M11 — VDD —
VDD Core and Platform supply M13 — VDD —
VDD Core and Platform supply M15 — VDD —
VDD Core and Platform supply M17 — VDD —
VDD Core and Platform supply M19 — VDD —
VDD Core and Platform supply M21 — VDD —
VDD Core and Platform supply M23 — VDD —
VDD Core and Platform supply N10 — VDD —
VDD Core and Platform supply N12 — VDD —
VDD Core and Platform supply N14 — VDD —
VDD Core and Platform supply N16 — VDD —
VDD Core and Platform supply N18 — VDD —
VDD Core and Platform supply N20 — VDD —
VDD Core and Platform supply N22 — VDD —
VDD Core and Platform supply P11 — VDD —
VDD Core and Platform supply P13 — VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 33
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

VDD Core and Platform supply P15 — VDD —

VDD Core and Platform supply P17 — VDD —
VDD Core and Platform supply P19 — VDD —
VDD Core and Platform supply P21 — VDD —
VDD Core and Platform supply P23 — VDD —
VDD Core and Platform supply R10 — VDD —
VDD Core and Platform supply R12 — VDD —
VDD Core and Platform supply R14 — VDD —
VDD Core and Platform supply R16 — VDD —
VDD Core and Platform supply R18 — VDD —
VDD Core and Platform supply R20 — VDD —
VDD Core and Platform supply R22 — VDD —
VDD Core and Platform supply T11 — VDD —
VDD Core and Platform supply T13 — VDD —
VDD Core and Platform supply T15 — VDD —
VDD Core and Platform supply T17 — VDD —
VDD Core and Platform supply T19 — VDD —
VDD Core and Platform supply T21 — VDD —
VDD Core and Platform supply U12 — VDD —
VDD Core and Platform supply U14 — VDD —
VDD Core and Platform supply U16 — VDD —
VDD Core and Platform supply U18 — VDD —
VDD Core and Platform supply U20 — VDD —
VDD Core and Platform supply U22 — VDD —
VDD Core and Platform supply V11 — VDD —
VDD Core and Platform supply V13 — VDD —
VDD Core and Platform supply V15 — VDD —
VDD Core and Platform supply V17 — VDD —
VDD Core and Platform supply V19 — VDD —
VDD Core and Platform supply V21 — VDD —
VDD Core and Platform supply W12 — VDD —
VDD Core and Platform supply W14 — VDD —
VDD Core and Platform supply W16 — VDD —
VDD Core and Platform supply W18 — VDD —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

34 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

VDD Core and Platform supply W20 — VDD —

VDD Core and Platform supply W22 — VDD —
VDD Core and Platform supply Y11 — VDD —
VDD Core and Platform supply Y13 — VDD —
VDD Core and Platform supply Y15 — VDD —
VDD Core and Platform supply Y17 — VDD —
VDD Core and Platform supply Y19 — VDD —
VDD Core and Platform supply Y21 — VDD —
VDD Core and Platform supply AA12 — VDD —
VDD Core and Platform supply AA14 — VDD —
VDD Core and Platform supply AA16 — VDD —
VDD Core and Platform supply AA18 — VDD —
VDD Core and Platform supply AA20 — VDD —
VDD Core and Platform supply AA22 — VDD —
VDD Core and Platform supply AB11 — VDD —
VDD Core and Platform supply AB13 — VDD —
VDD Core and Platform supply AB15 — VDD —
VDD Core and Platform supply AB17 — VDD —
VDD Core and Platform supply AB19 — VDD —
VDD Core and Platform supply AB21 — VDD —
VDD Core and Platform supply AC12 — VDD —
VDD Core and Platform supply AC14 — VDD —
VDD Core and Platform supply AC16 — VDD —
VDD Core and Platform supply AC18 — VDD —
VDD Core and Platform supply AC20 — VDD —
VDD Core and Platform supply AC22 — VDD —
GND GND A2 — — —
GND GND B1 — — —
GND GND C2 — — —
GND GND D1 — — —
GND GND D3 — — —
GND GND F3 — — —
GND GND G1 — — —
GND GND G6 — — —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 35
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

GND GND G7 — — 20
GND GND G8 — — 20
GND GND G32 — — —
GND GND H4 — — —
GND GND H8 — — 20
GND GND H29 — — —
GND GND J6 — — —
GND GND J11 — — —
GND GND J13 — — —
GND GND J25 — — —
GND GND J27 — — —
GND GND K2 — — —
GND GND K10 — — —
GND GND K12 — — —
GND GND K14 — — —
GND GND K24 — — 20
GND GND K31 — — —
GND GND L4 — — —
GND GND L11 — — —
GND GND L13 — — —
GND GND L15 — — —
GND GND L17 — — —
GND GND L19 — — —
GND GND L21 — — —
GND GND L23 — — —
GND GND L29 — — —
GND GND M6 — — —
GND GND M9 — — —
GND GND M10 — — —
GND GND M12 — — —
GND GND M14 — — —
GND GND M16 — — —
GND GND M18 — — —
GND GND M20 — — —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

36 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

GND GND M22 — — —

GND GND M24 — — —
GND GND M27 — — —
GND GND N2 — — —
GND GND N11 — — —
GND GND N13 — — —
GND GND N15 — — —
GND GND N17 — — —
GND GND N19 — — —
GND GND N21 — — —
GND GND N23 — — —
GND GND N31 — — —
GND GND P4 — — —
GND GND P10 — — —
GND GND P12 — — —
GND GND P14 — — —
GND GND P16 — — —
GND GND P18 — — —
GND GND P20 — — —
GND GND P22 — — —
GND GND P29 — — —
GND GND R2 — — —
GND GND R6 — — —
GND GND R11 — — —
GND GND R13 — — —
GND GND R15 — — —
GND GND R17 — — —
GND GND R19 — — —
GND GND R21 — — —
GND GND R23 — — —
GND GND R27 — — —
GND GND R31 — — —
GND GND T12 — — —
GND GND T14 — — —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 37
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

GND GND T16 — — —

GND GND T18 — — —
GND GND T20 — — —
GND GND T22 — — —
GND GND U10 — — —
GND GND U11 — — —
GND GND U13 — — —
GND GND U15 — — —
GND GND U17 — — —
GND GND U19 — — —
GND GND U21 — — —
GND GND U23 — — —
GND GND V12 — — —
GND GND V14 — — —
GND GND V16 — — —
GND GND V18 — — —
GND GND V20 — — —
GND GND V22 — — —
GND GND W10 — — —
GND GND W11 — — —
GND GND W13 — — —
GND GND W15 — — —
GND GND W17 — — —
GND GND W19 — — —
GND GND W21 — — —
GND GND W23 — — —
GND GND Y2 — — —
GND GND Y4 — — —
GND GND Y12 — — —
GND GND Y14 — — —
GND GND Y16 — — —
GND GND Y18 — — —
GND GND Y20 — — —
GND GND Y22 — — —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

38 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

GND GND Y29 — — —

GND GND Y31 — — —
GND GND AA11 — — —
GND GND AA13 — — —
GND GND AA15 — — —
GND GND AA17 — — —
GND GND AA19 — — —
GND GND AA21 — — —
GND GND AB2 — — —
GND GND AB5 — — —
GND GND AB8 — — —
GND GND AB9 — — —
GND GND AB10 — — —
GND GND AB12 — — —
GND GND AB14 — — —
GND GND AB16 — — —
GND GND AB18 — — —
GND GND AB20 — — —
GND GND AB22 — — —
GND GND AB23 — — —
GND GND AB24 — — —
GND GND AB25 — — —
GND GND AB28 — — —
GND GND AB31 — — —
GND GND AC7 — — —
GND GND AC10 — — —
GND GND AC11 — — —
GND GND AC13 — — —
GND GND AC15 — — —
GND GND AC17 — — —
GND GND AC19 — — —
GND GND AC21 — — —
GND GND AC23 — — —
GND GND AC26 — — —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 39
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

GND GND AD4 — — —

GND GND AD8 — — —
GND GND AD9 — — —
GND GND AD14 — — —
GND GND AD16 — — —
GND GND AD18 — — —
GND GND AD20 — — —
GND GND AD22 — — —
GND GND AD24 — — —
GND GND AD25 — — —
GND GND AD29 — — —
GND GND AE2 — — —
GND GND AE13 — — —
GND GND AE15 — — —
GND GND AE17 — — —
GND GND AE19 — — —
GND GND AE21 — — —
GND GND AE22 — — —
GND GND AE31 — — —
GND GND AF5 — — —
GND GND AF28 — — —
GND GND AG8 — — —
GND GND AG11 — — —
GND GND AG14 — — —
GND GND AG17 — — —
GND GND AG20 — — —
GND GND AG23 — — —
GND GND AG26 — — —
GND GND AH2 — — —
GND GND AH31 — — —
GND GND AJ5 — — —
GND GND AJ7 — — —
GND GND AJ10 — — —
GND GND AJ13 — — —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

40 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

GND GND AJ16 — — —

GND GND AJ19 — — —
GND GND AJ22 — — —
GND GND AJ25 — — —
GND GND AJ28 — — —
GND GND AL1 — — —
GND GND AL3 — — —
GND GND AL6 — — —
GND GND AL9 — — —
GND GND AL12 — — —
GND GND AL15 — — —
GND GND AL18 — — —
GND GND AL21 — — —
GND GND AL24 — — —
GND GND AL27 — — —
GND GND AL30 — — —
GND GND AL32 — — —
GND GND AM2 — — —
GND GND AM31 — — —
XGND SerDes transceiver GND D6 — — —
XGND SerDes transceiver GND D9 — — —
XGND SerDes transceiver GND D12 — — —
XGND SerDes transceiver GND D15 — — —
XGND SerDes transceiver GND D18 — — —
XGND SerDes transceiver GND D21 — — —
XGND SerDes transceiver GND D24 — — —
XGND SerDes transceiver GND D27 — — —
XGND SerDes transceiver GND D30 — — —
XGND SerDes transceiver GND E6 — — —
XGND SerDes transceiver GND E9 — — —
XGND SerDes transceiver GND E12 — — —
XGND SerDes transceiver GND E15 — — —
XGND SerDes transceiver GND E18 — — —
XGND SerDes transceiver GND E21 — — —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 41
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

XGND SerDes transceiver GND E24 — — —

XGND SerDes transceiver GND E27 — — —
XGND SerDes transceiver GND E30 — — —
XGND SerDes transceiver GND F18 — — —
SGND SerDes core logic GND A4 — — —
SGND SerDes core logic GND A7 — — —
SGND SerDes core logic GND A10 — — —
SGND SerDes core logic GND A13 — — —
SGND SerDes core logic GND A15 — — —
SGND SerDes core logic GND A18 — — —
SGND SerDes core logic GND A21 — — —
SGND SerDes core logic GND A23 — — —
SGND SerDes core logic GND A25 — — —
SGND SerDes core logic GND A28 — — —
SGND SerDes core logic GND A31 — — —
SGND SerDes core logic GND B4 — — —
SGND SerDes core logic GND B7 — — —
SGND SerDes core logic GND B10 — — —
SGND SerDes core logic GND B13 — — —
SGND SerDes core logic GND B15 — — —
SGND SerDes core logic GND B18 — — —
SGND SerDes core logic GND B21 — — —
SGND SerDes core logic GND B23 — — —
SGND SerDes core logic GND B25 — — —
SGND SerDes core logic GND B28 — — —
SGND SerDes core logic GND B31 — — —
SGND SerDes core logic GND C4 — — —
SGND SerDes core logic GND C5 — — —
SGND SerDes core logic GND C6 — — —
SGND SerDes core logic GND C7 — — —
SGND SerDes core logic GND C8 — — —
SGND SerDes core logic GND C9 — — —
SGND SerDes core logic GND C10 — — —
SGND SerDes core logic GND C11 — — —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

42 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

SGND SerDes core logic GND C12 — — —

SGND SerDes core logic GND C13 — — —
SGND SerDes core logic GND C14 — — —
SGND SerDes core logic GND C15 — — —
SGND SerDes core logic GND C16 — — —
SGND SerDes core logic GND C17 — — —
SGND SerDes core logic GND C18 — — —
SGND SerDes core logic GND C19 — — —
SGND SerDes core logic GND C20 — — —
SGND SerDes core logic GND C21 — — —
SGND SerDes core logic GND C22 — — —
SGND SerDes core logic GND C23 — — —
SGND SerDes core logic GND C24 — — —
SGND SerDes core logic GND C25 — — —
SGND SerDes core logic GND C26 — — —
SGND SerDes core logic GND C27 — — —
SGND SerDes core logic GND C28 — — —
SGND SerDes core logic GND C29 — — —
SGND SerDes core logic GND C30 — — —
SGND SerDes core logic GND D4 — — —
SGND SerDes core logic GND D31 — — —
SGND SerDes core logic GND D32 — — —
SGND SerDes core logic GND E4 — — —
SGND SerDes core logic GND F5 — — —
SGND SerDes core logic GND F6 — — —
SGND SerDes core logic GND F7 — — —
SGND SerDes core logic GND F8 — — —
SGND SerDes core logic GND F10 — — —
SGND SerDes core logic GND F11 — — —
SGND SerDes core logic GND F13 — — —
SGND SerDes core logic GND F14 — — —
SGND SerDes core logic GND F16 — — —
SGND SerDes core logic GND F20 — — —
SGND SerDes core logic GND F22 — — —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 43
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

SGND SerDes core logic GND F23 — — —

SGND SerDes core logic GND F25 — — —
SGND SerDes core logic GND F26 — — —
SGND SerDes core logic GND F28 — — —
SGND SerDes core logic GND F29 — — —
SGND SerDes core logic GND F31 — — —
SGND SerDes core logic GND F32 — — —
SGND SerDes core logic GND G9 — — —
SGND SerDes core logic GND G11 — — —
SGND SerDes core logic GND G12 — — —
SGND SerDes core logic GND G15 — — —
SGND SerDes core logic GND G17 — — —
SGND SerDes core logic GND G19 — — —
SGND SerDes core logic GND G21 — — —
SGND SerDes core logic GND G23 — — —
SGND SerDes core logic GND G27 — — —
SGND SerDes core logic GND H10 — — —
SGND SerDes core logic GND H12 — — —
SGND SerDes core logic GND H13 — — —
SGND SerDes core logic GND H19 — — —
SGND SerDes core logic GND H25 — — —
SGND SerDes core logic GND H26 — — —
SGND SerDes core logic GND J14 — — —
SGND SerDes core logic GND J15 — — —
SGND SerDes core logic GND J16 — — —
SGND SerDes core logic GND J17 — — —
SGND SerDes core logic GND J18 — — —
SGND SerDes core logic GND J19 — — —
SGND SerDes core logic GND J20 — — —
SGND SerDes core logic GND J21 — — —
SGND SerDes core logic GND J22 — — —
SGND SerDes core logic GND J23 — — —
SGND SerDes core logic GND J24 — — —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

44 NXP Semiconductors
 Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

No connection pins

NC_D2 No Connection D2 — — 18
NC_E3 No Connection E3 — — 18
NC_F4 No Connection F4 — — 18
NC_G5 No Connection G5 — — 18
NC_G13 No Connection G13 — — 18
NC_G16 No Connection G16 — — 18
NC_G22 No Connection G22 — — 18
NC_G25 No Connection G25 — — 18
NC_G28 No Connection G28 — — 18
NC_H7 No Connection H7 — — 18
NC_H15 No Connection H15 — — 18
NC_H16 No Connection H16 — — 18
NC_H22 No Connection H22 — — 18
NC_H23 No Connection H23 — — 18
NC_AD10 No Connection AD10 — — 18
NC_AD23 No Connection AD23 — — 18
NC_DET Orientation Detect B32 — — 18

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 45
Pin assignments

Table 1. Pinout list by bus (continued)

Package Power
Signal Signal Description Pin Type Notes
Pin Supply

1. MDIC[0] is grounded through a 237 Ω for B4860 Rev. 1 and 187 Ω for B4860 Rev. 2 precision 1% resistor and MDIC[1] is
connected to GnVDD through a 237 Ω for B4860 Rev. 1 and 187 Ω for B4860 Rev. 2 precision 1% resistor. For either full or
half driver strength calibration of DDR IOs, use the same MDIC resistor value of 237 Ω for B4860 Rev. 1 and 187 Ω for B4860
Rev. 2. The memory controller register setting can be used to determine automatic calibration is done to full or half-drive
strength. These pins are used for automatic calibration of the DDR3/DDR3L IOs.
2. Functionally, this pin is an output or an input, but structurally it is an I/O because it either samples configuration input during
reset, is a muxed pin, or it has other manufacturing test functions. Thus, this pin is described as an I/O for boundary scan.
3. This pin is an open drain signal. Recommend that a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD.
4. When used as an I2C interface, this pin functions as an open drain I/O. Recommend that a pull-up resistor (1 kΩ) be placed
on this pin to DVDD.
5. When used as an IRQ_OUT_B pin, this pin functions as an open drain I/O. Recommend that a weak pull-up resistor
(2–10 kΩ) be placed on this pin to OVDD.
6. See Section 3.5, “Connection recommendations for unused pins,” for additional details on this signal.
7. QVDD is an internal IO quiet power domain. Externally, it should be connected to the OVDD supply.
8. Pin must NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or if there are any externally
connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, external pull-up is required
to drive this pin to a safe state during reset.
9. Pin has a weak (~20 kΩ) internal pull-up P-FET, which is always enabled.
10.This output is actively driven during reset rather than being tristated during reset.
11.This pin requires a 698 Ω (1% accuracy) pull-up to XVDD.
12.This pin requires a 200 Ω (1% accuracy) pull-up to SVDD.
13.These pins should be pulled up to 1.2 V through a 180 Ω (1% accuracy) resistor for EMI2_MDC and 330 Ω (1% accuracy)
resistor for EMI2_MDIO.
14.Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage
levels. OVDD must be powered to use this interface.
15.CFG_RSP_DIS configuration pin allows the B4860 to enter debug mode immediately after reset. The board should be
configured (by some FPGA/dip-switch) to drive the CFG_RSP_DIS pin during PORESET sequence to logic 0 or logic 1, with
a default level of logic 1, and with the timing as defined for all other CFG pins. After POR completion, the pin is used as
IFC_AVD function.
16.See Section 2.2, “Power sequencing,” and Section 5, “Security fuse processor,” for additional details on this signal.
17.These pins are connected to the same global power and ground (VDD and GND) nets internally and may be connected as
a differential pair to be used by the voltage regulators with remote sense function.
18.Do not connect. These pins should be left floating.
19.The QVDD supply to these pins is not an actual supply pin, but a functional pin requires the QVDD supply connectivity. Pin
must be connected with a pull up resistor of 10 kΩ.
20.The GND supply to these pins is not an actual supply pin, but a functional pin requires the GND supply connectivity. Pin
must be connected with a pull down resistor of 10 kΩ.
21.The Thermal Monitoring Unit (TMU) is defeatured on this device. TH_VDD should be connected to an OVDD supply.
22.This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor
is in its reset state. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor. However, when
the signal is intended to be high after reset, and when there is a device on the net that might pull down the value of the net
at reset, a pull-up or active driver is needed.
23.CFG_DRAM_TYPE configuration pin selects the DRAM type: “0”—DDR3 (IO is 1.5 V), “1”—DDR3L (IO is 1.35 V)
24.CFG_XVDD_SEL configuration pin selects the XVDD voltage: “0”—XVDD is 1.5 V, “1”—XVDD is 1.35 V.
25.CFG_IFC_TE configuration pin selects the IFC External Transceiver Enable Pin Polarity: “0”—Default value of IFC’s
CSPR0[TE] is logic 1, “1”—Default value of IFC’s CSPR0[TE] is logic 0.
26.Recommend that a weak pull-up resistor (4.7-kΩ) be placed on this pin to the respective power supply.
27.Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the respective power supply.
28.Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply.
29.Must be pulled down externally (for any active CPRI lane that is not connected to an SFP).
30.When configured as DUART (using RCW[UART_EXT] bits), pins are internally pulled down. When the pins are configured
as CP_LOSi, they should be pulled down externally for any active CPRI lane that is not connected to an SFP.
31.When the thermal diode is not used, its pins (anode, cathode) should be connected to GND.
32.If used as an SDHC signal, pull-up 10 to 100 kΩ. to the respective IO supply.

B4860 QorIQ Qonverge Data Sheet, Rev. 4

46 NXP Semiconductors
 Pin assignments

WARNING
See Section 3.5, “Connection recommendations for unused pins,” for additional details on
properly connecting these pins for specific applications.

1.3 Pinout list by package pin number

This table provides the pinout list for the chip sorted by package pin number.
Table 2. Pinout by package pin number

Package pin Package pin

Package pin name Package Pin Name
number number

A1 — B1 GND
A2 GND B2 AVDD_CGB1
A3 AVDD_CGA1 B3 AVDD_PLAT
A4 SGND B4 SGND
A5 SD2_RX7 B5 SD2_RX7_B
A6 SD2_RX6 B6 SD2_RX6_B
A7 SGND B7 SGND
A8 SD2_RX5 B8 SD2_RX5_B
A9 SD2_RX4 B9 SD2_RX4_B
A10 SGND B10 SGND
A11 SD2_RX3 B11 SD2_RX3_B
A12 SD2_RX2 B12 SD2_RX2_B
A13 SGND B13 SGND
A14 SD2_REF1_CLK_B B14 SD2_REF1_CLK
A15 SGND B15 SGND
A16 SD2_RX1 B16 SD2_RX1_B
A17 SD2_RX0 B17 SD2_RX0_B
A18 SGND B18 SGND
A19 SD1_RX0 B19 SD1_RX0_B
A20 SD1_RX1 B20 SD1_RX1_B
A21 SGND B21 SGND
A22 SD1_REF1_CLK_B B22 SD1_REF1_CLK
A23 SGND B23 SGND
A24 SD1_RX2 B24 SD1_RX2_B
A25 SGND B25 SGND
A26 SD1_RX3 B26 SD1_RX3_B
A27 SD1_RX4 B27 SD1_RX4_B

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 47
Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

A28 SGND B28 SGND

A29 SD1_RX5 B29 SD1_RX5_B
A30 SD1_RX6 B30 SD1_RX6_B
A31 SGND B31 SGND
A32 — B32 NC_DET
C1 AVDD_CGA2 D1 GND
C2 GND D2 NC_D2
C3 AVDD_CGB2 D3 GND
C4 SGND D4 SGND
C5 SGND D5 SD2_REF2_CLK_B
C6 SGND D6 XGND
C7 SGND D7 SD2_TX7
C8 SGND D8 SD2_TX6
C9 SGND D9 XGND
C10 SGND D10 SD2_TX5
C11 SGND D11 SD2_TX4
C12 SGND D12 XGND
C13 SGND D13 SD2_TX3
C14 SGND D14 SD2_TX2
C15 SGND D15 XGND
C16 SGND D16 SD2_TX1
C17 SGND D17 SD2_TX0
C18 SGND D18 XGND
C19 SGND D19 SD1_TX0
C20 SGND D20 SD1_TX1
C21 SGND D21 XGND
C22 SGND D22 SD1_TX2
C23 SGND D23 SD1_TX3
C24 SGND D24 XGND
C25 SGND D25 SD1_TX4
C26 SGND D26 SD1_TX5
C27 SGND D27 XGND
C28 SGND D28 SD1_TX6
C29 SGND D29 SD1_TX7

B4860 QorIQ Qonverge Data Sheet, Rev. 4

48 NXP Semiconductors
 Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

C30 SGND D30 XGND

C31 SD1_RX7_B D31 SGND
C32 SD1_RX7 D32 SGND
E1 PORESET_B F1 SYSCLK
E2 QVDD F2 QVDD
E3 NC_E3 F3 GND
E4 SGND F4 NC_F4
E5 SD2_REF2_CLK F5 SGND
E6 XGND F6 SGND
E7 SD2_TX7_B F7 SGND
E8 SD2_TX6_B F8 SGND
E9 XGND F9 XVDD
E10 SD2_TX5_B F10 SGND
E11 SD2_TX4_B F11 SGND
E12 XGND F12 XVDD
E13 SD2_TX3_B F13 SGND
E14 SD2_TX2_B F14 SGND
E15 XGND F15 XVDD
E16 SD2_TX1_B F16 SGND
E17 SD2_TX0_B F17 XVDD
E18 XGND F18 XGND
E19 SD1_TX0_B F19 XVDD
E20 SD1_TX1_B F20 SGND
E21 XGND F21 XVDD
E22 SD1_TX2_B F22 SGND
E23 SD1_TX3_B F23 SGND
E24 XGND F24 XVDD
E25 SD1_TX4_B F25 SGND
E26 SD1_TX5_B F26 SGND
E27 XGND F27 XVDD
E28 SD1_TX6_B F28 SGND
E29 SD1_TX7_B F29 SGND
E30 XGND F30 XVDD
E31 SD1_REF2_CLK F31 SGND

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 49
Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

E32 SD1_REF2_CLK_B F32 SGND

G1 GND H1 D1_MDQ51
G2 D1_MDQ59 H2 D1_MDQ52
G3 D1_MDQ56 H3 D1_MDQ55
G4 D1_MDQ58 H4 GND
G5 NC_G5 H5 D1_MDQ60
G6 GND H6 D1_MDQ63
G7 GND H7 NC_H7
G8 GND H8 GND
G9 SGND H9 QVDD
G10 SD2_IMP_CAL_TX H10 SGND
G11 SGND H11 POVDD
G12 SGND H12 SGND
G13 NC_G13 H13 SGND
G14 AGND_SRDS2_PLL2 H14 AVDD_SRDS2_PLL2
G15 SGND H15 NC_H15
G16 NC_G16 H16 NC_H16
G17 SGND H17 AVDD_SRDS2_PLL1
G18 SD2_IMP_CAL_RX H18 AGND_SRDS2_PLL1
G19 SGND H19 SGND
G20 SD1_IMP_CAL_RX H20 AGND_SRDS1_PLL1
G21 SGND H21 AVDD_SRDS1_PLL1
G22 NC_G22 H22 NC_H22
G23 SGND H23 NC_H23
G24 AGND_SRDS1_PLL2 H24 AVDD_SRDS1_PLL2
G25 NC_G25 H25 SGND
G26 SD1_IMP_CAL_TX H26 SGND
G27 SGND H27 D2_MDQ63
G28 NC_G28 H28 D2_MDQ60
G29 D2_MDQ58 H29 GND
G30 D2_MDQ56 H30 D2_MDQ55
G31 D2_MDQ59 H31 D2_MDQ52
G32 GND H32 D2_MDQ51
J1 D1_MDQS6 K1 D1_MDQ50

B4860 QorIQ Qonverge Data Sheet, Rev. 4

50 NXP Semiconductors
 Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

J2 D1_MDQS6_B K2 GND
J3 D1_MDM6 K3 D1_MDQ53
J4 D1_MDQS7 K4 D1_MDQ54
J5 D1_MDQS7_B K5 D1_MDM7
J6 GND K6 D1_MDQ57
J7 TD_ANODE K7 D1_MDQ61
J8 TD_CATHODE K8 D1_MODT1
J9 SENSEGND1 K9 SENSEVDD1
J10 VDD K10 GND
J11 GND K11 VDD
J12 VDD K12 GND
J13 GND K13 VDD
J14 SGND K14 GND
J15 SGND K15 SVDD
J16 SGND K16 SVDD
J17 SGND K17 SVDD
J18 SGND K18 SVDD
J19 SGND K19 SVDD
J20 SGND K20 SVDD
J21 SGND K21 SVDD
J22 SGND K22 SVDD
J23 SGND K23 SVDD
J24 SGND K24 GND
J25 GND K25 D2_MODT1
J26 TH_VDD K26 D2_MDQ61
J27 GND K27 D2_MDQ57
J28 D2_MDQS7_B K28 D2_MDM7
J29 D2_MDQS7 K29 D2_MDQ54
J30 D2_MDM6 K30 D2_MDQ53
J31 D2_MDQS6_B K31 GND
J32 D2_MDQS6 K32 D2_MDQ50
L1 D1_MDQ48 M1 D1_MDQ35
L2 D1_MDQ49 M2 D1_MDQ34
L3 D1_MDQ43 M3 D1_MDQ37

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 51
Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

L4 GND M4 D1_MDQ41
L5 D1_MDQ47 M5 D1_MDQ42
L6 D1_MDQ45 M6 GND
L7 D1_MDQ62 M7 D1_MODT0
L8 G1VDD M8 D1_MODT3
L9 D1_MCS3_B M9 GND
L10 VDD M10 GND
L11 GND M11 VDD
L12 VDD M12 GND
L13 GND M13 VDD
L14 VDD M14 GND
L15 GND M15 VDD
L16 VDD M16 GND
L17 GND M17 VDD
L18 VDD M18 GND
L19 GND M19 VDD
L20 VDD M20 GND
L21 GND M21 VDD
L22 VDD M22 GND
L23 GND M23 VDD
L24 D2_MCS3_B M24 GND
L25 G2VDD M25 D2_MODT3
L26 D2_MDQ62 M26 D2_MODT0
L27 D2_MDQ45 M27 GND
L28 D2_MDQ47 M28 D2_MDQ42
L29 GND M29 D2_MDQ41
L30 D2_MDQ43 M30 D2_MDQ37
L31 D2_MDQ49 M31 D2_MDQ34
L32 D2_MDQ48 M32 D2_MDQ35
N1 D1_MDQ33 P1 D1_MDQS4
N2 GND P2 D1_MDQS4_B
N3 D1_MDM4 P3 D1_MDQ39
N4 D1_MDQS5 P4 GND
N5 D1_MDQS5_B P5 D1_MDQ40

B4860 QorIQ Qonverge Data Sheet, Rev. 4

52 NXP Semiconductors
 Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

N6 D1_MDM5 P6 D1_MDQ46
N7 D1_MWE_B P7 G1VDD
N8 D1_MODT2 P8 D1_MRAS_B
N9 D1_MA13 P9 D1_MCS1_B
N10 VDD P10 GND
N11 GND P11 VDD
N12 VDD P12 GND
N13 GND P13 VDD
N14 VDD P14 GND
N15 GND P15 VDD
N16 VDD P16 GND
N17 GND P17 VDD
N18 VDD P18 GND
N19 GND P19 VDD
N20 VDD P20 GND
N21 GND P21 VDD
N22 VDD P22 GND
N23 GND P23 VDD
N24 D2_MA13 P24 D2_MCS1_B
N25 D2_MODT2 P25 D2_MRAS_B
N26 D2_MWE_B P26 G2VDD
N27 D2_MDM5 P27 D2_MDQ46
N28 D2_MDQS5_B P28 D2_MDQ40
N29 D2_MDQS5 P29 GND
N30 D2_MDM4 P30 D2_MDQ39
N31 GND P31 D2_MDQS4_B
N32 D2_MDQ33 P32 D2_MDQS4
R1 D1_MDQ32 T1 G1VDD
R2 GND T2 D1_MA05
R3 D1_MDQ36 T3 D1_MAPAR_ERR_B
R4 D1_MDQ38 T4 D1_MA02
R5 D1_MDQ44 T5 D1_MBA1
R6 GND T6 D1_MA01
R7 D1_MCS2_B T7 D1_MAPAR_OUT

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 53
Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

R8 D1_MCAS_B T8 D1_MBA0
R9 G1VDD T9 D1_MCS0_B
R10 VDD T10 G1VDD
R11 GND T11 VDD
R12 VDD T12 GND
R13 GND T13 VDD
R14 VDD T14 GND
R15 GND T15 VDD
R16 VDD T16 GND
R17 GND T17 VDD
R18 VDD T18 GND
R19 GND T19 VDD
R20 VDD T20 GND
R21 GND T21 VDD
R22 VDD T22 GND
R23 GND T23 G2VDD
R24 G2VDD T24 D2_MCS0_B
R25 D2_MCAS_B T25 D2_MBA0
R26 D2_MCS2_B T26 D2_MAPAR_OUT
R27 GND T27 D2_MA01
R28 D2_MDQ44 T28 D2_MBA1
R29 D2_MDQ38 T29 D2_MA02
R30 D2_MDQ36 T30 D2_MAPAR_ERR_B
R31 GND T31 D2_MA05
R32 D2_MDQ32 T32 G2VDD
U1 D1_MCK2 V1 D1_MCK0
U2 D1_MCK2_B V2 D1_MCK0_B
U3 G1VDD V3 G1VDD
U4 D1_MCK3 V4 D1_MCK1
U5 D1_MCK3_B V5 D1_MCK1_B
U6 G1VDD V6 G1VDD
U7 D1_MA00 V7 D1_MDIC1
U8 D1_MA10 V8 D1_MA04
U9 G1VDD V9 D1_MA03

B4860 QorIQ Qonverge Data Sheet, Rev. 4

54 NXP Semiconductors
 Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

U10 GND V10 G1VDD

U11 GND V11 VDD
U12 VDD V12 GND
U13 GND V13 VDD
U14 VDD V14 GND
U15 GND V15 VDD
U16 VDD V16 GND
U17 GND V17 VDD
U18 VDD V18 GND
U19 GND V19 VDD
U20 VDD V20 GND
U21 GND V21 VDD
U22 VDD V22 GND
U23 GND V23 G2VDD
U24 G2VDD V24 D2_MA03
U25 D2_MA10 V25 D2_MA04
U26 D2_MA00 V26 D2_MDIC1
U27 G2VDD V27 G2VDD
U28 D2_MCK3_B V28 D2_MCK1_B
U29 D2_MCK3 V29 D2_MCK1
U30 G2VDD V30 G2VDD
U31 D2_MCK2_B V31 D2_MCK0_B
U32 D2_MCK2 V32 D2_MCK0
W1 G1VDD Y1 D1_MECC3
W2 D1_MDIC0 Y2 GND
W3 D1_MA08 Y3 D1_MECC7
W4 D1_MA06 Y4 GND
W5 D1_MA07 Y5 D1_MECC0
W6 D1_MA09 Y6 D1_MCKE3
W7 D1_MA12 Y7 G1VDD
W8 D1_MA11 Y8 D1_MCKE2
W9 G1VDD Y9 D1_MA15
W10 GND Y10 G1VDD
W11 GND Y11 VDD

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 55
Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

W12 VDD Y12 GND

W13 GND Y13 VDD
W14 VDD Y14 GND
W15 GND Y15 VDD
W16 VDD Y16 GND
W17 GND Y17 VDD
W18 VDD Y18 GND
W19 GND Y19 VDD
W20 VDD Y20 GND
W21 GND Y21 VDD
W22 VDD Y22 GND
W23 GND Y23 G2VDD
W24 G2VDD Y24 D2_MA15
W25 D2_MA11 Y25 D2_MCKE2
W26 D2_MA12 Y26 G2VDD
W27 D2_MA09 Y27 D2_MCKE3
W28 D2_MA07 Y28 D2_MECC0
W29 D2_MA06 Y29 GND
W30 D2_MA08 Y30 D2_MECC7
W31 D2_MDIC0 Y31 GND
W32 G2VDD Y32 D2_MECC3
AA1 D1_MDQS8_B AB1 D1_MDM8
AA2 D1_MDQS8 AB2 GND
AA3 D1_MECC6 AB3 D1_MECC2
AA4 D1_MDQ30 AB4 D1_MDQ29
AA5 D1_MDM3 AB5 GND
AA6 D1_MBA2 AB6 D1_MDQ27
AA7 D1_MCKE0 AB7 D1_MDQ26
AA8 D1_MCKE1 AB8 GND
AA9 D1_MA14 AB9 GND
AA10 G1VDD AB10 GND
AA11 GND AB11 VDD
AA12 VDD AB12 GND
AA13 GND AB13 VDD

B4860 QorIQ Qonverge Data Sheet, Rev. 4

56 NXP Semiconductors
 Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

AA14 VDD AB14 GND

AA15 GND AB15 VDD
AA16 VDD AB16 GND
AA17 GND AB17 VDD
AA18 VDD AB18 GND
AA19 GND AB19 VDD
AA20 VDD AB20 GND
AA21 GND AB21 VDD
AA22 VDD AB22 GND
AA23 G2VDD AB23 GND
AA24 D2_MA14 AB24 GND
AA25 D2_MCKE1 AB25 GND
AA26 D2_MCKE0 AB26 D2_MDQ26
AA27 D2_MBA2 AB27 D2_MDQ27
AA28 D2_MDM3 AB28 GND
AA29 D2_MDQ30 AB29 D2_MDQ29
AA30 D2_MECC6 AB30 D2_MECC2
AA31 D2_MDQS8 AB31 GND
AA32 D2_MDQS8_B AB32 D2_MDM8
AC1 D1_MECC5 AD1 D1_MDM2
AC2 D1_MECC4 AD2 D1_MDQ19
AC3 D1_MECC1 AD3 D1_MDQ22
AC4 D1_MDQ31 AD4 GND
AC5 D1_MDQS3_B AD5 D1_MDQ28
AC6 D1_MDQS3 AD6 D1_MDQ24
AC7 GND AD7 D1_MDQ25
AC8 AVDD_DDR1 AD8 GND
AC9 M1VREF AD9 GND
AC10 GND AD10 NC_AD10
AC11 GND AD11 SENSEGND2
AC12 VDD AD12 D1_DDRCLK
AC13 GND AD13 OVDD
AC14 VDD AD14 GND
AC15 GND AD15 OVDD

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 57
Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

AC16 VDD AD16 GND

AC17 GND AD17 OVDD
AC18 VDD AD18 GND
AC19 GND AD19 DVDD
AC20 VDD AD20 GND
AC21 GND AD21 D2_DDRCLK
AC22 VDD AD22 GND
AC23 GND AD23 NC_AD23
AC24 M2VREF AD24 GND
AC25 AVDD_DDR2 AD25 GND
AC26 GND AD26 D2_MDQ25
AC27 D2_MDQS3 AD27 D2_MDQ24
AC28 D2_MDQS3_B AD28 D2_MDQ28
AC29 D2_MDQ31 AD29 GND
AC30 D2_MECC1 AD30 D2_MDQ22
AC31 D2_MECC4 AD31 D2_MDQ19
AC32 D2_MECC5 AD32 D2_MDM2
AE1 D1_MDQ21 AF1 D1_MDQS2_B
AE2 GND AF2 D1_MDQS2
AE3 D1_MDQ23 AF3 D1_MDQ16
AE4 D1_MDQS0_B AF4 D1_MDQ03
AE5 D1_MDQS0 AF5 GND
AE6 D1_MDQ04 AF6 D1_MDQ06
AE7 D1_MDQ01 AF7 D1_MDQ00
AE8 TSEC_1588_CLK_OUT AF8 USB_D0
AE9 TSEC_1588_TRIG_IN1 AF9 TSEC_1588_PULSE_OUT1
AE10 EVT0_B AF10 TSEC_1588_TRIG_IN2
AE11 EVT1_B AF11 CP_SYNC1
AE12 SENSEVDD2 AF12 EVT4_B
AE13 GND AF13 IFC_AD02/CFG_GPINPUT2
AE14 OVDD AF14 IFC_AD08/CFG_RCW_SRC0
AE15 GND AF15 IFC_AD09/CFG_RCW_SRC1
AE16 OVDD AF16 IFC_AD10/CFG_RCW_SRC2
AE17 GND AF17 IFC_AD12/CFG_RCW_SRC4

B4860 QorIQ Qonverge Data Sheet, Rev. 4

58 NXP Semiconductors
 Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

AE18 OVDD AF18 IFC_AD13/CFG_RCW_SRC5

AE19 GND AF19 IFC_AD03/CFG_GPINPUT3
AE20 DVDD AF20 TMP_DETECT_B
AE21 GND AF21 SDHC_DAT3/GPIO2[8]
AE22 GND AF22 IRQ01
AE23 IIC2_SCL AF23 IRQ00
AE24 UART1_CTS_B/GPIO1[21]/UART3_SIN/ AF24 UART1_RTS_B/GPIO1[19]/UART3_SOUT/
CP_LOS7 CP_LOS6
AE25 IIC4_SDA/GPIO3[6]/EVT6_B/ AF25 UART2_SOUT/GPIO1[16]
USB_PWRFAULT
AE26 D2_MDQ01 AF26 D2_MDQ00
AE27 D2_MDQ04 AF27 D2_MDQ06
AE28 D2_MDQS0 AF28 GND
AE29 D2_MDQS0_B AF29 D2_MDQ03
AE30 D2_MDQ23 AF30 D2_MDQ16
AE31 GND AF31 D2_MDQS2
AE32 D2_MDQ21 AF32 D2_MDQS2_B
AG1 D1_MDQ20 AH1 D1_MDM1
AG2 D1_MDQ18 AH2 GND
AG3 D1_MDQ17 AH3 D1_MDQ13
AG4 D1_MDM0 AH4 D1_MDQ08
AG5 D1_MDQ05 AH5 D1_MDQ07
AG6 D1_MDQ02 AH6 USB_STP
AG7 USB_D1 AH7 USB_D2
AG8 GND AH8 TSEC_1588_ALARM_OUT2
AG9 TSEC_1588_ALARM_OUT1 AH9 CP_SYNC7
AG10 CP_SYNC2 AH10 CP_SYNC3
AG11 GND AH11 EVT2_B
AG12 IFC_AD00/CFG_GPINPUT0 AH12 IFC_A24/IFC_WP3_B
AG13 IFC_AD01/CFG_GPINPUT1 AH13 IFC_PAR0/GPIO2[13]
AG14 GND AH14 IFC_A17
AG15 IFC_A16 AH15 IFC_AD04/CFG_GPINPUT4
AG16 IFC_A18 AH16 IFC_AD11/CFG_RCW_SRC3
AG17 GND AH17 IFC_A20
AG18 IFC_AD15/CFG_RCW_SRC7 AH18 IFC_A19

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 59
Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

AG19 IFC_A21/CFG_DRAM_TYPE AH19 IFC_AD14/CFG_RCW_SRC6

AG20 GND AH20 SPI_CS2_B/GPIO2[2]/SDHC_DAT6
AG21 SPI_CLK AH21 SDHC_DAT1/GPIO2[6]
AG22 SDHC_DAT0/GPIO2[5] AH22 IRQ02
AG23 GND AH23 IRQ03/GPIO1[23]
AG24 IIC2_SDA AH24 IRQ04/GPIO1[24]
AG25 UART2_RTS_B/GPIO1[20]/UART4_SOUT AH25 IIC1_SDA
AG26 GND AH26 UART2_SIN/GPIO1[18]
AG27 D2_MDQ02 AH27 IIC1_SCL
AG28 D2_MDQ05 AH28 D2_MDQ07
AG29 D2_MDM0 AH29 D2_MDQ08
AG30 D2_MDQ17 AH30 D2_MDQ13
AG31 D2_MDQ18 AH31 GND
AG32 D2_MDQ20 AH32 D2_MDM1
AJ1 D1_MDQ11 AK1 D1_MDQS1_B
AJ2 D1_MDQ14 AK2 D1_MDQS1
AJ3 D1_MDQ12 AK3 D1_MDQ10
AJ4 D1_MDQ09 AK4 USB_D7
AJ5 GND AK5 USB_D4
AJ6 USB_D3 AK6 USB_D5
AJ7 GND AK7 TSEC_1588_PULSE_OUT2
AJ8 EMI2_MDIO AK8 CP_SYNC5
AJ9 CP_SYNC0 AK9 CP_SYNC6
AJ10 GND AK10 ASLEEP/GPIO1[13]/CFG_XVDD_SEL
AJ11 EVT3_B AK11 CKSTP_OUT_B
AJ12 IFC_PAR1/GPIO2[14] AK12 IFC_WE_B/IFC_WBE0
AJ13 GND AK13 IFC_CS1_B/GPIO2[10]
AJ14 IFC_A25/GPIO2[25]/IFC_RB2_B/ AK14 IFC_CS2_B/GPIO2[11]
IFC_FCTA2
AJ15 IFC_A26/GPIO2[26]/IFC_RB3_B/ AK15 IFC_CS0_B
IFC_FCTA3
AJ16 GND AK16 IFC_OE_B/IFC_RE_B
AJ17 IFC_A27/GPIO2[27] AK17 IFC_A23/IFC_WP2_B
AJ18 IFC_CS3_B/GPIO2[12] AK18 IFC_AD07/CFG_GPINPUT7
AJ19 GND AK19 SPI_CS1_B/GPIO2[1]/SDHC_DAT5

B4860 QorIQ Qonverge Data Sheet, Rev. 4

60 NXP Semiconductors
 Pin assignments

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

AJ20 IFC_A22/IFC_WP1_B AK20 SDHC_CMD/GPIO2[4]

AJ21 SPI_CS0_B/GPIO2[0]/SDHC_DAT4 AK21 IRQ06/GPIO1[26]/TMR0
AJ22 GND AK22 IRQ08/GPIO1[28]/TMR2
AJ23 IRQ_OUT_B/EVT9_B AK23 IRQ05/GPIO1[25]
AJ24 IRQ10/GPIO1[30]/TMR4 AK24 IRQ07/GPIO1[27]/TMR1
AJ25 GND AK25 TRST_B
AJ26 EMI1_MDC AK26 EMI1_MDIO
AJ27 IIC4_SCL/GPIO3[5]/EVT5_B AK27 CP_LOS1
AJ28 GND AK28 UART2_CTS_B/GPIO1[22]/UART4_SIN
AJ29 D2_MDQ09 AK29 IIC3_SDA/GPIO3[4]
AJ30 D2_MDQ12 AK30 D2_MDQ10
AJ31 D2_MDQ14 AK31 D2_MDQS1
AJ32 D2_MDQ11 AK32 D2_MDQS1_B
AL1 GND AM1 —
AL2 D1_MDQ15 AM2 GND
AL3 GND AM3 TSEC_1588_CLK_IN
AL4 USB_CLK AM4 USB_D6
AL5 USB_NXT AM5 USB_DIR
AL6 GND AM6 DMA1_DREQ0_B/GPIO3[0]
AL7 DMA1_DACK0_B/GPIO3[1]/EVT7_B/TMR6 AM7 DMA1_DDONE0_B/GPIO3[2]/EVT8_B/TM
R7
AL8 CP_SYNC4 AM8 EMI2_MDC
AL9 GND AM9 RESET_REQ_B
AL10 CP_RCLK0 AM10 CP_RCLK0_B
AL11 CP_RCLK1 AM11 CP_RCLK1_B
AL12 GND AM12 HRESET_B
AL13 IFC_AD05/CFG_GPINPUT5 AM13 CLK_OUT
AL14 IFC_WP0_B AM14 IFC_CLE/IFC_WBE1/CFG_RCW_SRC8
AL15 GND AM15 IFC_RB0_B/IFC_FCTA0
AL16 IFC_BCTL AM16 IFC_TE/CFG_IFC_TE
AL17 IFC_AD06/CFG_GPINPUT6 AM17 IFC_RB1_B/IFC_FCTA1
AL18 GND AM18 IFC_CLK0
AL19 IFC_AVD/IFC_ALE/CFG_RSP_DIS AM19 IFC_CLK1
AL20 SPI_MISO AM20 SPI_CS3_B/GPIO2[3]/SDHC_DAT7

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 61
Electrical characteristics

Table 2. Pinout by package pin number (continued)

Package pin Package pin

Package pin name Package Pin Name
number number

AL21 GND AM21 SPI_MOSI

AL22 SDHC_DAT2/GPIO2[7] AM22 SDHC_CLK/GPIO2[9]
AL23 IRQ11/GPIO1[31]/TMR5 AM23 RTC/GPIO1[14]
AL24 GND AM24 IRQ09/GPIO1[29]/TMR3
AL25 TDO AM25 TMS
AL26 TCK AM26 TDI
AL27 GND AM27 CP_LOS2
AL28 CP_LOS3 AM28 UART1_SIN/GPIO1[17]/CP_LOS5
AL29 UART1_SOUT/GPIO1[15]/CP_LOS4 AM29 CP_LOS0
AL30 GND AM30 IIC3_SCL/GPIO3[3]
AL31 D2_MDQ15 AM31 GND
AL32 GND AM32 —

2 Electrical characteristics
This section provides the AC and DC electrical specifications for the chip.

2.1 Overall DC electrical characteristics

This section describes the ratings, conditions, and other characteristics.

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62 NXP Semiconductors
 Electrical characteristics

2.1.1 Absolute maximum ratings

This table provides the absolute maximum ratings.
Table 3. Absolute operating conditions1

Parameter Symbol Recommended value Unit Notes

Platform and cores supply voltage VDD –0.3 to 1.1 V —

PLL supply voltage: –0.3 to 1.9 V —
• CGA1 PLL AVDD_CGA1
• CGA2 PLL AVDD_CGA2
• CGB1 PLL AVDD_CGB1
• CGB2 PLL AVDD_CGB2
• Platform PLL AVDD_PLAT
• DDR1 PLL AVDD_DDR1
• DDR2 PLL AVDD_DDR2

PLL supply voltage (SerDes) –0.3 to 1.45/1.6 V —

• SerDes1 PLL1 AVDD_SRDS1_PLL1
• SerDes1 PLL2 AVDD_SRDS1_PLL2
• SerDes2 PLL1 AVDD_SRDS2_PLL1
• SerDes2 PLL2 AVDD_SRDS2_PLL2

Fuse programming override supply POVDD –0.3 to 1.99 V —

Thermal monitor unit supply TH_VDD –0.3 to 1.90 V 5
UART, I2C, CPRI LOS and GPIO I/O voltage DVDD –0.3 to 1.9 V/2.6 V —
IFC, SPI, (e)SDHC, MPIC, Trust, power management, OVDD –0.3 to 1.9 V —
clocking, debug, JTAG, CPRI SYNC/RCLK, 1588,
Ethernet MI, USB ULPI, DMA, GPIO, system control I/O
voltage
SYSCLK, PORESET_B I/O voltage QVDD –0.3 to 1.9 V —
DDR DRAM I/O voltage –0.3 to 1.45/1.6 V 2
• DDR1 G1VDD
• DDR2 G2VDD

Core power supply for SerDes receivers SVDD –0.3 to 1.1 V —

Pad power supply for SerDes transmitters XVDD –0.3 to 1.45/1.6 V —

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 63
Electrical characteristics

Table 3. Absolute operating conditions1 (continued)

Parameter Symbol Recommended value Unit Notes

Input voltage DDR DRAM signals MVIN –0.3 to (GnVDD + 0.3) V 2

DDR DRAM reference MnVREF –0.3 to (GnVDD/2 + 0.3) V —
UART, I2C, Ethernet MI1, CPRI LOS and QVIN –0.3 to (DVDD + 0.3) V 3
GPIO signals
SYSCLK and PORESET_B signals QVIN –0.3 to (QVDD + 0.3) V 4
IFC, SPI, (e)SDHC, MPIC, Trust, power OVIN –0.3 to (OVDD + 0.3) V 3
management, clocking, debug, JTAG,
CPRI SYNC/RCLK, 1588, USB ULPI,
DMA, GPIO, system signals
Ethernet Management Interface (EMI2) — –0.3 to 1.98 V 6
SerDes signals SVIN –0.4 to (SVDD + 0.3) V —
Storage junction temperature range Tstg –55 to 150 °C —
Note:
1. Functional operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only; functional operation
at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage
to the device.
2. Caution: MVIN must not exceed GnVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: QVIN must not exceed QVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. The Thermal Monitoring Unit (TMU) supply is defeatured on this device. TH_VDD should be connected to an OVDD supply.
6. Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels.
OVDD must be powered to use this interface..

2.1.2 Recommended operating conditions

This table provides the recommended operating conditions for this chip.

NOTE
The values shown are the recommended operating conditions. Proper device operation
outside these conditions is not guaranteed.
Table 4. Recommended operating conditions

Recommended
Characteristic Symbol Unit Notes
Value

Core and platform supply voltage At initial start-up VDD 1.05 V ± 30 mV V 4, 5, 6

During normal operation VID ± 30 mV V 1, 4, 5
PLL supply voltage (core, platform, DDR) AVDD_CGAn 1.8 V ± 90 mV V —
AVDD_CGBn
AVDD_PLAT
AVDD_DDRn

B4860 QorIQ Qonverge Data Sheet, Rev. 4

64 NXP Semiconductors
 Electrical characteristics

Table 4. Recommended operating conditions (continued)

PLL supply voltage (SerDes, filtered from XnVDD) AVDD_SDRSn_PLLn 1.5 V ± 75 mV V —
1.35 V ± 67 mV
Fuse programming override supply POVDD 1.8 V ± 90 mV V 2
IFC, eSPI, eSHDC, MPIC, trust (TMP_DETECT_B), system OVDD 1.8 V ± 90 mV V —
control (HRESET_B), power management (ASLEEP), DDRCLK,
RTC, debug (EVT*, CKSTP_OUT_B, CLK_OUT), JTAG, CPRI
SYNC/RCLK, 1588, US ULPI, DMA
UART, I2C, Ethernet MI1, CPRI LOS, and GPIO I/O voltage DVDD 2.5 V ± 125 mV V —
1.8 V ± 90 mV
SYSCLK and PORESET I/O voltage QVDD 1.8 V ± 90mV V 7
DDR DRAM I/O voltage DDR3 GnVDD 1.5 V ± 75 mV V —
DDR3L 1.35 V ± 67 mV —
Main power supply for internal circuitry of SerDes and pad power SVDD 1.0 V +50mV/-30mV V —
supply for SerDes receivers
Pad power supply for SerDes transmitters XVDD 1.5 V ± 75 mV V —
1.35 V ± 67 mV
Ethernet management interface 2 (EMI2) I/O voltage — 1.2 V ± 60 mV V 8
Input voltage DDR3 and DDR3L DRAM MVIN GND to GnVDD V —
signals
DDR3 and DDR3L DRAM Dn_MVREF GnVDD/2 ± 1% V —
reference
UART, I2C, Ethernet MI1, CPRI DVIN GND to DVDD V —
LOS and GPIO signals
eSHDC, eSPI, DMA, MPIC, OVIN GND to OVDD V —
GPIO, system control and
power management, clocking,
debug, IFC, Dn_DDRCLK
supply, and JTAG signals
SYSCLK, PORESET signals QVIN GND to QVDD V —
SerDes signals SVIN GND to SVDD V —

Ethernet management — GND to 1.2 V V 3

interface 2 (EMI2) signals

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 65
Electrical characteristics

Table 4. Recommended operating conditions (continued)

Operating temperature range Normal operation TA, TA = 0 (min) to °C —
TJ TJ = 105 (max)
Extended Temperature TA, TA = -40 (min) to °C —
TJ TJ = 105 (max)
Secure boot fuse programming TA, TA = 0 (min) to °C 2
TJ TJ = 70 (max)
Note:
1. The Voltage ID (VID) operating range is between 0.95 V and 1.05 V. Regulator selection should be based on a Vout range of at
least 0.9 V to 1.1 V, with resolution of 12.5 mV or better. See Section 3.2.1, “Voltage ID (VID) controllable supply” for more
details.
2. POVDD must be supplied 1.8 V and the chip must operate in the specified fuse programming temperature range only –0 –70°C
during secure boot fuse programming. For all other operating conditions, POVDD must be tied to GND, subject to the power
sequencing constraints shown in Section 2.2, “Power sequencing.”
3. Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels.
4. See Section 3.2.2, “Core supply voltage filtering,” for additional information.
5. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
6. Operation at 1.05 V is allowable for up to 1 second at initial power on.
7. Add a bypass cap of 0.1uF on this power ball pin.

8. These pins should be pulled up to 1.2 V through a 180 Ω (1% accuracy) resistor for EMI2_MDC and 330 Ω (1% accuracy)
resistor for EMI2_MDIO. When Ethernet Management Interface 2 unused, EMI2_MDIO’s external pull-up resistor can be tied
to OVDD

B4860 QorIQ Qonverge Data Sheet, Rev. 4

66 NXP Semiconductors
 Electrical characteristics

This figure shows the undershoot and overshoot voltages at the interfaces of the chip.

[Nominal]D/Q/O/GnVDD + 20%
D/Q/O/GnVDD + 5%
VIH D/Q/O/GnVDD

GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to exceed 10%
of tCLOCK
Note:
tCLOCK refers to the clock period associated with the respective interface:
For I2C and JTAG, tCLOCK refers to SYSCLK.
For DDR GnVDD, tCLOCK refers to Dn_DDRCLK.
For SPI OVDD, tCLOCK refers to SPI_CLK.
For SerDes XVDD, tCLOCK refers to SD_REF_CLK.
Figure 7. Overshoot/Undershoot voltage for DVDD/QVDD/OVDD/GnVDD

See Table 4 for actual recommended core voltage. Voltage to the processor interface I/Os are provided through separate sets of
supply pins and must be provided at the voltages shown in Table 4. The input voltage threshold scales with respect to the
associated I/O supply voltage. DVDD, QVDD, and OVDD-based receivers are simple CMOS I/O circuits and satisfy
appropriate LVCMOS type specifications. The DDR SDRAM interface uses differential receivers referenced by the externally
supplied MnVREF signal (nominally set to GnVDD/2) as is appropriate for the SSTL_1.35/SSTL_1.5 electrical signaling
standard. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven
and cannot be grounded.

2.1.3 Output driver characteristics

This chip provides information on the characteristics of the output driver strengths. These values are preliminary estimates.
Table 5. Output drive capability

Driver type Output impedance (Ω) Supply voltage Notes

DDR3 signal 18 (full-strength mode) GnVDD= 1.5 V 1

27 (half-strength mode)

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NXP Semiconductors 67
Electrical characteristics

Table 5. Output drive capability (continued)

Driver type Output impedance (Ω) Supply voltage Notes

DDR3L signal 18 (full-strength mode) GnVDD = 1.35 V 1

27 (half-strength mode)
IFC, eSPI, eSDHC, MPIC, Trust, power management, clocking, OVDD = 1.8 V —
debug, JTAG, CPRI SYNC/RCLK, 1588, USB ULPI, DMA, GPIO, 45
system control, Reset
DUART, I2C, Ethernet MI, CPRI-LOS, GPIO 45 DVDD = 2.5 V —
DVDD = 1.8 V
Note:
1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 °C and at GnVDD (min).

2.2 Power sequencing

The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. For power
up, these requirements are as follows:
1. There are no restrictions on the order of Power supplies bringing up. During power up, drive POVDD = GND.
— PORESET_B input must be driven asserted and held during this step.
2. Negate PORESET_B input as long as the required assertion/hold time has been met per Table 13.
3. For secure boot fuse programming, use the following steps:
a) After negation of PORESET_B, drive POVDD = 1.8 V after a required minimum delay per Table 6.
b) After fuse programming is completed, it is required to return POVDD = GND before the system is power cycled
(PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Table 6. See
Section 5, “Security fuse processor,” for additional details.

WARNING
No activity other than that required for secure boot fuse programming is permitted while
POVDD is driven to any voltage above GND, including the reading of the fuse block. The
reading of the fuse block may only occur while POVDD = GND.
From a system standpoint, if any of the I/O power supplies ramp prior to the VDD supply,
the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and
extra current may be drawn by the device.
WARNING
Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is
based on design estimates and is preliminary.
All supplies must be at their stable values within 75 ms.

B4860 QorIQ Qonverge Data Sheet, Rev. 4

68 NXP Semiconductors
 Electrical characteristics

This figure provides the POVDD timing diagram.

Fuse programming

10% POVDD
POVDD 10% POVDD

90% VDD
VDD tPOVDD_VDD

90% OVDD tPOVDD_PROG 90% OVDD

PORESET_B
tPOVDD_DELAY tPOVDD_RST

NOTE: POVDD must be stable at 1.8 V prior to initiating fuse programming.

Figure 8. POVDD timing diagram

This table provides information on the power-down and power-up sequence parameters for POVDD.
Table 6. POVDD timing5

Driver type Min Max Unit Notes

tPOVDD_DELAY 100 — SYSCLKs 1

tPOVDD_PROG 0 — μs 2
tPOVDD_VDD 0 — μs 3
tPOVDD_RST 0 — μs 4
Note:
1. Delay required from the deassertion of PORESET_B to driving POVDD ramp up. Delay measured from PORESET_B
deassertion at 90% OVDD to 10% POVDD ramp up.
2. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD
is stable at 1.8 V. No activity other than that required for secure boot fuse programming is permitted while POVDD is driven
to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD
= GND. After fuse programming is completed, it is required to return POVDD = GND.
3. Delay required from POVDD ramp down complete to VDD ramp down start. POVDD must be grounded to minimum 10%
POVDD before VDD is at 90% VDD.
4. Delay required from POVDD ramp down complete to PORESET_B assertion. POVDD must be grounded to minimum 10%
POVDD before PORESET_B assertion reaches 90% OVDD.
5. Only two secure boot fuse programming events are permitted per lifetime of a device.

NOTE
While VDD is ramping, current may be supplied from VDD through the chip to GnVDD.
Nevertheless, GnVDD from an external supply should follow the sequencing described
above.

2.3 Power-down requirements

The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be
started.
If performing secure boot fuse programming per Section 2.2, “Power sequencing,” it is required that POVDD = GND before the
system is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in
Table 6.

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 69
Electrical characteristics

2.4 Power characteristics

Because it depends strongly on application type, the power characteristics for the average power and instantaneous peak current
numbers are supplied by the device’s detailed power calculator.

2.5 Power-on ramp rate

This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum
power-on ramp rate is required to avoid excess in-rush current.
This table provides the power supply ramp rate specifications.
Table 7. Power supply ramp rate

Parameter Min Max Unit Notes

Required ramp rate for all voltage supplies (including OVDD/DVDD/ — 25 V/ms 1, 2
GnVDD/QVDD/SVDD/XVDD, core VDD supply, MnVREF and all AVDD supplies.)
Required ramp rate for POVDD — 25 V/ms 1, 2

Notes:
1. Ramp rate is specified as a linear ramp from 10 to 90%. If nonlinear (for example, exponential), the maximum rate of change
from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry. If needed to slow down the rate,
usage of larger capacitors is recommended.
2. Over full recommended operating temperature range (see Table 4)

2.6 Input clocks

2.6.1 System clock (SYSCLK) timing specifications

This section provides the system clock DC and AC timing specifications.

2.6.1.1 System clock DC timing specifications

This table provides the system clock (SYSCLK) DC specifications.
Table 8. SYSCLK DC electrical characteristics
At recommended operating conditions with QVDD = 1.8 V, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Input high voltage VIH 1.25 — — V 1

Input low voltage VIL — — 0.6 V 1
Input capacitance CIN — 7 12 pF —
Input current IIN — — ± 50 μA 2
(OVIN= 0 V or OVIN = QVDD)
Notes:
1. The min VILand max VIH values are based on the respective min and max QVIN values found in Table 4.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

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70 NXP Semiconductors
 Electrical characteristics

2.6.1.2 System clock AC timing specifications

This table provides the system clock (SYSCLK) AC timing specifications.
Table 9. SYSCLK AC timing specifications
At recommended operating conditions with OVDD = 1.8 V, see Table 4.

Parameter/Condition Symbol Min Typ Max Unit Notes

SYSCLK frequency fSYSCLK 66.667 — 133.333 MHz 1, 2

SYSCLK cycle time tSYSCLK 7.5 — 15 ns 1, 2
SYSCLK duty cycle tKHK / tSYSCLK 40 50 60 % 2
SYSCLK slew rate — 1 — 4 V/ns 3
SYSCLK peak period jitter — — — ±150 ps —
SYSCLK jitter phase noise at –56 dBc — — — 500 KHz 4
AC Input Swing Limits at 1.8 V QVDD ΔVAC 0.35 x QVDD — 0.65 x QVDD V —
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at QVDD/2.
3. Slew rate is measured from 10% ~ 90% of VIL to VIH.
4. Phase noise is calculated as FFT of TIE jitter.

2.6.2 Spread-spectrum sources

Spread-spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by
spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter
specification given in this table considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output
jitter should meet the chip’s input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns;
the chip is compatible with spread spectrum sources if the recommendations listed in this table are observed.
Table 10. Spread-spectrum clock source recommendations
At recommended operating conditions with OVDD = 1.8 V, see Table 4.

Parameter Min Max Unit Notes

Frequency modulation — 60 kHz —

Frequency spread — 1.0 % 1, 2
Notes:
1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
maximum specifications given in Table 9.
2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device.

CAUTION
The processor’s minimum and maximum SYSCLK and core/platform/DDR frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which
the processor is operated at its maximum rated core/platform/DDR frequency should avoid
violating the stated limits by using down-spreading only.

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Electrical characteristics

2.6.3 Real-time clock timing

The real-time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an
input to the counters of the MPIC and the time base unit of the core; there is no need for jitter specification. The minimum period
of the RTC signal should be greater than or equal to 16× the period of the platform clock with a 50% duty cycle. There is no
minimum RTC frequency; RTC may be grounded if not needed.

2.6.4 DDR clock timing

2.6.4.1 DDR D1_DDRCLK/D2_DDRCLK clocks DC timing specifications

This table provides the system clock (MCLK) DC specifications.
Table 11. D1_DDRCLK3/D2_DDRCLK DC electrical characteristics
At recommended operating conditions with OVDD = 1.8v, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Input high voltage VIH 1.25 — — V 1

Input low voltage VIL — — 0.6 V 1
Input capacitance CIN — 7 12 pF —
Input current IIN — — ± 50 μA 2
(OVIN= 0 V or OVIN = OVDD)
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 4.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
3. D1_DDRCLK must toggle in order to get out of PORESET, even if the DDR1 interface is not required. AVDD_DDR1 voltage
must be supplied.

2.6.4.2 DDR D1_DDRCLK/D2_DDRCLK clocks AC timing specifications

This table provides the system clock (D1_DDRCLK/D2_DDRCLK) AC timing specifications.
Table 12. Dn_DDRCLK AC timing specifications
At recommended operating conditions with OVDD = 1.8V, see Table 4.

Parameter/Condition Symbol Min Typ Max Unit Notes

Dn_DDRCLK frequency fMCLK 66.667 — 133.333 MHz 1, 2

Dn_DDRCLK cycle time tMCLK 7.5 — 15 ns 1, 2
Dn_DDRCLK duty cycle tKHK / tMCLK 40 50 60 % 2
Dn_DDRCLK slew rate — 1 — 4 V/ns 3

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Table 12. Dn_DDRCLK AC timing specifications (continued)

At recommended operating conditions with OVDD = 1.8V, see Table 4.

Parameter/Condition Symbol Min Typ Max Unit Notes

Dn_DDRCLK peak period jitter — — — ± 150 ps —

Dn_DDRCLK jitter phase noise at — — — 500 KHz 4
–56 dBc
AC Input Swing Limits at 1.8 V OVDD ΔVAC 0.35 x OVDD — 0.65 x OVDD V —
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting D1_DDRCLK/D2_DDRCLK frequency do
not exceed their respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate is measured from 10% ~ 90% of VIL to VIH.
4. Phase noise is calculated as FFT of TIE jitter.

2.6.5 Other input clocks

A description of the overall clocking of this device is available in the chip reference manual in the form of a clock subsystem
block diagram. For information about the input clock requirements of functional modules sourced external of the chip, such as
SerDes, I2C, eSDHC, IFC, USB, and 1588, see the specific interface section.

2.7 RESET initialization

This table describes the AC electrical specifications for the RESET initialization timing.
Table 13. RESET Initialization timing specifications

Parameter/Condition Min Max Unit Notes

Required assertion time of PORESET_B 1 — ms 3

Required input assertion time of HRESET_B 32 — SYSCLKs 1, 2
Maximum rise/fall time of HRESET_B — 1 SYSCLK 4
PLL input setup time with stable SYSCLK before HRESET_B negation 100 — μs —
Input setup time for POR configs with respect to negation of 4 — SYSCLKs 1
PORESET_B
Input hold time for all POR configs with respect to negation of 2 — SYSCLKs 1
PORESET_B
Maximum valid-to-high impedance time for actively driven POR configs — 5 SYSCLKs 1
with respect to negation of PORESET_B
Notes:
1. SYSCLK is the primary clock input for the chip.
2. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The device
releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is
documented in the “Power-On Reset Sequence” section of the chip reference manual.
3. PORESET_B must be driven asserted before the core and platform power supplies are powered up.
4. The system/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

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NXP Semiconductors 73
Electrical characteristics

This table provides the PLL lock times.

Table 14. PLL lock times

Parameter/Condition Min Max Unit Notes

PLL lock times — 100 μs —

2.8 DDR3 and DDR3L SDRAM controller

This section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note
that the required GnVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the GnVDD(typ) voltage is 1.35 V when
interfacing to DDR3L SDRAM.

NOTE
When operating at DDR data rates of 1866 MT/s, only one dual-ranked module per
memory controller is supported.

2.8.1 DDR3 and DDR3L SDRAM interface DC electrical characteristics

This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3
SDRAM.
Table 15. DDR3 SDRAM interface DC electrical characteristics (GnVDD = 1.5 V)1
For recommended operating conditions, see Table 4.

Parameter Symbol Min Max Unit Notes

I/O reference voltage MnVREF 0.49 × GnVDD 0.51 × GnVDD V 2, 3, 4

Input high voltage VIH MnVREF + 0.100 GnVDD V 5
Input low voltage VIL GND MnVREF – 0.100 V 5
I/O leakage current IOZ –50 50 μA 6
Notes:
1. GnVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s
voltage supply may or may not be from the same source.
2. MnVREFis expected to be equal to 0.5 × GnVDD and to track GnVDD DC variations as measured at the receiver.
Peak-to-peak noise on MnVREFmay not exceed the MnVREFDC level by more than ±1% of the DC value (that is, ±15 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to
be equal to MnVREFwith a min value of MnVREF – 0.04 and a max value of MnVREF + 0.04. VTT should track variations
in the DC level of MnVREF.
4. The voltage regulator for MnVREFmust meet the specifications stated in Table 18.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GnVDD.

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 Electrical characteristics

This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L
SDRAM.
Table 16. DDR3L SDRAM interface DC electrical characteristics (GnVDD = 1.35 V)1
For recommended operating conditions, see Table 4.

Parameter Symbol Min Max Unit Notes

I/O reference voltage MnVREF 0.49 × GnVDD 0.51 × GnVDD V 2, 3, 4

Input high voltage VIH MnVREF + 0.090 GnVDD V 5
Input low voltage VIL GND MnVREF – 0.090 V 5
I/O leakage current IOZ –100 100 μA 6
Notes:
1. GnVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage
supply may or may not be from the same source.
2. MnVREF is expected to be equal to 0.5 × GnVDD and to track GnVDD DC variations as measured at the receiver. Peak-to-peak
noise on MnVREF may not exceed the MnVREF DC level by more than ±1% of the DC value (that is, ±13.5mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MnVREF with a min value of MnVREF – 0.04 and a max value of MnVREF + 0.04. VTT should track variations in the
DC level of MnVREF.
4. The voltage regulator for MnVREF must meet the specifications stated in Table 18.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GnVDD.
7. See the IBIS model for the complete output IV curve characteristics.

This table provides the DDR controller interface capacitance for DDR3 and DDR3L.
Table 17. DDR3 and DDR3L SDRAM capacitance
For recommended operating conditions, see Table 4.

Parameter Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS, DQS_B CIO 6 8 pF —

Delta input/output capacitance: DQ, DQS, DQS_B CDIO — 0.5 pF —

This table provides the current draw characteristics for MnVREF.

Table 18. Current draw characteristics for MnVREF
For recommended operating conditions, see Table 4.

Parameter Symbol Min Max Unit Notes

Current draw for DDR3 SDRAM for MnVREF IMnVREF — 500 μA —

Current draw for DDR3L SDRAM for MnVREF IMnVREF — 500 μA —

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NXP Semiconductors 75
Electrical characteristics

2.8.2 DDR3 and DDR3L SDRAM interface AC timing specifications

This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports
DDR3 and DDR3L memories. Note that the required GnVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the
required GnVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.

2.8.2.1 DDR3 and DDR3L SDRAM interface input AC timing specifications

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.
Table 19. DDR3 and DDR3L SDRAM interface input AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Max Unit Notes

Controller Skew for MDQS—MDQ/MECC tCISKEW ps 1

1866 MT/s data rate –93 93
1600 MT/s data rate –112 112
1333 MT/s data rate –125 125
1200 MT/s data rate –142 142
1066 MT/s data rate –170 170
Tolerated Skew for MDQS—MDQ/MECC tDISKEW ps 2
1866 MT/s data rate –175 175
1600 MT/s data rate –200 200
1333 MT/s data rate –250 250
1200 MT/s data rate –275 275
1066 MT/s data rate –300 300
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. This must be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW = ±(T ÷ 4 – abs(tCISKEW)), where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.

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76 NXP Semiconductors
 Electrical characteristics

This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.

MCK_B[n]

MCK[n]
tMCK

MDQS[n]

tDISKEW

MDQ[x] D0 D1
tDISKEW
tDISKEW

Figure 9. DDR3 and DDR3L SDRAM interface input timing diagram

2.8.2.2 DDR3 and DDR3L SDRAM interface output AC timing specifications

This table contains the output AC timing targets for the DDR3 SDRAM interface.
Table 20. DDR3 and DDR3L SDRAM interface output AC timing specifications
For recommended operating conditions, see Table 4

Parameter Symbol1 Min Max Unit Notes

MCK[n] cycle time tMCK 1.072 1.876 ns 2

ADDR/CMD output setup with respect to MCK tDDKHAS ns 3
1866 MT/s data rate 0.410 —
1600 MT/s data rate 0.495 —
1333 MT/s data rate 0.606 —
1200 MT/s data rate 0.675 —
1066 MT/s data rate 0.744 —
ADDR/CMD output hold with respect to MCK tDDKHAX ns 3
1866 MT/s data rate 0.390 —
1600 MT/s data rate 0.495 —
1333 MT/s data rate 0.606 —
1200 MT/s data rate 0.675 —
1066 MT/s data rate 0.744 —
MCK to MDQS skew tDDKHMH ns 4
> 1600 MT/s data rate -0.150 -0.150 4,6
data rate > 1066MT/s & =< 1600 MT/s -0.245 0.245 4,6

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NXP Semiconductors 77
Electrical characteristics

Table 20. DDR3 and DDR3L SDRAM interface output AC timing specifications (continued)
For recommended operating conditions, see Table 4

Parameter Symbol1 Min Max Unit Notes

MDQ/MECC/MDM output Data eye tDDKXDEYE ns 5

1866 MT/s data rate 0.350 —
1600 MT/s data rate 0.400 —
1333 MT/s data rate 0.500 —
1200 MT/s data rate 0.550 —
1066 MT/s data rate 0.600 —
MDQS preamble tDDKHMP 0.9 x tMCK — ns —
MDQS postamble tDDKHME 0.4 x tMCK 0.6 x tMCK ns —
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time.
2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay
as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters
have been set to the same adjustment value. See the chip reference manual for a description and explanation of the timing
modifications enabled by use of these bits.
5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller
will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.
6. For data rates of 1200 MT/s and higher, it is required to program the start value of the DQS adjust for write leveling.

NOTE
For the ADDR/CMD setup and hold specifications in Table 20, it is assumed that the clock
control register is set to adjust the memory clocks by ½ applied cycle.

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78 NXP Semiconductors
 Electrical characteristics

This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK to MDQS skew measurement
(tDDKHMH).

MCK[n]

MCK[n]
tMCK

tDDKHMH(max)

MDQS

tDDKHMH(min)

MDQS

Figure 10. tDDKHMH timing diagram

This figure shows the DDR3 and DDR3L SDRAM output timing diagram.

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Figure 11. DDR3 and DDR3L output timing diagram

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NXP Semiconductors 79
 Electrical characteristics

2.9 DC electrical characteristics

2.9.1 DC characteristics for 1.8 V IO cells

This table provides the DC electrical characteristics for the IFC, SPI, MPIC, Trust, power management, clocking, debug, JTAG,
CPRI SYNC/RCLK, 1588, eSDHC, USB ULPI, DMA, Timers, UART and GPIO interface operating at VDDIO =
OVDD/QVDD/DVDD= 1.8 V.
Table 21. DC electrical characteristics (1.8 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

High-level output voltage VOH — — V —

IOH = 1 mA VDDIOMIN – 0.15
IOH = 2 mA VDDIOMIN x 0.8
IOH = -100uA VDDIOMIN – 0.2 3
Low-level output voltage VOL — — V —
IOL = 1 mA 0.15
IOL = 2 mA 0.2 x VDDIOMAX
IOL = 2 mA 0.3 3
Input current (VIN = 0 V or VIN = OVDD/QVDD/DVDD) IIN — — ±50 μA 2
High-level DC input voltage VIH 0.7 x VDDIOMAX — — V 1
Low-level DC input voltage VIL — — 0.3 x VDDIOMIN V 1
Note:
1. The min VILand max VIH values are based on the respective min and max OVIN/QVIN values found in Table 4.
2. The symbol VIN, in this case, represents the OVIN/QVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
3. eSDHC protocol open-drain mode for MMC cards only.

2.9.2 DC characteristics for 2.5 V IO cells

This table provides the DC electrical characteristics for the UART, Ethernet MI1, and GPIO interface operating at
DVDD = 2.5 V.
Table 22. DC electrical characteristics (2.5 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

High-level output voltage VOH — — V —

IOH = 1 mA VDDIOMIN – 0.15
IOH = 2 mA VDDIOMIN x 0.8
Low-level output voltage VOL — — V —
IOL = 1 mA 0.15
IOL = 2 mA 0.2 x VDDIOMAX

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80 NXP Semiconductors
 Electrical characteristics

Table 22. DC electrical characteristics (2.5 V) (continued)

For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

Input current (VIN = 0 V or VIN = OVDD/QVDD/DVDD) IIN — — ±50 μA 2

High-level DC input voltage VIH 0.7 x VDDIOMAX — — V 1
Low-level DC input voltage VIL — — 0.3 x VDDIOMIN V 1
Note:
1. The min VILand max VIH values are based on the respective min and max QVIN values found in Table 4.
2. The symbol VIN, in this case, represents the QVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

2.10 eSPI interface

This section describes the AC electrical specifications for the eSPI interface.

2.10.1 eSPI AC timing specifications

This table provides the eSPI input and output AC timing specifications.
Table 23. eSPI AC timing specifications1

Characteristic Symbol 2 Min Max Unit Note

SPI_MOSI output—Master data (internal tNIKHOX n1 + (tPLATFORM_CLK/2 — ns 2, 3, 4

clock) hold time * SPMODE[HO_ADJ])

SPI_MOSI output—Master data (internal tNIKHOV — n2 + (tPLATFORM_CLK/2 ns 2, 3, 4

clock) delay * SPMODE[HO_ADJ])

SPI_CS outputs—Master data (internal clock) tNIKHOX2 0 — ns 2

hold time

SPI_CS outputs—Master data (internal clock) tNIKHOV2 — 6.0 ns 2

delay
SPI inputs—Master data (internal clock) input tNIIVKH 5 — ns —
setup time

SPI inputs—Master data (internal clock) input tNIIXKH 0 — ns —

hold time

Clock-high/low time tNIKCKH/ 4 — ns —

tNIKCKL

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Electrical characteristics

Table 23. eSPI AC timing specifications1 (continued)

Characteristic Symbol 2 Min Max Unit Note

CLKOUT period SPI_CLK 12 — ns —

Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI
outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid
(V).
2. Output specifications are measured from the 50% level of the rising edge of SPI_CLK to the 50% level of the signal. Timings
are measured at the pin.
3. See the chip reference manual for details about the SPMODE register.
4. The optimal n1 and n2 values are –1.0 and 1.0, respectively, based on the AC timing specifications for the majority of the SPI
flash devices on the market.

This figure provides the AC test load for the eSPI.

Output Z0 = 50 Ω OVDD/2
RL = 50 Ω

Figure 12. eSPI AC test load

This figure provides the eSPI clock output timing diagram.

Figure 13. eSPI clock output timing diagram

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 Electrical characteristics

This figure represents the AC timing from Table 23 in master mode (internal clock). Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Also, note that the clock edge is selectable on eSPI.

SPI_CLK (output)
tNIIXKH
tNIIVKH
Input signals:
SPI_MISO
tNIKHOX
tNIKHOV
Output signals:
SPI_MOSI

tNIKHOV2 tNIKHOX2
Output signals:
SPI_CS[0:3]

Figure 14. eSPI AC timing in master mode (internal clock) diagram

2.11 DUART interface

This section describes the AC electrical specifications for the DUART interface.

2.11.1 UART AC electrical specifications

This table provides the AC timing parameters for the UART interface.
Table 24. UART AC timing specifications

Parameter Value Unit Notes

Minimum baud rate fPLAT/(2 × 1,048,576) baud 1, 3

Maximum baud rate fPLAT/(2 × 16) baud 1, 2

Notes:
1. fPLAT refers to the internal platform clock.
2. The actual attainable baud rate is limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each 16th sample.

2.12 Ethernet interface, Ethernet management interface

1 and 2, IEEE Std 1588™
This section provides the AC and DC electrical characteristics for the Ethernet controller and the Ethernet management
interfaces.

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Electrical characteristics

2.12.1 SGMII electrical specifications

See Section 2.23.8, “SGMII interface.”

2.12.2 Ethernet management interface (EMI)

This section discusses the electrical characteristics for the EMI1 and EMI2 interfaces.
EMI1 is the PHY management interface controlled by the MDIO controller associated with Frame Manager GMAC1-6.
EMI2 is the XAUI, and XFI PHY management interface controlled by the MDIO controller associated with Frame Manager
10GMAC9-10.
Table 22, “DC electrical characteristics (2.5 V),” provides the Ethernet Management interface EMI1 DC electrical
characteristics.

2.12.2.1 Ethernet management interface 1 AC electrical specifications

This table provides the Ethernet management interface 1 AC electrical characteristics.
Table 25. Ethernet management interface 1 AC timing specifications 6

Parameter/Condition Symbol1 Min Typ Max Unit Notes

MDC frequency fMDC — — 2.5 MHz 2

MDC clock pulse width high tMDCH 160 — — ns —

MDC to MDIO delay tMDKHDX (Y× tenet_clk) – 4 — (Y× tenet_clk) + 4 ns 3,4,5

MDIO to MDC setup time tMDDVKH 12.5 — — ns —

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 Electrical characteristics

Table 25. Ethernet management interface 1 AC timing specifications (continued)6

Parameter/Condition Symbol1 Min Typ Max Unit Notes

MDIO to MDC hold time tMDDXKH 0 — — ns —

Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first
two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the
time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.Also, tMDDVKH symbolizes
management data timing (MD) with respect to the time data input signals (D) reach the valid state(V) relative to the tMDC
clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the Ethernet clock frequency. MDIO_CFG [MDIO_CLK_DIV] field determines the clock
frequency of the MgmtClk Clock MDIO_MDC.In Rev2 the default value of MDIO_CFG [MDIO_CLK_DIV] is 0 means no
clock is available. Recommended to configure this field in PBL.
3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to Y x Ethernet clock periods ±4 ns.
For example, with an Ethernet clock of 333 MHz, the min/max delay is (5 x 1/333M) = 15 ns ± 4 ns.
Default values for Rev 1: silicon:
MDIO_CFG[MDIO_HOLD] = 3’b010 which selects 5 tenet_clk cycles
Default values for Rev 2 silicon:
MDIO_CFG[MDIO_HOLD] = 3’b010 which selects 5 tenet_clk cycles
MDIO_CFG[NEG] = 1
MDIO_CFG[EHOLD] = 0
For Rev 1 silicon: Y = MDIO_CFG[MDIO_HOLD]
For Rev 2 silicon:
If MDIO_CFG[EHOLD] = 0 then Y = MDIO_CFG[MDIO_HOLD]
If MDIO_CFG[EHOLD] = 1 then Y = 8 x MDIO_CFG[MDIO_HOLD] +1
4. tMDKHDX transition:
For Rev 1 silicon: tMDKHDX is MDC positive edge to MDIO transition
For Rev 2 silicon:
If MDIO_CFG[NEG] = 0 then tMDKHDX is MDC positive edge to MDIO transition
If MDIO_CFG[NEG] = 1 then tMDKHDX is MDC negative edge to MDIO transition
5. tenet_clk is the Ethernet clock period derived from Frame Manger clock, FM clock. tenet_clk=1/2 × FM_clock.
6. For recommended operating conditions, see Table 4.

2.12.2.2 Ethernet management interface 2 DC electrical characteristics

Ethernet management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels.
OVDD must be powered to use this interface. The DC electrical characteristics for EMI2_MDIO and EMI2_MDC are provided
in this section.
Table 26. Ethernet management interface 2 DC electrical characteristics (1.2 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.84 — V —

Input low voltage VIL — 0.36 V —

Output low voltage (IOL = 5.5 mA) VOL — 0.2 V —

Input capacitance CIN — 10 pF —

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Electrical characteristics

2.12.2.3 Ethernet management interface 2 AC electrical specifications

This table provides the Ethernet management interface 2 AC electrical characteristics.

Table 27. Ethernet management interface 2 AC timing specifications6

Parameter/Condition Symbol1 Min Typ Max Unit Notes

MDC frequency fMDC — — 2.5 MHz 2

MDC clock pulse width high tMDCH 160 — — ns —

MDC to MDIO delay tMDKHDX (Y× tenet_clk) – 4 — (Y× tenet_clk) + 4 ns 3, 4

MDIO to MDC setup time tMDDVKH 12.5 — — ns 6

MDIO to MDC hold time tMDDXKH 0 — — ns —

Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first
two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the
time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.Also, tMDDVKH symbolizes
management data timing (MD) with respect to the time data input signals (D) reach the valid state(V) relative to the tMDC
clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the Ethernet clock frequency. (MDIO_CFG [MDIO_CLK_DIV] field determines the clock
frequency of the MgmtClk Clock MDIO_MDC).
3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to Y x Ethernet clock periods ±4 ns.
For example, in default rev1 silicon, with an Ethernet clock of 333 MHz, the min/max delay is (5 x 1/333M) = 15 ns ± 4 ns.
Default values for Rev 1: silicon:
MDIO_CFG[MDIO_HOLD] = 3’b010 which selects 5 tenet_clk cycles
Default values for Rev 2 silicon:
MDIO_CFG[MDIO_HOLD] = 3’b010 which selects 5 tenet_clk cycles
MDIO_CFG[NEG] = 1
MDIO_CFG[EHOLD] = 0
For Rev 1 silicon: Y = MDIO_CFG[MDIO_HOLD]
For Rev 2 silicon:
If MDIO_CFG[EHOLD] = 0 then Y = MDIO_CFG[MDIO_HOLD]
If MDIO_CFG[EHOLD] = 1 then Y = 8 x MDIO_CFG[MDIO_HOLD] +1
4. tMDKHDX transition:
For Rev 1 silicon: tMDKHDX is MDC positive edge to MDIO transition.
For Rev 2 silicon:
If MDIO_CFG[NEG] = 0 then tMDKHDX is MDC positive edge to MDIO transition
If MDIO_CFG[NEG] = 1 then tMDKHDX is MDC negative edge to MDIO transition
5. tenet_clk is the Ethernet clock period derived from Frame Manger clock, FM clock. tenet_clk=1/2 × FM_clock.
6. The actual setup time varies with the MDC slew rate. For a 180 Ω MDC pull-up and 470 pF load, the setup time is expected
to be 68 ns measured at 50% points. To ensure setup time is met, the EMI2 clock frequency may need to be reduced from
the default setting by selecting a larger clock divider via configuration of MDIO_CFG[MDIO_CLK_DIV] associated with
EMI2.
7. For recommended operating conditions, see Table 4.

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This figure shows the Ethernet management interface timing diagram.

tMDC

MDC

tMDCH

MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)

tMDKHDX

Figure 15. Ethernet management interface timing diagram

2.12.3 IEEE 1588 AC specifications

This table provides the IEEE 1588 AC timing specifications.
Table 28. IEEE 1588 AC timing specifications
For recommended operating conditions, see Table 4.

Parameter/Condition Symbol Min Typ Max Unit Notes

TSEC_1588_CLK_IN clock period tT1588CLK 6.4 — — ns 1, 3

TSEC_1588_CLK_IN duty cycle tT1588CLKH/ 40 50 60 % 2

tT1588CLK

TSEC_1588_CLK_IN peak-to-peak jitter tT1588CLKINJ — — 250 ps —

Rise time TSEC_1588_CLK_IN tT1588CLKINR 1.0 — 2.0 ns —

(20% –80%)

Fall time TSEC_1588_CLK_IN tT1588CLKINF 1.0 — 2.0 ns —

(80% –20%)

TSEC_1588_CLK_OUT clock period tT1588CLKOUT 2 × tT1588CLK — — ns —

TSEC_1588_CLK_OUT duty cycle tT1588CLKOTH/ 30 50 70 % —

tT1588CLKOUT

TSEC_1588_PULSE_OUT hold time tT1588OV 0.5 — For rev 1, rev 2.0, ns —

rev 2.1:
Max tT1588OV =
9.8ns
For rev 2.2:
Max tT1588OV =
5.3ns

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Table 28. IEEE 1588 AC timing specifications (continued)

For recommended operating conditions, see Table 4.

Parameter/Condition Symbol Min Typ Max Unit Notes

TSEC_1588_TRIG_IN pulse width tT1588TRIGH 2 × tT1588CLK_MAX — — ns 3

Notes:
1.TRX_CLK is the maximum clock period of Ethernet receiving clock selected by TMR_CTRL[CKSEL]. See the chip reference
manual for a description of TMR_CTRL registers.
2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference manual
for a description of the TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK are 2800, 280, and 56 ns, respectively.

This figure shows the data and command output AC timing diagram.

tT1588CLKOUT
tT1588CLKOUTH

TSEC_1588_CLK_OUT

tT1588OV

TSEC_1588_PULSE_OUT
TSEC_1588_ALARM_OUT

Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting. Otherwise, it
is counted starting at the falling edge.
Figure 16. IEEE 1588 output AC timing

This figure shows the data and command input AC timing diagram.

tT1588CLK
tT1588CLKH

TSEC_1588_CLK

TSEC_1588_TRIG_IN

tT1588TRIGH

Figure 17. IEEE 1588 input AC timing

2.13 USB interface

This section provides the AC electrical specifications for the USB interface.

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2.13.1 USB AC electrical specifications

This table describes the general timing parameters of the USB interface of the device.
Table 29. USB general timing parameters (ULPI mode only) 1,6
For recommended operating conditions, see Table 4.

Parameter Symbol1 Min Max Unit Notes

USB clock cycle time tUSCK 15 — ns 2, 3, 4, 5

Input setup to USB clock—all inputs tUSIVKH 4 — ns 2, 3, 4, 5
Input hold to USB clock—all inputs tUSIXKH 1 — ns 2, 3, 4, 5
USB clock to output valid—all outputs tUSKHOV — 7 ns 2, 3, 4, 5
Output hold from USB clock—all outputs tUSKHOX 2 — ns 2, 3, 4, 5
Note:
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for
the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes USB
timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to the USB clock.
3. All signals are measured from OVDD/2 of the rising edge of the USB clock to OVDD/2 of the signal.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through
the component pin is less than or equal to that of the leakage current specification.
6. When switching the data pins from outputs to inputs using the USBn_DIR pin, the output timings are violated on that cycle
because the output buffers are tristated asynchronously. This should not be a problem, because the PHY should not be
functionally looking at these signals on that cycle as per the ULPI specifications.

The following two figures provide the USB AC test load and signals, respectively.

Output Z0 = 50 Ω OVDD/2
RL = 50 Ω

Figure 18. USB AC test load

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Electrical characteristics

USB_CLK
tUSIXKH
tUSIVKH
Input signals

tUSKHOV tUSKHOX
Output signals:

Figure 19. USB signals

2.14 Integrated flash controller

This section describes the AC electrical specifications for the integrated flash controller.

2.14.1 Integrated flash controller AC timing specifications

This section describes the AC timing specifications for the integrated flash controller.
All output signal timings are relative to the falling edge of any IFC_CLK. The external circuit must use the rising edge of the
IFC_CLKs to latch the data.
All input timings are relative to the rising edge of IFC_CLKs.
This table describes the timing specifications of the integrated flash controller interface.
Table 30. Integrated flash controller timing specifications (OVDD = 1.8 V)
For recommended operating conditions, see Table 4

Parameter Symbol1 Min Max Unit Notes

IFC_CLK cycle time tIBK 12 — ns —

IFC_CLK duty cycle tIBKH/ tIBK 45 55 % —
IFC_CLK[n] skew to IFC_CLK[m] tIBKSKEW — ± 75 ps 2
Input setup tIBIVKH 4 — ns —
Input hold tIBIXKH 1 — ns —

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Table 30. Integrated flash controller timing specifications (OVDD = 1.8 V) (continued)
For recommended operating conditions, see Table 4

Parameter Symbol1 Min Max Unit Notes

Output delay tIBKLOV — 1.5 ns —

Output hold tIBKLOX –2 — ns 4
IFC_CLK to output high impedance for AD tIBKLOZ — 2 ns 3
Note:
1. All signals are measured from OVDD/2 of rising/falling edge of IFC_CLK to OVDD/2 of the signal in question.
2. Skew is measured between different IFC_CLK signals at OVDD/2.
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Here the negative sign means that the output transit happens earlier than the falling edge of IFC_CLK.

This figure shows the AC timing diagram.

IFC_CLK[m]
tIBIXKH
tIBIVKH
Input signals

tIBIVKL

tIBKLOV tIBKLOX

Output signals

tIBKLOZ
tIBKLOX

AD
(data phase)

Figure 20. Integrated flash controller signals

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Figure 20 applies to all the controllers that IFC supports.

• For input signals, the AC timing data is used directly for all controllers.
• For output signals, each type of controller provides its own unique method to control the signal timing. The final signal
delay value for output signals is the programmed delay plus the AC timing delay.
This figure shows how the AC timing diagram applies to GPCM. The same principle also applies to other controllers of IFC.

IFC_CLK

AD address read data address write data

teahc + tIBKLOV
teadc + tIBKLOV
AVD

tacse + tIBKLOV
CE_B
taco + tIBKLOV

OE_B trad + tIBKHOV

tch + tIBKLOV
tcs+ tIBKLOV
WE_B

twp + tIBKLOV

BCTL

read write

1
taco, trad, teahc, teadc, tacse, tcs, tch, twp are programmable. See the chip reference manual.
2
For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay
value for output signals is the programmed delay plus the AC timing delay.
Figure 21. GPCM output timing diagram

2.14.2 Test condition

This figure provides the AC test load for the integrated flash controller.

Output Z0 = 50 Ω OVDD/2
RL = 50 Ω

Figure 22. Integrated flash controller AC test load

2.15 Enhanced secure digital host controller (eSDHC)

This section describes the AC electrical specifications for the eSDHC interface. For the DC electrical specifications, see
Table 21.

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2.15.1 eSDHC AC timing specifications

This table provides the eSDHC AC timing specifications as defined in Figure 23.
Table 31. eSDHC AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol1 Min Max Unit Notes

SDHC_CLK clock frequency: fSHSCK — MHz 2, 4

eMMC Full-speed/high-speed mode 20/52
SDHC_CLK clock low time—full-speed/high-speed mode tSHSCKL 10/7 — ns 4
SDHC_CLK clock high time—full-speed/high-speed mode tSHSCKH 10/7 — ns 4
SDHC_CLK clock rise and fall times tSHSCKR/ — 3 ns 4
tSHSCKF
Input setup times: SDHC_CMD, SDHC_DATx, SDHC_CD to tSHSIVKH 2.5 — ns 3, 4, 5
SDHC_CLK
Input hold times: SDHC_CMD, SDHC_DATx, SDHC_CD to tSHSIXKH 2.5 — ns 4, 5
SDHC_CLK
Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tSHSKHOX –3 — ns 4, 5
Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tSHSKHOV — 3 ns 4, 5
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC
high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching
the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing
the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. In full-speed mode, the clock frequency value can be 0–20 MHz for an MMC card. In high-speed mode, the clock frequency
value can be 0–52 MHz for an MMC card.
3. To satisfy setup timing, one-way board-routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx
should not exceed 1 ns.
4. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF.
5. The parameter values apply to both full-speed and high-speed modes.

This figure provides the eSDHC clock input timing diagram.

eSDHC
VM VM VM
external clock
operational mode tSHSCKL tSHSCKH

tSHSCK
tSHSCKR tSHSCKF
VM = Midpoint Voltage (OVDD/2)
Figure 23. eSDHC clock input timing diagram

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Electrical characteristics

This figure provides the data and command input/output timing diagram.

Figure 24. eSDHC data and command input/output timing diagram referenced to clock

2.16 Multicore programmable interrupt controller

(MPIC) specifications
This section describes the AC electrical specifications for the multicore programmable interrupt controller.

2.16.1 MPIC AC timing specifications

This table provides the MPIC input and output AC timing specifications.
Table 32. MPIC input AC timing specifications
For recommended operating conditions, see Table 4.

Characteristic Symbol Min Max Unit Notes

MPIC inputs—minimum pulse width tPIWID 3 — SYSCLKs 1

Note:
1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs must be synchronized before use by any
external synchronous logic. MPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working
in edge triggered mode

2.17 JTAG controller

This section describes the AC electrical specifications for the IEEE 1149.6 (JTAG) interface.

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2.17.1 JTAG DC Electrical Characteristics

This table provides the JTAG DC electrical characteristics.
Table 33. JTAG DC Electrical Characteristics

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 1.25 — V 1

Input low voltage VIL — 0.6 V 1
Input current (OVIN = 0V or OVIN = OVDD) IIN — -100/+50 μA 2, 4
Output high voltage (OVDD = min, IOH = –0.5 mA) VOH 1.35 — V —
Output low voltage (OVDD = min, IOL = 0.5 mA) VOL — 0.4 V —
Notes:
1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 4.
2. The symbol VIN, in this case, represents the OVIN symbol found in Table 4.
3. For recommended operating conditions, see Table 4.
4. Per IEEE Std. 1149.1 specification, TDI, TMS, and TRST_B have internal pull-up that is always enabled.

2.17.2 JTAG AC timing specifications

This table provides the JTAG AC timing specifications as defined in Figure 25 through Figure 28.
Table 34. JTAG AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol1 Min Max Unit Notes

JTAG external clock frequency of operation fJTG 0 33.3 MHz —

JTAG external clock cycle time tJTG 30 — ns —
JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns —
JTAG external clock rise and fall times tJTGR/tJTGF 0 2 ns —
TRST_B assert time tTRST 25 — ns 2
Input setup times tJTDVKH 4 — ns —
Input hold times tJTDXKH 13 — ns —
Output valid times

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Electrical characteristics

Table 34. JTAG AC timing specifications (continued)

For recommended operating conditions, see Table 4.

Parameter Symbol1 Min Max Unit Notes

TCK to TDO output valid time tJTKLDV1 — 13 ns 4

TCK to boundary-scan data out times tJTKLDV2 — 34
Output hold times tJTKLDX 0 — ns 3
Note:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to
the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The
output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must
be added for trace lengths, vias, and connectors in the system.
4. Due to value of tJTKLDV1, after Update-IR or Update-DR transitions for EXTEST* or CLAMP instructions, a transition
through the optional Run-Test-Idle state is recommended to allow for board level propagation and setup times of observation
points.

This figure provides the AC test load for TDO and the boundary-scan outputs of the device.

Output Z0 = 50 Ω OVDD/2
RL = 50 Ω

Figure 25. AC test load for the JTAG interface

This figure provides the JTAG clock input timing diagram.

JTAG
VM VM VM
external clock

tJTKHKL tJTGR
tJTG tJTGF
VM = Midpoint voltage (OVDD/2)
Figure 26. JTAG clock input timing diagram

This figure provides the TRST_B timing diagram.

TRST_B VM VM

tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 27. TRST_B timing diagram

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This figure provides the TDI/TMS/TDO and boundary-scan data timing diagram.

JTAG
external clock VM VM
tJTDVKH
tJTDXKH
Boundary Input
data inputs data valid
tJTKLDV
tJTKLDX
Boundary
Output data valid
data outputs

VM = midpoint voltage (OVDD/2)

Figure 28. TDI/TMS/TDO and boundary-scan timing diagram

2.18 I2C interface

This section describes the DC and AC electrical characteristics for the I2C interface.

2.18.1 I2C DC electrical characteristics

This table provides the DC electrical characteristics for the I2C interfaces operating at 2.5 V.
Table 35. I2C DC electrical characteristics (DVDD = 2.5 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 1.7 — V 1

Input low voltage VIL — 0.7 V 1
Output low voltage (DVDD = min, IOL = 3 mA) VOL 0 0.4 V 2
Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3
Input current each I/O pin (input voltage is between 0.1 × DVDD and IIN — ±50 μA 4
0.9 × DVDD(max)
Capacitance for each I/O pin CI — 10 pF —
Notes:
1. The min VILand max VIH values are based on the respective min and max QVIN values found in Table 4.
2. Output voltage (open drain or open collector) condition = 2 mA sink current.
3. See the chip reference manual for information about the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if DVDD is switched off.

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This table provides the DC electrical characteristics for the I2C interfaces operating at 1.8 V.
Table 36. I2C DC electrical characteristics (DVDD = 1.8 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 1.25 — V 1

Input low voltage VIL — 0.6 V 1
Output low voltage (DVDD = min, IOL = 1 mA) VOL 0 0.36 V 2
Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3
Input current each I/O pin (input voltage is between 0.1 × DVDD and IIN — ±50 μA 4
0.9 × DVDD(max)
Capacitance for each I/O pin CI — 10 pF —
Notes:
1. The min VILand max VIH values are based on the respective min and max QVIN values found in Table 4.
2. Output voltage (open drain or open collector) condition = 2 mA sink current.
3. See the chip reference manual for information about the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if DVDD is switched off.

2.18.2 I2C AC timing specifications

This table provides the AC timing parameters for the I2C interfaces.
Table 37. I2C AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol1 Min Max Unit Notes

SCL clock frequency fI2C 0 400 kHz 2

Low period of the SCL clock tI2CL 1.3 — μs —
High period of the SCL clock tI2CH 0.6 — μs —
Setup time for a repeated START condition tI2SVKH 0.6 — μs —
Hold time (repeated) START condition (after this period, the first tI2SXKL 0.6 — μs —
clock pulse is generated)
Data setup time tI2DVKH 100 — ns —
Data input hold time: tI2DXKL μs 3
CBUS compatible masters — —
I2C bus devices 0 —
Data output delay time tI2OVKL — 0.9 μs 4
Setup time for STOP condition tI2PVKH 0.6 — μs —
Bus free time between a STOP and START condition tI2KHDX 1.3 — μs —

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Table 37. I2C AC timing specifications (continued)

For recommended operating conditions, see Table 4.

Parameter Symbol1 Min Max Unit Notes

Noise margin at the LOW level for each connected device VNL 0.1 × DVDD — V —
(including hysteresis)
Noise margin at the HIGH level for each connected device VNH 0.2 × DVDD — V —
(including hysteresis)
Capacitive load for each bus line Cb — 400 pF —
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Determining the I2C Frequency Divider Ratio for SCL
(AN2919).
3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal)
to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP condition. When
the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL and SDA are
balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns SDA output delay time
is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the chip as transmitter, see
Determining the I2C Frequency Divider Ratio for SCL (AN2919).
4. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.

This figure provides the AC test load for the I2C.

Output Z0 = 50 Ω ODVDD/2
RL = 50 Ω

Figure 29. I2C AC test load

This figure shows the AC timing diagram for the I2C bus.

SDA
tI2DVKH tI2KHKL tI2KHDX
tI2CL tI2SXKL

SCL
tI2SXKL tI2CH tI2SVKH tI2PVKH
tI2DXKL,tI2OVKL
S Sr P S
2
Figure 30. I C Bus AC timing diagram

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2.19 GPIO interface

This section describes the AC electrical characteristics for the GPIO interface.

2.19.1 GPIO AC timing specifications

This table provides the GPIO input and output AC timing specifications.
Table 38. GPIO Input AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Unit Notes

GPIO inputs—minimum pulse width tPIWID 20 ns 1

Notes:
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.

This figure provides the AC test load for the GPIO.

Output Z0 = 50 Ω (D/O)VDD/2
RL = 50 Ω

Figure 31. GPIO AC test load

2.20 Timers interface

This section describes the AC electrical characteristics for the Timers interface.

2.20.1 Timers AC timing specifications

This table provides the Timers input AC timing specifications.
Table 39. GPIO input AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Unit Notes

Timers inputs-minimum pulse width tTIWID timers ns 1, 2

clock/2
Notes:
1. The maximum allowed frequency of timer outputs is 1/(timers clock source/2). Configure the timer modules appropriately.
2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any
external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.

This figure provides the AC test load for the timers.

Output Z0 = 50 Ω OVDD/2
RL = 50 Ω

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2.21 Asynchronous signal timing

This table provides AS specifications for the asynchronous signal timing specifications.
Table 40. Signal timing

Characteristics Symbol Type Min

Input tIN Asynchronous One SYSCLK cycle

Output tOUT Asynchronous Application-dependent
Note: Input value relevant for DMA, EVT_B[9–0] only.

The following interfaces use the specified asynchronous signals:

• Debug port—Signals EVT_B[9–0]
• DMA signals
• Interrupt outputs—Signals IRQn, CKSTP_OUT_B

2.22 CPRI interface signals

This section describes the DC and AC electrical characteristics for the CPRI interface signals.

2.22.1 CPRI signals DC electrical characteristics

This table provides the DC electrical characteristics for the CPRI LOS interfaces operating at 2.5 V.
Table 41. CPRI signals DC electrical characteristics (DVDD = 2.5 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 1.7 — V 1

Input low voltage VIL — 0.7 V 1
Output high voltage VOH 2.0 — V —
(OVDD/DVDD = min, IOH = –2 mA)
Output low voltage (OVDD/DVDD = min, IOL = 2 mA) VOL 0 0.4 V —
Input current for each I/O pin (input voltage is between 0.1 × OVDD/DVDD II –40 40 μA —
and 0.9 × OVDD/DVDD(max)
Notes:
1. The min VILand max VIH values are based on the respective min and max DVIN values found in Table 4.

2.22.2 CPRI signals AC specifications

This table provides the CPRI signals timing specifications.
Table 42. CPRI signals timing specifications
For recommended operating conditions, see Table 4.

Parameter/condition Symbol Min Typ Max Unit Notes

CP_SYNC period tCP-SYNCCLK — 10 — ms 1, 3

CP_SYNC pulse width (output) tCP-SYNCCLKWDO 64 — 512 ns —

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Table 42. CPRI signals timing specifications (continued)

For recommended operating conditions, see Table 4.

Parameter/condition Symbol Min Typ Max Unit Notes

CP_SYNC pulse width (input) tCP-SYNCCLKWDI 12 — 0.5 * tCP-SYNCCLK ns —

CP_RCLK frequency tCP-RCLK — 122.88 — MHz 2

Notes:
1.TCP-SYNCCLK is the required sync period for both input or output sync.
2. The recovery output clock frequency. See Table 44 for details on using CP_RCLK as RefClk for RE to SLAVE
configuration.
3. CP_SYNC and CPRI SerDes reference clock are generated from a common source with the following ratio:
tCP_SYNCCLK = 1228800 * tREFCLK

2.23 High-speed serial interfaces (HSSI)

The chip features a serializer/deserializer (SerDes) interface to be used for high-speed serial interconnect applications. The
SerDes interface can be used for PCI Express, Serial RapidIO, XAUI, XFI, SGMII, 10 GBase-KR, CPRI, Aurora, and
2.5x SGMII data transfers.
This section describes the common portion of SerDes DC electrical specifications: the DC requirement for SerDes reference
clocks. The SerDes data lane’s transmitter (Tx) and receiver (Rx) reference circuits are also shown.

2.23.1 Signal terms definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines the terms that are used in
the description and specification of differential signals.
This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This
figure shows the waveform for either a transmitter output (SD_TXn and SD_TXn_B) or a receiver input (SD_RXn and
SD_RXn_B). Each signal swings between A volts and B volts where A > B.
SD_TXn or
SD_RXn
A volts

Vcm = (A + B)/2
SD_TXn_B or
SD_RXn_B
B volts

Differential swing, VID or VOD = A – B

Differential peak voltage, VDIFFp = |A – B|

Differential peak-to-peak voltage, VDIFFpp = 2 × VDIFFp (not shown)

Figure 32. Differential voltage definitions for transmitter or receiver

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Using this waveform, the definitions are as shown in the following list. To simplify the illustration, the definitions assume that
the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment:
Single-Ended Swing The transmitter output signals and the receiver input signals SD_TXn, SD_TXn_B, SD_RXn, and
SD_RXn_B each have a peak-to-peak swing of A – B volts. This is also referred as each signal
wire’s single-ended swing.
Differential Output Voltage, VOD (or Differential Output Swing)
The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of
the two complimentary output voltages: VSD_TXn – VSD_TXn_B. The VOD value can be either
positive or negative.
Differential Input Voltage, VID (or Differential Input Swing)
The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two
complimentary input voltages: VSD_RXn – VSD_RXn_B. The VID value can be either positive or
negative.
Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal
is defined as the differential peak voltage, VDIFFp = |A – B| volts.
Differential Peak-to-Peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter
output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,
VDIFFp-p = 2 × VDIFFp = 2 × |(A – B)| volts, which is twice the differential swing in amplitude, or
twice of the differential peak. For example, the output differential peak-to-peak voltage can also
be calculated as VTX-DIFFp-p = 2 × |VOD|.
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SD_TXn_B, for
example) from the non-inverting signal (SD_TXn_B, for example) within a differential pair. There
is only one signal trace curve in a differential waveform. The voltage represented in the differential
waveform is not referenced to ground. See Figure 37 as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each conductor of
a balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out = (VSD_TXn + VSD_TXn_B) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two
complimentary output voltages within a differential pair. In a system, the common mode voltage
may often differ from one component’s output to the other’s input. It may be different between the
receiver input and driver output circuits within the same component. It is also referred to as the DC
offset on some occasions.
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended swing for each signal.
Because the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing
(VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV
and –500 mV. In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage
(VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.

2.23.2 SerDes reference clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks inputs are SD1_REF[1:2]_CLK and SD1_REF[1:2]_CLK_B for SerDes 1,
SD2_REF[1:2]_CLK and SD2_REF[1:2]_CLK_B for SerDes 2.

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SerDes 1–2 may be used for various combinations of the following IP blocks based on the RCW Configuration field
SRDS_PRTCLn:
• SerDes 1: SGMII (1.25 and 3.125 Gbps), CPRI (1.2288, 2.4576, 3.072, 4.9152, 6.144, 9.8304 Gbps), Aurora (2.5,
3.125, 5 Gbps)
• SerDes 2: SGMII (1.25 and 3.125 Gbps), SRIO(2.5, 3.125, 5 Gbps), XAUI (3.125 Gbps), PCIe (2.5, 5 Gbps),
XFI/10 GBase-KR (10.3125 Gbps), Aurora (2.5, 3.125, 5 Gbps).
The following sections describe the SerDes reference clock requirements and provide application information.

2.23.2.1 PCIe SerDes spread-spectrum clock source recommendations

SDn_REFn_CLK/SDn_REFn_CLK_B are designed to work with spread spectrum clock for PCI Express protocol only with
the spreading specification defined in Table 43. When using spread spectrum clocking for PCI Express, both ends of the link
partners should use the same reference clock. For best results, a source without significant unintended modulation must be used.
The spread spectrum clocking cannot be used if the same SerDes reference clock is shared with other non-spread spectrum
supported protocols. For example, if the spread spectrum clocking is desired on a SerDes reference clock for PCI Express and
the same reference clock is used for any other protocol such as SGMII or SRIO due to the SerDes lane usage mapping option,
spread spectrum clocking cannot be used at all.

Table 43. SerDes spread-spectrum clock source recommendations

At recommended operating conditions. See Table 4.

Parameter Min Max Unit Notes

Frequency modulation 30 33 kHz —

Frequency spread +0 –0.5 % 1

Note:
1. Only down-spreading is allowed.

2.23.2.2 SerDes reference clock receiver characteristics

This figure shows a receiver reference diagram of the SerDes reference clocks.

50 Ω

SDn_REFn_CLK

Input
Amp
SDn_REFn_CLK_B

50 Ω

Figure 33. Receiver of SerDes reference clocks

The characteristics of the clock signals are as follows:

• The SerDes receivers core power supply voltage requirements (SVDD) are as specified in Section 2.1.2,
“Recommended operating conditions.”

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• The SerDes reference clock receiver reference circuit structure is as follows:

— The SDn_REFn_CLK and SDn_REFn_CLK_B are internally AC-coupled differential inputs as shown in
Figure 33. Each differential clock input (SDn_REFn_CLK or SDn_REFn_CLK_B) has on-chip 50-Ω termination
to SGND followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the differential mode and
single-ended mode descriptions below for detailed requirements.
• The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V ÷ 50 = 8 mA)
while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle
can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such
that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
— If the device driving the SDn_REFn_CLK and SDn_REFn_CLK_B inputs cannot drive 50 Ω to SGND DC or the
drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled
off-chip.
• The input amplitude requirement is described in detail in the following sections.

2.23.2.3 DC-level requirement for SerDes reference clocks

The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
• Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-to-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For an external DC-coupled connection, as described in Section 2.23.2.2, “SerDes reference clock receiver
characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) as between 100 mV and 400 mV. Figure 34 shows the SerDes reference clock input requirement
for DC-coupled connection scheme.

200 mV < Input amplitude or differential peak < 800 mV

SDn_REFn_CLK
Vmax < 800 mV

100 mV < Vcm < 400 mV

SDn_REFn_CLK_B
Vmin >0V
Figure 34. Differential reference clock input DC requirements (external DC-coupled)

— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Because the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock

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Electrical characteristics

receiver operate in different common mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing
below and above the common mode voltage (SGND). Figure 35 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.

200 mV < Input amplitude or differential peak < 800 mV

SDn_REFn_CLK
Vmax < Vcm + 400 mV

Vcm

SDn_REFn_CLK_B Vmin > Vcm – 400 mV

Figure 35. Differential reference clock input DC requirements (external AC-coupled)

• Single-Ended Mode
— The reference clock can also be single-ended. The SDn_REFn_CLK input amplitude (single-ended swing) must
be between 400 mV and 800 mV peak-to-peak (from VMIN to VMAX) with SDn_REFn_CLK_B either left
unconnected or tied to ground.
— The SDn_REFn_CLK input average voltage must be between 200 and 400 mV. Figure 36 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SDn_REFn_CLK_B) through the same source impedance as the clock input (SDn_REFn_CLK) in use.

400 mV < SDn_REFn_CLK input amplitude < 800 mV

SDn_REFn_CLK

0V

SDn_REFn_CLK_B
Figure 36. Single-ended reference clock input DC requirements

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2.23.2.4 AC requirements for SerDes reference clocks

This table lists the AC requirements for SerDes reference clocks for protocols running at data rates up to 8 Gb/s.
This includes PCI Express (2.5, 5 GT/s), SGMII (1.25Gbps), 2.5x SGMII (3.125Gbps), Serial RapidIO (2.5, 3.125, 5 Gbps),
Aurora (2.5, 3.125, 5 Gbps), CPRI (1.2288, 2.4576, 3.072, 4.9152, 6.144 Gbps), XAUI (3.125 Gbps). SerDes reference clocks
to be guaranteed by the customer’s application design.
Table 44. SDn_REFn_CLK and SDn_REFn_CLK_B input clock requirements (SVDD= 1.0 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

SDn_REFn_CLK/ SDn_REFn_CLK_B frequency range tCLK_REF — 100/122.88/ — MHz 1

125/156.25
SDn_REFn_CLK/ SDn_REFn_CLK_B clock frequency tCLK_TOL –300 — 300 ppm 7, 10
tolerance
For PEX Gen 1, 2
SDn_REFn_CLK/ SDn_REFn_CLK_B clock frequency tCLK_TOL –100 — 100 ppm 8, 10
tolerance
For SGMII, 2.5x SGMII, sRIO, XAUI, Aurora, CPRI
SDn_REFn_CLK/ SDn_REFn_CLK_B reference clock tCLK_DUTY 40 50 60 % —
duty cycle (measured at 1.6 V)
SDn_REFn_CLK/ SDn_REFn_CLK_B max tCLK_DJ — — 42 ps —
deterministic peak-to-peak jitter at 10-6 BER
SDn_REFn_CLK/ SDn_REFn_CLK_B total reference tCLK_TJ — — 86 ps 2
clock jitter at 10-6 BER (peak-to-peak jitter at refClk
input)
SDn_REFn_CLK/ SDn_REFn_CLK_B Allowed cut-off tCLK_TC — — 300 Hz 9
frequency of REC-slave synchronization mechanism
SDn_REFn_CLK/ SDn_REFn_CLK_B df/f0 contribution tCLK_TF –0.002 — 0.002 ppm 9
of jitter between REC master to REC slave to the
frequency accuracy budget
SDn_REFn_CLK/ SDn_REFn_CLK_B rising/falling tCLKRR/tCLKFR 1 — 4 V/ns 3
edge rate

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Table 44. SDn_REFn_CLK and SDn_REFn_CLK_B input clock requirements (SVDD= 1.0 V) (continued)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

Differential input high voltage VIH VCM + — — mV 4

200mV
Differential input low voltage VIL — — VCM – mV 4
200mV
Rising edge rate (SDn_REFn_CLK) to falling edge rate Rise-Fall — — 20 % 5, 6
(SDn_REFn_CLK_B) matching Matching
Notes:
1. Caution: Only 100, 122.88, 125 and 156.25 have been tested. In-between values do not work correctly with the rest of the
system.
2. Limits from PCI Express CEM Rev 2.0
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REFn_CLK minus
SDn_REFn_CLK_B). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV
measurement window is centered on the differential zero crossing. See Figure 37.
4. Measurement taken from differential waveform.VCM is the common mode voltage
5. Measurement taken from single-ended waveform
6. Matching applies to rising edge for SDn_REFn_CLK and falling edge rate for SDn_REFn_CLK_B. It is measured using a
200 mV window centered on the median cross point where SDn_REFn_CLK rising meets SDn_REFn_CLK_B falling. The
median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The
rise edge rate of SDn_REFn_CLK must be compared to the fall edge rate of SDn_REFn_CLK_B, the maximum allowed
difference should not exceed 20% of the slowest edge rate. See Figure 38.
7. For PCI Express (2.5, 5 GT/s)
8. For SGMII, 2.5x SGMII, sRIO, XAUI, XFI, Aurora, CPRI.
9. This spec is applied to CPRI protocol clocks only. The TCLK_TC is to comply with R-17 requirement in the protocol. TCLK_TF,
to comply to R-18 requirement.
10. When two or more protocols share the same PLL on a SerDes module, the tightest SDn_REFn_CLK/ SDn_REFn_CLK_B
clock frequency tolerance must be followed.

This table lists the AC requirements for SerDes reference clocks for protocols running at data rates greater than 8 Gb/s. This
includes XFI/10 GBase-KR (10.3125 Gbps) and CPRI (9.8304 Gbps). SerDes reference clocks to be guaranteed by the
customer’s application design.
Table 45. SDn_REFn_CLK and SDn_REFn_CLK_B input clock requirements (SVDD = 1.0 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

SDn_REFn_CLK/ SDn_REFn_CLK_B frequency range tCLK_REF — 122.88/ — MHz 1

156.25
SDn_REFn_CLK/ SDn_REFn_CLK_B clock frequency tolerance tCLK_TOL –100 — 100 ppm 7
SDn_REFn_CLK/ SDn_REFn_CLK_B reference clock duty cycle tCLK_DUTY 40 50 60 % —
(measured at 1.6 V)
SDn_REFn_CLK/ SDn_REFn_CLK_B single side band noise @1 kHz — — –85 dBC/Hz 2
SDn_REFn_CLK/ SDn_REFn_CLK_B single side band noise @10 kHz — — –108 dBC/Hz 2
SDn_REFn_CLK/ SDn_REFn_CLK_B single side band noise @100 kHz — — –128 dBC/Hz 2

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Table 45. SDn_REFn_CLK and SDn_REFn_CLK_B input clock requirements (SVDD = 1.0 V) (continued)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

SDn_REFn_CLK/ SDn_REFn_CLK_B single side band noise @1 MHz — — –138 dBC/Hz 2

SDn_REFn_CLK/ SDn_REFn_CLK_B single side band noise @10MHz — — –138 dBC/Hz 2
SDn_REFn_CLK/ SDn_REFn_CLK_B random jitter (1.2 MHz to tCLK_RJ — — 0.8 ps —
15 MHz)
SDn_REFn_CLK/ SDn_REFn_CLK_B total reference clock jitter tCLK_TJ — — 11 ps —
at 10-12 BER (1.2 MHz to 15 MHz)
SDn_REFn_CLK/ SDn_REFn_CLK_B spurious noise (1.2 MHz to — — — –75 dBC —
15 MHz)
SDn_REFn_CLK/ SDn_REFn_CLK_B Allowed cut-off frequency tCLK_TC — — 300 Hz 8
of REC-slave synchronization mechanism
SDn_REFn_CLK/ SDn_REFn_CLK_B df/f0 contribution of jitter tCLK_TF –0.002 — 0.002 ppm 8
between REC master to REC slave to the frequency accuracy
budget
SDn_REFn_CLK/ SDn_REFn_CLK_B rising/falling edge rate tCLKRR/ 1 — 4 V/ns 3
tCLKFR
Differential input high voltage VIH VCM + — — mV 4
200mV
Differential input low voltage VIL — — VCM - mV 4
200mV
Rising edge rate (SDn_REFn_CLK) to falling edge rate Rise-Fall — — 20 % 5, 6
(SDn_REFn_CLK_B) matching Matching
Notes:
1. Caution: Only 122.88 and 156.25 have been tested. In-between values do not work correctly with the rest of the system.
2. Per XFP Spec. Rev 4.5, the Module Jitter Generation spec at XFI Optical Output is 10mUI (RMS) and 100 mUI (p-p). In the
CDR mode the host is contributing 7 mUI (RMS) and 50 mUI (p-p) jitter.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REFn_CLK minus SDn_REFn_CLK_B).
The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 37.
4. Measurement taken from differential waveform
5. Measurement taken from single-ended waveform
6. Matching applies to rising edge for SDn_REFn_CLK and falling edge rate for SDn_REFn_CLK_B. It is measured using a
200 mV window centered on the median cross point where SDn_REFn_CLK rising meets SDn_REFn_CLK_B falling. The
median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The
rise edge rate of SDn_REFn_CLK must be compared to the fall edge rate of SDn_REFn_CLK_B, the maximum allowed
difference should not exceed 20% of the slowest edge rate. See Figure 38.
7. When two or more protocols share the same PLL on a SerDes module, the tightest SDn_REFn_CLK/ SDn_REFn_CLK_B
clock frequency tolerance must be followed.
8. This spec is applied to CPRI protocol clocks only. The TCLK_TC is to comply with R-17 requirement in the protocol. TCLK_TF, to
comply to R-18 requirement.

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Rise edge rate Fall edge rate

VIH = +200 mV
0.0 V
VIL = –200 mV
SDn_REFn_CLK –
SDn_REFn_CLK_B

Figure 37. Differential measurement points for rise and fall time

TFALL TRISE
SDn_REFn_CLK_B SDn_REFn_CLK_B

VCROSS MEDIAN + 100 mV

VCROSS MEDIAN VCROSS MEDIAN

VCROSS MEDIAN – 100 mV

SDn_REFn_CLK SDn_REFn_CLK

Figure 38. Single-ended measurement points for rise and fall time matching

2.23.3 SerDes transmitter and receiver reference circuits

This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.

SDn_TXn SDn_RXn

50 Ω
Transmitter 100 Ω Receiver

SDn_TXn_B SDn_RXn_B 50 Ω

Figure 39. SerDes transmitter and receiver reference circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below based on the application
usage
• Section 2.23.4, “PCI Express interface”
• Section 2.23.5, “Serial RapidIO (sRIO) interface”
• Section 2.23.6, “XAUI interface”
• Section 2.23.7, “Aurora interface”
• Section 2.23.8, “SGMII interface”
• Section 2.23.9, “XFI interface”
• Section 2.23.10, “10GBase-KR interface”

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• Section 2.23.11, “CPRI interface”

Note that external AC-coupling capacitor is required for the above serial transmission protocols with the capacitor value defined
in the specification of each protocol section.

2.23.4 PCI Express interface

This section describes the clocking dependencies as well as the DC and AC electrical specifications for the PCI Express bus.

2.23.4.1 Clocking dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a ± 300 ppm tolerance.

2.23.4.2 PCI Express clocking requirements for

SDn_REFn_CLK/SDn_REFn_CLK_B
SerDes 2 (SD2_REF[1:2]_CLK and SD2_REF[1:2]_CLK_B) may be used for various SerDes PCI Express configurations
based on the RCW Configuration field SRDS_PRTCL_S2. PCI Express is supported on SerDes 2 only.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”

2.23.4.3 PCI Express DC physical layer specifications

This section contains the DC specifications for the physical layer of PCI Express on this chip.

2.23.4.3.1 PCI Express DC physical layer transmitter specifications

This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all transmitters. The parameters
are specified at the component pins.
Table 46. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Units Notes

Differential peak-to-peak VTX-DIFFp-p 800 1000 1200 mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-|

output voltage

De-emphasized differential VTX-DE-RATIO 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and following
output voltage (ratio) bits after a transition divided by the VTX-DIFFp-p of
the first bit after a transition.

DC differential transmitter ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential mode low impedance
impedance

Transmitter DC impedance ZTX-DC 40 50 60 Ω Required transmitter D+ as well as D– DC

Impedance during all states

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This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential output at all transmitters. The parameters
are specified at the component pins.
Table 47. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Units Notes

Differential peak-to-peak VTX-DIFFp-p 800 1000 1200 mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-|

output voltage
Low power differential VTX-DIFFp-p_low 400 500 1200 mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-|
peak-to-peak output voltage

De-emphasized differential VTX-DE-RATIO-3.5dB 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and
output voltage (ratio) following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition.

De-emphasized differential VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB Ratio of the VTX-DIFFp-p of the second and
output voltage (ratio) following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition.
DC differential transmitter ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential mode low
impedance impedance

Transmitter DC Impedance ZTX-DC 40 50 60 Ω Required transmitter D+ as well as D– DC

impedance during all states

2.23.4.3.2 PCI Express DC physical layer receiver specifications

This section discusses the PCI Express DC physical layer receiver specifications for 2.5 GT/s and 5 GT/s.
This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are
specified at the component pins.
Table 48. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (SVDD = 1.0 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Units Notes

Differential input peak-to-peak voltage VRX-DIFFp-p 120 1000 1200 mV VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-|
See Note 1.

DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential mode

impedance.
See Note 2

DC single input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as D– DC

Impedance (50 ± 20% tolerance).
See Notes 1 and 2.

Powered down DC input impedance ZRX-HIGH-IMP-DC 50 — — kΩ Required receiver D+ as well as D– DC

Impedance when the receiver
terminations do not have power.
See Note 3.

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Table 48. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (SVDD = 1.0 V) (continued)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Units Notes

Electrical idle detect threshold VRX-IDLE-DET-DIF 65 — 175 mV VRX-IDLE-DET-DIFFp-p =

Fp-p 2 × |VRX-D+ – VRX-D–|
Measured at the package pins of the
receiver

Notes:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there
is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the receiver ground.

This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are
specified at the component pins.
Table 49. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (SVDD = 1.0 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Units Notes

Differential input peak-to-peak voltage VRX-DIFFp-p 120 1000 1200 mV VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D–|
See Note 1.

DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential mode

impedance. See Note 2

DC input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as D–

DC Impedance (50 ± 20%
tolerance). See Notes 1 and 2.

Powered down DC input impedance ZRX-HIGH-IMP-DC 50 — — kΩ Required receiver D+ as well as D–

DC Impedance when the receiver
terminations do not have power.
See Note 3.

Electrical idle detect threshold VRX-IDLE-DET-DIF 65 — 175 mV VRX-IDLE-DET-DIFFp-p =

Fp-p 2 × |VRX-D+ – VRX-D–|
Measured at the package pins of the
receiver

Notes:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the receiver ground.

2.23.4.4 PCI Express AC physical layer specifications

This section contains the AC specifications for the physical layer of PCI Express on this device.

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Electrical characteristics

2.23.4.4.1 PCI Express AC physical layer transmitter specifications

This section discusses the PCI Express AC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all transmitters. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 50. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Units Notes

Unit interval UI 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not
account for spread-spectrum clock dictated
variations.

Minimum transmitter eye TTX-EYE 0.75 — — UI The maximum transmitter jitter can be derived
width as TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI.
Does not include spread-spectrum or RefCLK
jitter. Includes device random jitter at 10-12.
See Notes 1 and 2.

Maximum time between the TTX-EYE-MEDIAN- — — 0.125 UI Jitter is defined as the measurement variation
jitter median and maximum to- of the crossing points (VTX-DIFFp-p = 0 V) in
deviation from the median MAX-JITTER relation to a recovered transmitter UI. A
recovered transmitter UI is calculated over
3500 consecutive unit intervals of sample
data. Jitter is measured using all edges of the
250 consecutive UI in the center of the 3500 UI
used for calculating the transmitter UI.
See Notes 1 and 2.

AC coupling capacitor CTX 75 — 200 nF All transmitters must be AC coupled. The AC

coupling is required either within the media or
within the transmitting component itself.
See Note 3.

Notes:
1. Specified at the measurement point into a timing and voltage test load as shown in Figure 41 and measured over any 250
consecutive transmitter UIs.
2. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of
the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not
the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is
approximately equal as opposed to the averaged time value.
3. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.

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This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all transmitters. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 51. PCI Express 2.0 (5 GT/s) differential transmitter output AC specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Units Notes

Unit Interval UI 199.94 200.00 200.06 ps Each UI is 200 ps ± 300 ppm. UI does not
account for spread-spectrum clock dictated
variations.

Minimum transmitter eye width TTX-EYE 0.75 — — UI The maximum transmitter jitter can be
derived as:
TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI.
See Note 1.

Transmitter RMS deterministic TTX-HF-DJ-DD — — 0.15 ps —

jitter > 1.5 MHz
Transmitter RMS deterministic TTX-LF-RMS — 3.0 — ps Reference input clock RMS jitter (< 1.5 MHz)
jitter < 1.5 MHz at pin < 1 ps

AC coupling capacitor CTX 75 — 200 nF All transmitters must be AC coupled. The AC

coupling is required either within the media
or within the transmitting component itself.
See Note 2.

Notes:
1. Specified at the measurement point into a timing and voltage test load as shown in Figure 41 and measured over any 250
consecutive transmitter UIs.
2. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.

2.23.4.4.2 PCI Express AC physical layer receiver specifications.

This section discusses the PCI Express AC physical layer receiver specifications for 2.5 GT/s and 5 GT/s.
This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are
specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 52. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Units Notes

Unit Interval UI 399.88 400.00 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations.

Minimum receiver eye width TRX-EYE 0.4 — — UI The maximum interconnect media and
transmitter jitter that can be tolerated by the
receiver can be derived as
TRX-MAX-JITTER = 1 – TRX-EYE= 0.6 UI.
See Notes 1 and 2.

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Electrical characteristics

Table 52. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications (continued)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Units Notes

Maximum time between the TRX-EYE-MEDIAN- — — 0.3 UI Jitter is defined as the measurement
jitter median and maximum to-MAX-JITTER variation of the crossing points
deviation from the median. (VRX-DIFFp-p = 0 V) in relation to a recovered
transmitter UI. A recovered transmitter UI is
calculated over 3500 consecutive unit
intervals of sample data. Jitter is measured
using all edges of the 250 consecutive UI in
the center of the 3500 UI used for calculating
the transmitter UI.
See Notes 1, 2 and 3.

Notes:
1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 41 must be used as
the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same
reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
2. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter
median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the
averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter
UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
3. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a fit
algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental
and simulated data.

This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are
specified at the component pins. The AC timing specifications do not include RefClk jitter. If spread spectrum clocking is
desired, the common clock must be used.
Table 53. PCI Express 2.0 (5 GT/s) differential receiver input AC specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Units Notes

Unit Interval UI 199.40 200.00 200.06 ps Each UI is 200 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations.

Max receiver inherent timing TRX-TJ-CC — — 0.4 UI The maximum inherent total timing error for
error common and separate RefClk receiver
architecture.

Max receiver inherent TRX-DJ-DD-CC — — 0.30 UI The maximum inherent deterministic timing
deterministic timing error error for common and separate RefClk
receiver architecture

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0.03 MHz 100 MHz

Sj sweep range

1.0 UI 20 dB
Rj (ps RMS)

decade
Sj (UI PP)

Sj
0.1 UI

Rj
~ 3.0 ps RMS

0.01 MHz 0.1 MHz 1.0 MHz 10 MHz 100 MHz 1000 MHz

Figure 40. Swept sinusoidal jitter mask

2.23.4.5 Test and measurement load

The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be
connected to the test/measurement load within 0.2 inches of that load, as shown in the following figure.

NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary. If the vendor does not explicitly
state where the measurement point is located, the measurement point is assumed to be the
D+ and D– package pins.

D+ package pin
C = CTX
Transmitter
silicon
+ package
C = CTX
D– package pin R = 50 Ω R = 50 Ω

Figure 41. Test/Measurement load

2.23.5 Serial RapidIO (sRIO) interface

This section describes the DC and AC electrical specifications for the Serial RapidIO interface of the LP-Serial physical layer.
The electrical specifications cover both single and multiple-lane links. Two transmitters (short run and long run) and a single
receiver are specified for each of three baud rates: 2.50, 3.125 and 5 GBaud.
Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to driving two connectors
across a backplane. A single receiver specification is given that accepts signals from both the short run and long run transmitter
specifications.

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Electrical characteristics

The short run transmitter must be used mainly for chip-to-chip connections on either the same printed circuit board or across a
single connector. This covers the case where connections are made to a mezzanine (daughter) card. The minimum swings of the
short run specification reduce the overall power used by the transceivers.
The long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. This
allows a user to drive signals across two connectors and a backplane.
All unit intervals are specified with a tolerance of ± 100 ppm. The worst case frequency difference between any transmit and
receive clock is 200 ppm.
To ensure interoperability between drivers and receivers of different vendors and technologies, AC coupling at the receiver
input must be used.

2.23.5.1 Signal definitions

This section defines the terms used in the description and specification of the differential signals used by the LP-Serial links.
The following figure shows how the signals are defined. The figures show waveforms for either a transmitter output (TD and
TD_B) or a receiver input (RD and RD_B). Each signal swings between A volts and B volts where A > B. Using these
waveforms, the definitions are as follows:
• The transmitter output signals and the receiver input signals—TD, TD_B, RD, and RD_B—each have a peak-to-peak
swing of A – B volts.
• The differential output signal of the transmitter, VOD, is defined as VTD – VTD_B
• The differential input signal of the receiver, VID, is defined as VRD – VRD_B
• The differential output signal of the transmitter and the differential input signal of the receiver each range from A – B
to –(A – B) volts
• The peak value of the differential transmitter output signal and the differential receiver input signal is A – B volts.
• The peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is
2 × (A – B) volts.

TD or RD
A volts

TD_B or RD_B
B volts

Differential peak-to-peak = 2 × (A – B)

Figure 42. Differential peak-to-peak voltage of transmitter or receiver

To illustrate these definitions using real values, consider the case of a CML (current mode logic) transmitter that has a common
mode voltage of 2.25 V, and each of its outputs TD and TD_B, has a swing that goes between 2.5 V and 2.0 V. Using these
values, the peak-to-peak voltage swing of the signals TD and TD_B is 500 mV p-p. The differential output signal ranges
between 500 mV and –500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.

2.23.5.2 Equalization
With the use of high-speed serial links, the interconnect media causes degradation of the signal at the receiver and produces
effects such as inter-symbol interference (ISI) or data-dependent jitter. This loss can be large enough to degrade the eye opening
at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The
most common equalization techniques that can be used are as follows:

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• De-emphasis on the transmitter

• A passive high-pass filter network placed at the receiver, often referred to as passive equalization.
• The use of active circuits in the receiver, often referred to as adaptive equalization.

2.23.5.3 Serial RapidIO clocking requirements for SDn_REFn_CLK and

SDn_REFn_CLK_B
SerDes 2 (SD2_REF[1:2]_CLK and SD2_REF[1:2]_CLK_B) may be used for various SerDes Serial RapidIO configurations
based on the RCW Configuration field SRDS_PRTCL_S2. Serial RapidIO is supported on SerDes 2 only.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”

2.23.5.4 DC requirements for Serial RapidIO

This section explains the DC requirements for the Serial RapidIO interface.

2.23.5.4.1 DC Serial RapidIO transmitter specifications

This table defines the transmitter DC specifications for Serial RapidIO operating at 2.5 and 3.125 GBaud.
Table 54. Serial RapidIO transmitter DC specifications—2.5 GBaud, 3.125 GBaud (XVDD = 1.35V or 1.5V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

Output voltage VO –0.40 — 2.30 V 1

Long-run differential output voltage VDIFFPP 800 — 1600 mV p-p —
Short-run differential output voltage VDIFFPP 500 — 1000 mV p-p —
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential impedance
Note:
1. Voltage relative to COMMON of either signal comprising a differential pair

This table defines the transmitter DC specifications for Serial RapidIO operating at 5 GBaud.
Table 55. Serial RapidIO transmitter DC specifications—5 GBaud (XVDD = 1.35V or 1.5V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

Long-run differential output voltage VDIFF 800 — 1200 mV —

Short-run differential output voltage VDIFF 400 — 750 mV —
Long-run de-emphasized differential output voltage (ratio) VTX-DE-RATIO-3.5dB 3 3.5 4 dB —
Long-run de-emphasized differential output voltage (ratio) VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB —
Differential resistance RTD 80 100 120 Ω —
Note:
1. Voltage relative to COMMON of either signal comprising a differential pair.

2.23.5.4.2 DC Serial RapidIO receiver specifications

LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section.

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Electrical characteristics

Receiver input impedance results in a differential return loss better than 10 dB and a common mode return loss better than 6 dB
from 100 MHz to (0.8) × (Baud Frequency). This includes contributions from on-chip circuitry, the chip package, and any
off-chip components related to the receiver. AC coupling components are included in this requirement. The reference
impedance for return loss measurements is 100-Ω resistive for differential return loss and 25-Ω resistive for common mode.
This table defines the receiver DC specifications for Serial RapidIO operating at 2.5 and 3.125 GBaud.
Table 56. Serial RapidIO receiver DC specifications—2.5 GBaud, 3.125 GBaud (SVDD = 1.0V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

Differential input voltage VIN 200 — 1600 mV p-p 1

DC Differential receiver input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential
impedance
Note:
1. Measured at the receiver

This table defines the receiver DC specifications for Serial RapidIO operating at 5 GBaud.
Table 57. Serial RapidIO receiver DC specifications—5 GBaud (SVDD = 1.0V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

Long-run differential input voltage VDIFF — — 1200 mV 1

Short-run differential input voltage VDIFF 125 — 1200 mV 1
Differential resistance RRTD 80 — 120 Ω —
Note:
1. Measured at the receiver

2.23.5.5 AC requirements for Serial RapidIO

This section explains the AC requirements for the Serial RapidIO interface.

2.23.5.5.1 AC requirements for Serial RapidIO transmitter

This table defines the transmitter AC specifications for the Serial RapidIO operating at 2.5 and 3.125 GBaud. The AC timing
specifications do not include RefClk jitter.
Table 58. Serial RapidIO transmitter AC timing specifications—2.5 GBaud, 3.125 GBaud
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit

Deterministic jitter JD — — 0.17 UI p-p

Total jitter JT — — 0.35 UI p-p
Unit Interval: 2.5 GBaud UI 400 – 100ppm 400 400 + 100ppm ps
Unit Interval: 3.125 GBaud UI 320 – 100ppm 320 320 + 100ppm ps

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 Electrical characteristics

This table defines the transmitter AC specifications for the Serial RapidIO operating at 5 GBaud. The AC timing specifications
do not include RefClk jitter.
Table 59. Serial RapidIO transmitter AC timing specifications —5 GBaud
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit

Baud rate TBAUD 5.000 – 100ppm 5.000 5.000 + 100ppm Gb/s

Uncorrelated high probability jitter TUHPJ — — 0.155 UI p-p
Total jitter TJ — — 0.30 UI p-p

This table defines the receiver AC specifications for Serial RapidIO operating at 2.5 and 3.125 GBaud. The AC timing
specifications do not include RefClk jitter.
Table 60. Serial RapidIO receiver AC timing specifications —2.5 GBaud, 3.125 GBaud
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Deterministic jitter tolerance JD — — 0.37 UI p-p 1

Combined deterministic and random jitter JDR — — 0.55 UI p-p 1
tolerance
Total jitter tolerance2 JT — — 0.65 UI p-p 1
Bit error rate BER — — 10–12 — —
Unit Interval: 2.5 GBaud UI 400 – 100ppm 400 400 + 100 ppm ps —
Unit Interval: 3.125 GBaud UI 320 – 100ppm 320 320 + 100 ppm ps —
Notes:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 43. The sinusoidal jitter component
is included to ensure margin for low-frequency jitter, wander, noise, crosstalk, and other variable system effects.

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Electrical characteristics

This figure shows the single-frequency sinusoidal jitter limits for 2.5 GBaud and 3.125 GBaud rates.

8.5 UI p-p

Sinusoidal
Jitter 20dB/dec
Amplitude

0.10 UI p-p

baud/142000 Frequency baud/1667 20 MHz

Figure 43. Single-frequency sinusoidal jitter limits

This table defines the receiver AC specifications for Serial RapidIO operating at 5 GBaud. The AC timing specifications do not
include RefClk jitter.
Table 61. Serial RapidIO receiver AC timing specifications —5 GBaud
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Receiver baud rate RBAUD 5.000 – 100 ppm 5.000 5.000 + 100 ppm Gb/s —
Long-run Gaussian jitter RGJ — — 0.2 UI p-p —
Uncorrelated bounded high probability jitter RDJ — — 0.12 UI p-p —
Long-run correlated bounded high probability RCBHPJ — — 0.525 UI p-p —
jitter
Short-run correlated bounded high probability RCBHPJ — — 0.30 UI p-p —
jitter
Long-run bounded high probability jitter RBHPJ — — 0.75 UI p-p —
Short-run bounded high probability jitter RBHPJ — — 0.45 UI p-p —

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 Electrical characteristics

Table 61. Serial RapidIO receiver AC timing specifications (continued)—5 GBaud

For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Sinusoidal jitter, maximum RSJ-max — — 5.00 UI p-p —

Sinusoidal jitter, high frequency RSJ-hf — — 0.05 UI p-p —
Long-run total jitter (does not include RTj — — 0.95 UI p-p —
sinusoidal jitter)
Short-run total jitter (does not include RTj — — 0.60 UI p-p —
sinusoidal jitter)

This figure shows the single-frequency sinusoidal jitter limits for 5 GBaud rate.

5 UI p-p

Sinusoidal
Jitter 20dB/dec
Amplitude

0.05 UI p-p

35.2kHz Frequency 3MHz 20 MHz

Figure 44. Single-frequency sinusoidal jitter limits

2.23.6 XAUI interface

This section describes the DC and AC electrical specifications for the XAUI bus.

2.23.6.1 XAUI clocking requirements for SDn_REFn_CLK and

SDn_REFn_CLK_B
Only SerDes 2 (SD2_REF[1:2]_CLK and SD2_REF[1:2]_CLK_B) may be used for various SerDes2 XAUI configurations
based on the RCW Configuration field SRDS_PRTCL_S2.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”

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Electrical characteristics

2.23.6.2 XAUI DC electrical characteristics

This section discusses the XAUI DC electrical characteristics for the transmitter, and receiver.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”

2.23.6.2.1 XAUI transmitter DC electrical characteristics

This table defines the XAUI transmitter DC electrical characteristics.
Table 62. XAUI transmitter DC electrical characteristics (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Output voltage VO –0.40 — 2.30 V 1

Differential output voltage VDIFFPP 800 1000 1600 mV p-p —
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω 2
Note:
1. Absolute output voltage limit
2. Transmitter DC differential impedance.

2.23.6.2.2 XAUI receiver DC electrical characteristics

This table defines the XAUI receiver DC electrical characteristics.
Table 63. XAUI receiver DC timing specifications (SVDD = 1.0 V )
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Differential input voltage VIN 200 — 1600 mV p-p 1

DC Differential receiver input ZRX-DIFF-DC 80 100 120 Ω 2
impedance
Note:
1. Measured at the receiver.
2. Receiver DC differential impedance

2.23.6.3 XAUI AC timing specifications

This section discusses the XAUI AC timing specifications for the transmitter, and receiver.

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2.23.6.3.1 XAUI transmitter AC timing specifications

This table defines the XAUI transmitter AC timing specifications. RefClk jitter is not included.
Table 64. XAUI transmitter AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Deterministic jitter JD — — 0.17 UI p-p —

Total jitter JT — — 0.35 UI p-p —
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps —

2.23.6.3.2 XAUI receiver AC timing specifications

This table defines the receiver AC specifications for XAUI. RefClk jitter is not included.
Table 65. XAUI receiver AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Deterministic jitter tolerance JD — — 0.37 UI p-p 1

Combined deterministic and random JDR — — 0.55 UI p-p 1
jitter tolerance
Total jitter tolerance JT — — 0.65 UI p-p 1, 2
–12
Bit error rate BER — — 10 — —
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps —
Notes:
1. Measured at receiver.
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 43. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.

2.23.7 Aurora interface

This section describes the Aurora clocking requirements and its DC and AC electrical characteristics.

2.23.7.1 Aurora clocking requirements for SDn _REFn _CLK and SDn _REFn
_CLK_B
SerDes 1 and SerDes 2 (SD[1:2]_REF[1:2]_CLK and SD[1:2]_REF[1:2]_CLK_B) may be used for SerDes Aurora
configurations based on the RCW Configuration field SRDS_PRTCL_Sn.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”

2.23.7.2 Aurora DC electrical characteristics

This section describes the DC electrical characteristics for the Aurora interface.

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Electrical characteristics

2.23.7.2.1 Aurora transmitter DC electrical characteristics

This table defines the Aurora transmitter DC electrical characteristics.
Table 66. Aurora transmitter DC electrical characteristics (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit

Differential output voltage VDIFFPP 800 1000 1600 mV p-p

DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω

2.23.7.2.2 Aurora receiver DC electrical characteristics

This table defines the Aurora receiver DC electrical characteristics for the Aurora interface.
Table 67. Aurora receiver DC electrical characteristics (SVDD = 1.0 V )
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Differential input voltage VIN 200 — 1600 mV p-p 1

DC Differential receiver impedance ZRX-DIFF-DC 80 100 120 Ω 2
Note:
1. Measured at receiver.
2. DC Differential receiver impedance

2.23.7.3 Aurora AC timing specifications

This section describes the AC timing specifications for Aurora.

2.23.7.3.1 Aurora transmitter AC timing specifications

This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not included.
Table 68. Aurora transmitter AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit

Deterministic jitter JD — — 0.17 UI p-p

Total jitter JT — — 0.35 UI p-p
Unit interval: 2.5 GBaud UI 400 – 100 ppm 400 400 + 100 ppm ps
Unit interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps
Unit interval: 5.0 GBaud UI 200 – 100 ppm 200 200 + 100 ppm ps

2.23.7.3.2 Aurora receiver AC timing specifications

This table defines the Aurora receiver AC timing specifications. RefClk jitter is not included.

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Table 69. Aurora receiver AC timing specifications

For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Deterministic jitter tolerance JD — — 0.37 UI p-p 1

Combined deterministic and random JDR — — 0.55 UI p-p 1
jitter tolerance
Total jitter tolerance JT — — 0.65 UI p-p 1, 2
–12
Bit error rate BER — — 10 — —
Unit Interval: 2.5 GBaud UI 400 – 100 ppm 400 400 + 100 ppm ps —
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps —
Unit Interval: 5.0 GBaud UI 200 – 100 ppm 200 200 + 100 ppm ps —
Note:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 41. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

2.23.8 SGMII interface

Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in Figure 45, where
CTX is the external (on board) AC-coupled capacitor. Each SerDes transmitter differential pair features100-Ω output
impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XGND. The reference circuit
of the SerDes transmitter and receiver is shown in Figure 39.

2.23.8.1 SGMII clocking requirements for SDn_REFn_CLK and

SDn_REFn_CLK_B
When operating in SGMII mode, a SerDes reference clock is required on SD[1:2]_REF[1:2]_CLK and
SD[1:2]_REF[1:2]_CLK_B pins. SerDes 1–2 may be used for SerDes SGMII configurations based on the RCW Configuration
field SRDS_PRTCL_Sn.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”

2.23.8.2 SGMII DC electrical characteristics

This section discusses the electrical characteristics for the SGMII interface.

2.23.8.2.1 SGMII and SGMII 2.5x transmit DC specifications

This table describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are
measured at the transmitter outputs (SDn_TXn and SDn_TXn_B) as shown in Figure 46.

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Table 70. SGMII DC transmitter electrical characteristics (XVDD = 1.35 V or 1.5 V)

For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

Output high voltage VOH — — 1.5 x |VOD|-max mV 1

Output low voltage VOL |VOD|-min/2 — — mV 1
Output differential voltage2, 3 |VOD| 320 500.0 725.0 mV Amp Setting:
(XVDD-Typ at 1.35 V and 1.5 V) SRDSxLNmTECR0
[AMP_RED] = 6b0
293.8 459.0 665.6 Amp Setting:
SRDSxLNmTECR0
[AMP_RED] = 6b1
266.9 417.0 604.7 Amp Setting:
SRDSxLNmTECR0
[AMP_RED] = 6b11
240.6 376.0 545.2 Amp Setting:
SRDSxLNmTECR0
[AMP_RED] = 6b10
213.1 333.0 482.9 Amp Default
Setting:
SRDSxLNmTECR0
[AMP_RED] =
6b110
186.9 292.0 423.4 Amp Setting:
SRDSxLNmTECR0
[AMP_RED] =
6b111
160.0 250.0 362.5 Amp Setting:
SRDSxLNmTECR0
[AMP_RED] =
6b10000
Output impedance differential RO 80 100 120 Ω —
Notes:
1. This does not align to DC-coupled SGMII.
2. |VOD| = |VSD_TXn– VSD_TXn_B|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 × |VOD|.
3. The |VOD| value shown in the Typ column is based on the condition of XVDD-Typ = 1.35 V or 1.5 V, no common mode offset
variation. SerDes transmitter is terminated with 100-Ω differential load between SDn _TXn and SDn_TXn_B.

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This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.
Figure 45. 4-wire AC-coupled SGMII serial link connection example

SDn_TXn SDn_RXn
CTX

50 Ω
Transmitter 100 Ω Receiver

CTX
SDn_TXn_B SDn_RXn_B 50 Ω
SGMII
SerDes Interface
SDn_RXn CTX SDn_TXn

50 Ω
Receiver 100 Ω Transmitter

CTX
50 Ω SDn_RXn_B SDn_TXn_B

This figure shows the SGMII transmitter DC measurement circuit.

Figure 46. SGMII transmitter DC measurement circuit

SGMII
SerDes Interface

SDn_TXn

50 Ω

Transmitter 100 Ω VOD

50 Ω
SDn_TXn_B

This table defines the SGMII 2.5x transmitter DC electrical characteristics for 3.125 GBaud.
Table 71. SGMII 2.5x transmitter DC electrical characteristics (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Output differential voltage |VOD| 400 — 600 mV Amp Setting:

SRDSxLNmTECR0
[AMP_RED] = 6b0

Output impedance (differential) RO 80 100 120 Ω —

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2.23.8.2.2 SGMII and SGMII 2.5x DC receiver electrical characteristics

This table lists the SGMII DC receiver electrical characteristics. Source synchronous clocking is not supported. Clock is
recovered from the data.
Table 72. SGMII DC receiver electrical characteristics (SVDD = 1.0 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

DC input voltage range — N/A — 1

Input differential voltage — VRX_DIFFp-p 100 — 1200 mV 2, 4
— 175 —
Loss of signal threshold — VLOS 30 — 100 mV 3, 4
— 65 — 175
Receiver differential input impedance ZRX_DIFF 80 — 120 Ω —
Notes:
1. Input must be externally AC coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See
Section 2.23.4.3.2, “PCI Express DC physical layer receiver specifications,” and Section 2.23.4.4.2, “PCI Express AC physical
layer receiver specifications.,” for further explanation.
4. Default lost threshold sel = ‘001.’

This table defines the SGMII 2.5x receiver DC electrical characteristics for 3.125 GBaud.
Table 73. SGMII 2.5x receiver DC timing specifications (SVDD = 1.0 V )
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Input differential voltage VRX_DIFFp-p 200 — 1200 mV —

Loss of signal threshold VLOS 75 — 200 mV —
Receiver differential input impedance ZRX_DIFF 80 — 120 Ω —

2.23.8.3 SGMII AC timing specifications

This section discusses the AC timing specifications for the SGMII interface.

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2.23.8.3.1 SGMII and SGMII 2.5x transmit AC timing specifications

This table provides the SGMII and SGMII 2.5x transmit AC timing specifications. A source synchronous clock is not supported.
The AC timing specifications do not include RefClk jitter.
Table 74. SGMII transmit AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

Deterministic jitter JD — — 0.17 UI p-p —

Total jitter JT — — 0.35 UI p-p 2
Unit Interval: 1.25 GBaud (SGMII) UI 800 – 100 ppm 800 800 + 100 ppm ps 1
Unit Interval: 3.125 GBaud (2.5x SGMII) UI 320 – 100 ppm 320 320 + 100 ppm ps 1
AC coupling capacitor CTX 10 — 200 nF 3
Notes:
1. Each UI is 800 ps ± 100 ppm or 320 ps ± 100 ppm.
2. See Figure 43 for single frequency sinusoidal jitter measurements.
3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs.

2.23.8.3.2 SGMII AC measurement details

Transmitter and receiver AC characteristics are measured at the transmitter outputs (SDn_TXn and SDn_TXn_B) or at the
receiver inputs (SDn_RXn and SDn_RXn_B) respectively.

D+ package pin
C = CTX
Transmitter
silicon
+ package
C = CTX
D– package pin R = 50 Ω R = 50 Ω

Figure 47. SGMII AC test/measurement load

2.23.8.3.3 SGMII and SGMII 2.5x receiver AC timing specifications

This table provides the SGMII and SGMII 2.5x receiver AC timing specifications. The AC timing specifications do not include
RefClk jitter. Source synchronous clocking is not supported. Clock is recovered from the data.
Table 75. SGMII receive AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

Deterministic jitter tolerance JD — — 0.37 UI p-p 1

Combined deterministic and random jitter tolerance JDR — — 0.55 UI p-p 1
Total jitter tolerance JT — — 0.65 UI p-p 1, 2

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Table 75. SGMII receive AC timing specifications (continued)

For recommended operating conditions, see Table 4.

Parameter Symbol Min Typ Max Unit Notes

Bit error ratio BER — — 10-12 — —

Unit Interval: 1.25 GBaud (SGMII) UI 800 – 100 ppm 800 800 + 100 ppm ps 1
Unit Interval: 3.125 GBaud (2.5x SGMII]) UI 320 – 100 ppm 320 320 + 100 ppm ps 1
Notes:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 43. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 43.

2.23.9 XFI interface

This section describes the XFI clocking requirements and its DC and AC electrical characteristics.

2.23.9.1 XFI clocking requirements for SD2_REF2_CLK and SD2_REF2_CLK_B

Only SerDes 2 RefClk2 (SD2_REF2_CLK and SD2_REF2_CLK_B) may be used for SerDes XFI configurations based on the
RCW configuration field SRDS_PRTCL_S2.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”

2.23.9.2 XFI DC electrical characteristics

This section describes the DC electrical characteristics for XFI.

2.23.9.2.1 XFI transmitter DC electrical characteristics

This table defines the XFI transmitter DC electrical characteristics.
Table 76. XFI transmitter DC electrical characteristics (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Output differential voltage VTX-DIFF 360 — 770 mV —

De-emphasized differential output VTX-DE-RATIO- 0.6 1.1 1.6 dB —
voltage (ratio) 1.14dB

De-emphasized differential output VTX-DE-RATIO- 3 3.5 4 dB —

voltage (ratio) 3.5dB

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Table 76. XFI transmitter DC electrical characteristics (XVDD = 1.35 (continued)V or 1.5 (continued)V)
(continued)

Parameter Symbol Min Typical Max Unit Notes

De-emphasized differential output VTX-DE-RATIO- 4.1 4.6 5.1 dB —

voltage (ratio) 4.66dB

De-emphasized differential output VTX-DE-RATIO- 5.5 6.0 6.5 dB —

voltage (ratio) 6.0dB

De-emphasized differential output VTX-DE-RATIO- 9 9.5 10 dB —

voltage (ratio) 9.5dB

Differential resistance TRD 80 100 120 Ω —

2.23.9.2.2 XFI receiver DC electrical characteristics

This table defines the XFI receiver DC electrical characteristics.
Table 77. XFI receiver DC electrical characteristics (SVDD = 1.0 V )
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Input differential voltage VRX-DIFF 110 — 1050 mV 1

Differential resistance RRD 80 100 120 Ω —
Note:
1. Measured at receiver

2.23.9.3 XFI AC timing specifications

This section describes the AC timing specifications for XFI.

2.23.9.3.1 XFI transmitter AC timing specifications

This table defines the XFI transmitter AC timing specifications. RefClk jitter is not included.
Table 78. XFI transmitter AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit

Transmitter baud rate TBAUD 10.3125 – 100 ppm 10.3125 10.3125 + 100 ppm Gb/s
Unit Interval UI — 96.96 — ps
Deterministic jitter DJ — — 0.15 UI p-p
Total jitter TJ — — 0.30 UI p-p

2.23.9.3.2 XFI receiver AC timing specifications

This table defines the XFI receiver AC timing specifications. RefClk jitter is not included.

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Table 79. XFI receiver AC timing specifications

For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Receiver baud rate RBAUD 10.3125 – 100 10.3125 10.3125 + 100 Gb/s —
ppm ppm
Unit Interval UI — 96.96 — ps —
Total non-EQJ jitter TNON-EQJ — — 0.45 UI p-p 1
Total jitter tolerance TJ — — 0.65 UI p-p 1, 2
Note:
1. The total jitter (TJ) consists of Random Jitter (RJ), Duty Cycle Distortion (DCD), Periodic Jitter (PJ), and Inter symbol
Interference (ISI). Non-EQJ jitter can include duty cycle distortion (DCD), random jitter (RJ), and periodic jitter (PJ). Non-EQJ
jitter is uncorrelated to the primary data stream with exception of the DCD and so cannot be equalized by the receiver under
test. It can exhibit a wide spectrum. Non – EQJ = TJ – ISI = RJ + DCD + PJ
2. The XFI channel has a loss budget of 9.6 dB @5.5GHz. The channel loss including connector @ 5.5GHz is 6dB. The channel
crosstalk and reflection margin is 3.6dB. Manual tuning of TX Equalization and amplitude are required for performance
optimization.

This figure shows the sinusoidal jitter tolerance of XFI receiver.

Figure 48. XFI host receiver input sinusoidal jitter tolerance
Sinusoidal jitter tolerance (UIP-p)

, ƒ in MHz

–20 dB/Dec

0.17
0.05

0.04 4 8 27.2 40

Frequency (MHz)

2.23.10 10GBase-KR interface

This section describes the 10GBase-KR clocking requirements and its DC and AC electrical characteristics.

2.23.10.1 10GBase-KR clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B
Only SerDes 2 RefClk2 (SD2_REF2_CLK and SD2_REF2_CLK_B) may be used for SerDes 10GBase-KR configurations
based on the RCW configuration field SRDS_PRTCL_S2.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”

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2.23.10.2 10GBase-KR DC electrical characteristics

This section describes the DC electrical characteristics for 10GBase-KR.

2.23.10.2.1 10GBase-KR transmitter DC electrical characteristics

This table defines the 10GBase-KR transmitter DC electrical characteristics.
Table 80. 10GBase-KR transmitter DC electrical characteristics (XVDD=1.35V or 1.5V)
Table 81. For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Output differential voltage VTX-DIFF 800 - 1200 mV —

De-emphasized differential output VTX-DE-RATIO- 0.6 1.1 1.6 dB —
voltage (ratio) 1.14dB

VTX-DE-RATIO- 3 3.5 4 dB —
3.5dB

VTX-DE-RATIO- 4.1 4.6 5.1 dB —

4.66dB

VTX-DE-RATIO- 5.5 6.0 6.5 dB —

6.0dB

VTX-DE-RATIO- 9 9.5 10 dB —
9.5dB

Differential resistance TRD 80 100 120 Ω —

2.23.10.2.2 10GBase-KR receiver DC electrical characteristics

This table defines the 10GBase-KR receiver DC electrical characteristics.
Table 82. 10GBase-KR receiver DC electrical characteristics (XVDD=1.35V or 1.5V)
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Input differential voltage VRX-DIFF - - 1200 mV —

Differential resistance RRD 80 - 120 Ω —

2.23.10.3 10GBase-KR AC timing specifications

This section describes the AC timing specifications for 10GBase-KR.

2.23.10.3.1 10GBase-KR transmitter AC timing specifications

This table defines the 10GBase-KR transmitter AC timing specifications RefClk jitter is not included.

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Table 83. 10GBase-KR transmitter AC timing specifications

For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit

Transmitter baud rate TBAUD 10.3125 - 100 ppm 10.3125 10.3125 + 100 ppm GBd
Deterministic jitter DJ - - 0.155 UI p-p
Total jitter TJ - - 0.30 UI p-p

2.23.10.3.2 10GBase-KR receiver AC timing specifications

This table defines the 10GBase-KR receiver AC timing specifications. RefClk jitter is not included.
Table 84. 10GBase-KR receiver AC timing specifications
For recommended operating conditions, see Table 4.

Parameter Symbol Min Typical Max Unit Notes

Receiver baud rate RBAUD 10.3125 - 100 ppm 10.3125 10.3125 + 100 ppm Gbd —
Random jitter RJ - - 0.130 UI p-p 1
Sinusoidal jitter, maximum SJ-max - - 0.115 UI p-p 1
Duty cycle distortion DCD - - 0.035 UI p-p 1
Total jitter TJ - - 1.0 UI p-p 1,2
1. The AC specifications do not include Refclk jitter.
2. The total applied Jitter Tj = ISI + Rj + DCD + Sj-max where ISI is jitter due to frequency dependent loss.
3. TX Equalization and amplitude tuning is through software for performance optimization, as in NXP provided SDKs.

2.23.11 CPRI interface

This section describes the CPRI clocking requirements and its DC and AC electrical characteristics.

2.23.11.1 CPRI clocking requirements for SD1_REFn_CLK and SD1_REFn_CLK_B

Only SerDes 1 (SD1_REF[1:2]_CLK and SD1_REF[1:2]_CLK_B) may be used for SerDes CPRI configurations based on the
RCW Configuration field SRDS_PRTCL_S1.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”

2.23.11.2 CPRI LV
This section describes the CPRI LV XAUI based interface, designed to work at 1.2288, 2.4576 and 3.072 GB/s.

2.23.11.2.1 Transmitter specifications

This table defines the DC specifications for the differential output at all transmitters (TXs). The parameters are specified at the
component pins.
Table 85. Transmitter DC specifications (XVDD = 1.35 V or 1.5 V)

Characteristic Symbol Min Nom Max Unit

Output voltage VO –0.40 — 2.30 Volts

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Table 85. Transmitter DC specifications (XVDD = 1.35 V or 1.5 V)

Differential output voltage VDIFFPP 800 — 1600 mV p-p

Differential resistance T_Rd 80 100 120 Ω

The following table defines the AC specifications for the differential output at all transmitters (TXs). The parameters are
specified at the component pins.
Table 86. Transmitter AC specifications

Characteristic Symbol Min Nom Max Unit

Deterministic jitter JD — — 0.17 UI p-p

Total jitter JT — — 0.35 UI p-p

Unit interval: 1.2288 UI 1/1228.8-100ppm 1/1228.8 1/1228.8+100ppm us

GBaud

Unit interval: 2.4576 UI 1/2457.6-100ppm 1/2457.6 1/2457.6+100ppm us

GBaud

Unit interval: 3.072 UI 1/3072.0-100ppm 1/3072.0 1/3072.0+100ppm us

GBaud

Note:
The AC specifications do not include Refclk jitter.

2.23.11.2.2 Receiver specifications

This table defines the DC specifications for the differential input at all receivers (RXs). The parameters are specified at the
component pins.
Table 87. Receiver DC specifications (SVDD = 1.0 V)

Characteristic Symbol Min Nom Max Unit

Differential input voltage VIN 200 — 1600 mV p-p

Differential resistance R_Rdin 80 — 120 Ω

This table defines the AC specifications for the differential input at all receivers (RXs). The parameters are specified at the
component pins.
Table 88. Receiver AC specifications

Characteristic Symbol Min Nom Max Unit Condition

Deterministic jitter tolerance JD — — 0.37 UI p-p Measured at

receiver

Combined deterministic and JDR — — 0.55 UI p-p Measured at

random jitter tolerance receiver

Total jitter tolerance JT — — 0.65 UI p-p Measured at

receiver

Bit error ratio BER — — 10-12 — —

Unit interval: 1.2288 GBaud UI 1/1228.8-100ppm 1/1228.8 1/1228.8+100ppm ps —

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Table 88. Receiver AC specifications (continued)

Characteristic Symbol Min Nom Max Unit Condition

Unit interval: 2.4576 GBaud UI 1/2457.6-100ppm 1/2457.6 1/2457.6+100ppm ps —

Unit interval: 3.072 GBaud UI 1/3072.0-100ppm 1/3072.0 1/3072.0+100ppm ps —

Note:
1. Total random jitter is composed of deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter’s
amplitude and frequency is defined in agreement with XAUI specification IEEE 802.3-2005 [1], clause 47.
2. The AC specifications do not include Refclk jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude and
frequency in the unshaded region of Figure 41.

2.23.11.3 CPRI LV-II/LV-III

This section describes the CPRI LV-II CEI-6G-LR based (1.2288, 2.4576, 3.072, 4.9152 and 6.144 Gb/s) and CPRI LV-III IEEE
802.3 [22], clause 72.7 based (9.8304 Gb/s)

2.23.11.3.1 CPRI LV-II and LV-III transmitter specifications

This table provides the CPRI-LV-II and LV-III transmitter DC specifications.
Table 89. CPRI LV-II and LV-III transmitter DC specifications (XVDD = 1.35 V or 1.5 V)

Parameter Symbols Min Nom Max Units Condition

Output differential T_Vdiff 800 — 1200 mV Amp Setting: SRDS1LNmTECR0

voltage (into floating [AMP_RED] = 6b0
load Rload=100 Ω)

De-emphasized T_VTX-DE-RATIO-1.14dB -0.6 -1.1 -1.6 dB Ratio of full swing:

differential output SRDS1LNmTECR0 [RATIO_PST1Q]
voltage (ratio) = 5b00011

De-emphasized T_VTX-DE-RATIO-3.5dB -3 -3.5 -4 dB Ratio of full swing:

differential output SRDS1LNmTECR0 [RATIO_PST1Q]
voltage (ratio) = 5b01000
De-emphasized T_VTX-DE-RATIO-4.66dB -4.1 -4.6 -5.1 dB Ratio of full swing:
differential output SRDS1LNmTECR0 [RATIO_PST1Q]
voltage (ratio) = 5b01010

De-emphasized T_VTX-DE-RATIO-6.0dB -5.5 -6.0 -6.5 dB Ratio of full swing:

differential output SRDS1LNmTECR0 [RATIO_PST1Q]
voltage (ratio) = 5b01100

De-emphasized T_VTX-DE-RATIO-9.5dB -9 -9.5 -10 dB Ratio of full swing:

differential output SRDS1LNmTECR0 [RATIO_PST1Q]
voltage (ratio) = 5b10000

Differential resistance T_Rd 80 100 120 Ω

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This table provides the CPRI-LV-II/LV-III transmitter AC specifications.

Table 90. CPRI LV-II/LV-III transmitter AC specifications

Parameter Symbols Min Nom Max Units

Uncorrelated high-probability T_UHPJ/T_RJ — — 0.15 UI p-p

jitter/random jitter

Deterministic jitter T_DJ — — 0.15 UI p-p

Total jitter T_TJ — — 0.30 UI p-p

Unit interval: 1.2288 GBaud UI 1/1228.8-100ppm 1/1228.8 1/1228.8+100ppm us

Unit interval: 2.4576 GBaud UI 1/2457.6-100ppm 1/2457.6 1/2457.6+100ppm us

Unit interval: 3.072 GBaud UI 1/3072.0-100ppm 1/3072.0 1/3072.0+100ppm us

Unit interval: 4.9152 GBaud UI 1/4915.2-100ppm 1/4915.2.0 1/4915.2+100ppm us

Unit interval: 9.8304 GBaud UI 1/9830.4-100ppm 1/9.8304 1/9830.4+100ppm us

Note:
1. The Refclk jitter measured using Golden PLL is to be less than 0.05UI. The Golden PLL should have at maximum a bandwidth
of baud rate over 1667, with a maximum of 20dB/dec rolloff, until at least baud rate over 16.67, with no peaking around the
corner frequency.

This table provides the CPRI-LV-II/LV-III transmitter AC specifications for 6.144 GBaud.
Table 91. CPRI LV-II/LV-III transmitter AC specifications (6.144 GBaud)

Parameter Symbols Min Nom Max Units

Uncorrelated high-probability T_UHPJ/T_RJ — — 0.2 UI p-p

jitter/random jitter

Deterministic jitter T_DJ — — 0.17 UI p-p

Total jitter T_TJ — — 0.37 UI p-p

Unit interval: 6.144 GBaud UI 1/6144.0-100ppm 1/61440 1/6144.0+100ppm us

Note:
1. The Refclk jitter measured using Golden PLL is to be less than 0.05UI. The Golden PLL should have at maximum a bandwidth
of baud rate over 1667, with a maximum of 20dB/dec rolloff, until at least baud rate over 16.67, with no peaking around the
corner frequency.

2.23.11.3.2 CPRI LV-II and LV-III receiver specifications

This table provides the CPRI LV-II and the CPRI LV-III receiver DC timing specifications.
Table 92. CPRI-LV-II receiver DC specifications (SVDD = 1.0 V)

Parameter Symbols Min Nom Max Units

Input differential voltage R_Vdiff N/A — 1200 mV

Differential Resistance R_Rdin 80 — 120 Ω

Note:
1. It is assumed that for the R_diff Min spec, the eye can be closed at the receiver after passing the signal through
a CEI/CPRI Level II LR-compliant channel.

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Electrical characteristics

Table 93. CPRI LV-II receiver AC specifications

Parameter Symbols Min Nom Max Units

Gaussian jitter R_GJ — — 0.275 UI p-p

Uncorrelated bounded high-probability jitter R_UBHPJ — — 0.150 UI p-p

Correlated bounded high-probability jitter R_CBHPJ — — 0.525 UI p-p

Bounded high-probability jitter R_BHPJ — — 0.675 UI p-p

Sinusoidal jitter, maximum R_SJ-max — — 5.000 UI p-p

Sinusoidal jitter, high frequency R_SJ-hf — — 0.050 UI p-p

Total jitter does not include sinusoidal jitter R_Tj — — 0.950 UI p-p

Unit Interval: 1.2288 GBaud UI 1/1228.8-100ppm 1/1228.8 1/1228.8+100ppm us

Unit Interval: 2.4576 GBaud UI 1/2457.6-100ppm 1/2457.6 1/2457.6+100ppm us

Unit Interval: 3.072 GBaud UI 1/3072.0-100ppm 1/3072.0 1/3072.0+100ppm us

Unit Interval: 4.9152 GBaud UI 1/4915.2-100ppm 1/4915.2.0 1/4915.2+100ppm us

Note:
1. The AC specifications do not include Refclk jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude
and frequency in the unshaded region of Figure 41.
2. The ISI jitter (R_CBHPJ) and amplitude have to be correlated for example by a PCB trace.
3. The intended application is as a point-to-point interface of approximately 100cm and up to two connectors. The maximum
allowed total loss (channel + interconnect+ other loss) is 20.6dB @ 6.144 Gb/s.

This table provides the CPRI LV-II receiver AC specifications for 6.144 GBaud.
Table 94. CPRI LV-II receiver AC specifications (6.144 GBaud)

Parameter Symbols Min Nom Max Units

Gaussian jitter R_GJ — — 0.2 UI p-p

Uncorrelated bounded high-probability jitter R_UBHPJ — — 0.05 UI p-p

Correlated bounded high-probability jitter R_CBHPJ — — 0.35 UI p-p

Bounded high-probability jitter R_BHPJ — — 0.40 UI p-p

Sinusoidal jitter, maximum R_SJ-max — — 5.000 UI p-p

Sinusoidal jitter, high frequency R_SJ-hf — — 0.125 UI p-p

Total jitter does not include sinusoidal jitter R_Tj — — 0.6 UI p-p

Unit Interval: 6.144 GBaud UI 1/6144.0-100ppm 1/61440 1/6144.0+100ppm us

Note:
1. The AC specifications do not include Refclk jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude
and frequency in the unshaded region of Figure 41.
2. The ISI jitter (R_CBHPJ) and amplitude have to be correlated for example by a PCB trace.
3. The intended application is as a point-to-point interface of approximately 60cm and up to two connectors. The maximum
allowed total loss (channel + interconnect+ other loss) is 12.2dB @ 6.144 Gb/s.
4. R_Tj total jitter is measured at receiver inputs without post-equalizer.

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140 NXP Semiconductors
 Hardware design considerations

This table provides the LV-III RX parameters guided by 10GBase-KR electrical interface (IEEE 802.3 [22], clause 72.7.2).
Table 95. CPRI LV-III receiver AC specifications

Symbols Parameter Min Nom Max Units

Gaussian Jitter R_GJ — — 0.130 UI p-p

Sinusoidal Jitter, maximum R_SJ-max — — 0.115 UI p-p

DCD - Duty Cycle Distortion R_dcd — — 0.035 UI p-p

Total jitter R_Tj — — See Note 1. UI p-p

Unit Interval: 9.8304 GBaud UI 1/9.8304-100ppm 1/9.8304 1/9.8304+100ppm us

Note:
1. The R_Tj is per Interference Tolerance Test IEEE Std 802.3ap-2007 specified in Annex 69A.
2. The AC specifications do not include Refclk jitter.
3. The maximum channel insertion loss is achieved by manual tuning TX equalization.

3 Hardware design considerations

3.1 System clocking
This section describes the PLL configuration of the chip.

3.1.1 PLL characteristics

Characteristics of the chip’s PLLs include the following:
• There are a total of 11 PLLs on the chip.
• There are two selectable e6500 core cluster PLLs which generate a core clock from the externally supplied SYSCLK
input. The e6500 core complex can select from CGA1 PLL or CGA2 PLL. The frequency ratio between e6500 core
cluster PLLs and SYSCLK is selected using the configuration bits as described in the applicable chip reference manual.
• There are two selectable SC3900 core clusters PLLs which generate a core clock from the externally supplied
SYSCLK input. The SC3900 core clusters can select from CGB1 PLL or CGB2 PLL. The frequency ratio between
SC3900 core clusters PLLs and SYSCLK is selected using the configuration bits as described in the applicable chip
reference manual.
• The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in the
applicable chip reference manual.
• There are two DDR PLLs which generate the two DDR clocks (one per each), from the externally supplied DDR(1,
2)_CLK input per PLL (asynchronous mode). The frequency ratio is selected using the Memory Controller Complex
PLL multiplier/ratio configuration bits as described in the applicable chip reference manual.
• Each of the two SerDes blocks has 2 PLLs which generate a core clock from their respective externally supplied
SDn_REFn_CLK/SDn_REFn_CLK_B inputs. The frequency ratio is selected using the SerDes PLL ratio
configuration bits as described in Section 3.1.5, “SerDes PLL ratio.”

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Hardware design considerations

3.1.2 Clock ranges

This table provides the clocking specifications for the e6500 core, SC3900 core, Maple ETVPE, Maple/CPRI, Maple ULB,
platform, and DDR memory.
Table 96. Clocking specifications

Frequency Notes
Characteristic Unit
Min Max —

e6500 core frequency 250 1600 MHz 1,2,3

SC3900 core frequency 250 1200 MHz 1,2,3
Maple ETVPE frequency 250 1000 MHz —
Maple/CPRI frequency 250 600 MHz —
Maple ULB frequency 250 800 MHz —
Platform clock frequency 400 667 MHz 1, 5
DDR memory bus clock frequency 1067 1866 MHz 6
FM frequency 450 667 MHz 4
Notes:
1. Caution: The platform clock to SYSCLK ratio and any core to SYSCLK ratio settings must be chosen
such that the resulting cores frequency, and platform clock frequency do not exceed their respective
maximum or minimum operating frequencies.
2.The core can run at core complex PLL/1, PLL/2 or PLL/4 with a minimum PLL frequency of 1000.0 MHz.
This results in a minimum allowable core frequency of 250 MHz for PLL/4.
3. The e6500 and SC3900 clusters frequency must be at least the (Platform frequency)/2 and higher.
4. FM minimum frequency is 450 MHz when only SGMII at 1 Gbps ports are required (for example, no
usage of SGMII2.5). Otherwise, FM minimum frequency is 625 MHz.
5. 5G SRIO port operation is not supported for platform frequencies below 528 MHz.
6. DDR1 PLL and DDR2 PLL must have a reference clock of 133.333 MHz to achieve a frequency of
1866.667 MHz.

NOTE
Hardware accelerators cannot run at core/3 and core/4 speeds if the core speed is configured
to less than 1 GHz. When the core speed is configured to less than 1 GHz, core/4 speed is
not feasible for DFS. Cluster PLL maximum output frequency is 1800 MHz if SYSCLK is
lower than 100 MHz.

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 Hardware design considerations

3.1.3 Platform to SYSCLK PLL ratio

The allowed platform clock to SYSCLK ratio is from 3:1 to 12:1.

3.1.4 PPC core cluster to SYSCLK PLL ratio

The allowed e6500 core cluster or SC3900 cluster PLL clock to SYSCLK ratio are from 6:1 to 27:1.

3.1.5 SerDes PLL ratio

The allowed platform clock to SYSCLK ratio are from 3:1 to 12:1.
The clock ratio between each of the three SerDes PLLs and their respective externally supplied
SDn_REFn_CLK/SDn_REFn_CLK_B inputs is determined by a set of RCW Configuration fields—SRDS_PRTCL_Sn,
SRDS_PLL_REF_CLK_SEL_Sn — as shown in this table.
Table 97. Valid SerDes RCW encoding and reference clocks

Legal setting for

Valid reference Legal setting for
SerDes protocol (given lane) SRDS_PLL_REF Notes
clock frequency SRDS_PRTCL_Sn
_CLK_SEL_Sn

High-speed serial and debug interfaces

PCI Express 2.5 Gbps 100 MHz Any PCIe 0b0: 100 MHz 1
(doesn’t negotiate upwards)
125 MHz 0b1: 125 MHz 1
PCI Express 5 Gbps 100 MHz Any PCIe 0b0: 100 MHz 1
(can negotiate up to 5 Gbps)
125 MHz 0b1: 125 MHz 1
Serial RapidIO 2.5 Gbps 100 MHz sRIO @ 2.5/5 Gbps 0b0: 100 MHz —
125 MHz 0b1: 125 MHz —
Serial RapidIO 3.125 Gbps 125 MHz sRIO @ 3.125 Gbps 0b0: 125 MHz —
156.25 MHz 0b1: 156.25 MHz —
Serial RapidIO 5 Gbps 100 MHz sRIO @ 2.5/5 Gbps 0b0: 100 MHz —
125 MHz 0b1: 125 MHz —
CPRI 1.2288 Gbps 122.88 MHz CPRI @ 1.2288 Gbps 0b0: 122.88 MHz —
CPRI 2.4576 Gbps 122.88 MHz CPRI @ 2.4576 Gbps 0b0: 122.88 MHz —
CPRI 3.072 Gbps 122.88 MHz CPRI @ 3.072 Gbps 0b0: 122.88 MHz —
CPRI 4.9152 Gbps 122.88 MHz CPRI @ 4.9152 Gbps 0b0: 122.88 MHz —
CPRI 6.144 Gbps 122.88 MHz CPRI @ 6.144 Gbps 0b0: 122.88 MHz —
CPRI 9.8304 Gbps 122.88 MHz CPRI @ 9.8304 Gbps 0b0: 122.88 MHz —
Debug (2.5 Gbps) 100 MHz Aurora @ 2.5/5 Gbps 0b0: 100 MHz —
125 MHz 0b1: 125 MHz —
Debug (3.125 Gbps) 125 MHz Aurora @ 3.125 Gbps 0b0: 125 MHz —
156.25 MHz 0b1: 156.25 MHz —

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Hardware design considerations

Table 97. Valid SerDes RCW encoding and reference clocks (continued)

Legal setting for

Valid reference Legal setting for
SerDes protocol (given lane) SRDS_PLL_REF Notes
clock frequency SRDS_PRTCL_Sn
_CLK_SEL_Sn

Debug (5 Gbps) 100 MHz Aurora @ 2.5/5 Gbps 0b0: 100 MHz —
125 MHz 0b1: 125 MHz —

Networking interfaces

SGMII (1.25 Gbps) 100 MHz SGMII @ 1.25 Gbps 0b0: 100 MHz —
125 MHz 0b1: 125 MHz —
2.5x SGMII (3.125 Gbps) 125 MHz SGMII @ 3.125 Gbps 0b0: 125 MHz —
156.25 MHz 0b1: 156.25 MHz —
XAUI (3.125 Gbps) 125 MHz XAUI @ 3.125 Gbps 0b0: 125 MHz —
156.25 MHz 0b1: 156.25 MHz —
XFI (10.3125 Gbps) 156.25 Mhz XFI @ 10.3125 Gbps 0b0: 156.25 MHz —
Note:
1. A spread-spectrum reference clock is permitted for PCI Express. However, if any other high-speed interfaces such
as sRIO, or debug is used concurrently on the same SerDes bank, spread-spectrum clocking is not permitted.

3.1.5.1 Dn_DDRCLK and DDRn memory frequency options

This table shows the expected frequency options for Dn_DDRCLK and DDRn memory frequencies.

Table 98. Dn_DDRCLK and DDRn data rate options

Dn_DDRCLK (MHz)
DDRn data rate:
66.667 100.000 125.000 133.333
Dn_DDRCLK
DDRn data rate (MT/s)1

8:1 1066.667
9:1
10:1 1333.333
11:1
12:1 1600.000
13:1 1300.000
14:1 1866.667
15:1
16:1 1066.667 1600.000
17:1

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 Hardware design considerations

Table 98. Dn_DDRCLK and DDRn data rate options (continued)

18:1 1200.000 1800.000
19:1
20:1 1333.333
Notes:
1. DDR data rate values are shown rounded to the nearest whole number
(decimal place accuracy removed)

3.2 Power supply design

3.2.1 Voltage ID (VID) controllable supply

To guarantee performance and power specifications, a specific method of selecting the optimum voltage-level must be
implemented when the chip is used. As part of the chip's boot process, software must read the VID efuse values stored in the
Fuse Status register (DCFG_CCSR_FUSESR) and then configure the external voltage regulator based on this information. This
method requires an adjustable point of load voltage regulator (POL).

NOTE
During the power-on reset process, the fuse values are read and stored in the
DCFG_CCSR_FUSESR. It is expected that the chip's boot code reads the
DCFG_CCSR_FUSESR register very early in the boot sequence and updates the regulator
accordingly.
The default voltage regulator setting that is safe for the system to boot is the recommended operating VDD at initial start-up of
1.05 V. It is highly recommended to select a regulator with a Vout range of at least 0.9 V to 1.1 V, with a resolution of 12.5 mV
or better, when implementing a VID solution.
For additional information on VID, see the chip reference manual.

3.2.1.1 Options for system design

There are several widely-accepted options available to the system designer for obtaining the benefits of a VID solution. The
most common option is to use the VID solution to drive a system's controllable voltage-regulators through a sideband interface
such as a simple parallel bus or PMBus interface. PMBus is similar to I2C but with extensions to improve robustness and
address shortcomings of I2C; the PMBus specification can be found at www.pmbus.org. The simple parallel bus is supported
by the chip through GPIO pins and the PMBus interface is supported by an I2C interface. Other VID solutions may be to access
an FPGA/ASIC or separate power management chip through the IFC, SPI, or other chip-specific interface, where the other
device then manages the voltage regulator. The method chosen for implementing the chip-specific voltage in the system is
decided by the user.

3.2.1.1.1 Example 1: Regulators supporting parallel bus configuration

In this example, a user builds a VID solution using controllable regulators with a parallel bus. In this implementation, the user
chooses to utilize any subset of the available GPIO pins on the chip except those noted below.

NOTE
GPIO pins that are muxed on an interface used by the application for loading RCW
information are not available for VID use.
It is recommended that all GPIO pins used for VID are located in the same 32-bit GPIO IP
block so that all bits can be accessed with a single read or write.

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Hardware design considerations

The general procedure for setting the core voltage regulator to the desired operating voltage is as follows:
1. The GPIO pins are released to high-impedance at POR. Because GPIO pins default to being inputs, they do not begin
automatically driving after POR, and only work as outputs under software control.
2. The board is responsible for a default voltage regulator setting that is "safe" for the system to boot. To achieve this, the
user puts pull-up and/or pull-down resistors on the GPIO pins as needed for that specific system. For the case where
the regulator's interface operates at a different voltage than OVDD, the chip's GPIO module can be operated in an open
drain configuration.
3. There is no direct connection between the Fuse Status Register (FUSESR) and the chip's pins. As part of the chip's
boot process, software must read the efuse values stored in the FUSESR and then configure the voltage regulator based
on this information. The software determines the proper value for the parallel interface and writes it to the GPIO block
data (GPDAT) register. It then changes the GPIO direction (GPDIR) register from input to output to drive the new
value on the device pins, thus overriding the board configuration default value. Note that some regulators may require
a series of writes so that the voltage is slowly stepped from its old to its new value.
4. When the voltage has stabilized, software adjusts the operating frequencies as desired.
Upon completion of configuration, some regulators may have a write-protect pin to prevent undesired data changes after
configuration is complete. A single GPIO pin on the chip could be allocated for this task if desired.

3.2.1.1.2 Example 2: Regulators supporting PMBus configuration

In this example, a user builds a VID solution using controllable regulators with a PMBus interface. For the case where the
regulator's interface operates at a different voltage than DVDD, the chip's I2C module can be operated in an open-drain
configuration.
In this implementation, the user chooses to utilize any I2C interface available on the chip. These regulators have a means for
setting a safe, default, operating value either through strapping pins or through a default, non-volatile store.

NOTE
If I2C1 controller is selected, it is important that its calling address is different than the 7-bit
value of 0x50h used by the pre-boot loader (PBL) for RCW and pre-boot initialization.
The general procedure for setting the core voltage regulator to the desired operating voltage is as follows:
1. The board is responsible for configuring a safe default value for the controllable regulator either through dedicated
pins or its non-volatile store.
2. As part of the chip's boot process, software must read the efuse values stored in the FUSESR register and then
configure the voltage regulator based on this information. The software decides on a new configuration and sends this
value across the I2C interface connected to the regulator's PMBus interface. Note that some regulators may require a
series of writes so that the voltage is slowly stepped from its old to its new value.
3. When the voltage has stabilized, software adjusts the operating frequencies as desired.
Upon completion of configuration, some regulators may have a write-protect pin to prevent undesired data changes after
configuration is complete. A single GPIO pin on the chip could be allocated for this task, if desired.

3.2.1.1.3 Example 3: Regulators supporting FPGA/ASIC or separate power

management device configuration
In this example, a user builds a VID solution using controllable regulators that are managed by a FPGA/ASIC or a separate
power-management device. In this implementation, the user chooses to utilize the IFC, eSPI or any other available chip interface
to connect to the power-management device.
The general procedure for setting the core voltage regulator to the desired operating voltage is as follows:
1. The board is responsible for configuring a safe default value for the controllable regulator either through dedicated
pins or its non-volatile store.

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146 NXP Semiconductors
 Hardware design considerations

2. As part of the chip's boot process, software must read the efuse values stored in the FUSESR and then configure the
voltage regulator based on this information. The software decides on a new configuration and sends this value across
the IFC, eSPI, or any other interface that is used to connect to the FPGA/ASIC or separate power-management device
that manages the regulator. Note that some regulators may require a series of writes so that the voltage is slowly
stepped from its old to its new value.
3. When the voltage has stabilized, software adjusts the operating frequencies as desired.
Upon completion of configuration, some regulators may have a write-protect pin to prevent undesired data changes after
configuration is complete. A single GPIO pin on the chip could be allocated for this task, if desired.

3.2.2 Core supply voltage filtering

The VDD supply is normally derived from a high current capacity or switching power supply which can regulate its output
voltage very accurately despite changes in current demand from the chip within the regulator’s relatively low bandwidth.
Several bulk decoupling capacitors must be distributed around the PCB to supply transient current demand above the bandwidth
of the voltage regulator.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance. However, customers
should work directly with their power regulator vendor for best values and types of bulk capacitors.
As a guideline for customers and their power regulator vendors, NXP recommends that these bulk capacitors be chosen to
maintain the power supply voltage within ± 30 mV.
These bulk decoupling capacitors ideally supply a stable voltage for current transients into the megahertz range. Above that,
see Section 3.3, “Decoupling recommendations for further decoupling recommendations.

3.2.3 PLL power supply filtering

Each of the PLLs described in Section 3.1, “System clocking,” is provided with power through independent power supply pins
(AVDD_PLAT, AVDD_CGAn, AVDD_CGBn and AVDD_DDRn and AVDD_SRDSn_PLLn). AVDD_PLAT, AVDD_CGAn,
AVDD_CGBn and AVDD_DDRn voltages must be derived directly from a 1.8 V voltage source through a low frequency filter
scheme. AVDD_SRDSn_PLLn voltages must be derived directly from the XVDD voltage source through a low frequency filter
scheme. The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as
illustrated in Figure 49, one for each of the AVDD pins. By providing independent filters to each PLL, the opportunity to cause
noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLL’s resonant frequency range
from a 500 kHz to 10 MHz range.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the
footprint, without the inductance of vias.
This figure shows the PLL power supply filter circuit.
Where:
R = 5 Ω ± 5%
C1 = 10 μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH
C2 = 1.0 μF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH

NOTE
A higher capacitance value for C2 may be used to improve the filter as long as the other C2
parameters do not change (0402 body, X5R, ESL ≤ 0.5 nH).
Voltage for AVDD is defined at the input of the PLL supply filter and not the pin of AVDD.

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NXP Semiconductors 147
Hardware design considerations

R
1.8 V source AVDD_PLAT, AVDD_CGAn, AVDD_CGBn, AVDD_DDRn
C1 C2

Low-ESL surface-mount capacitors

GND
Figure 49. PLL power supply filter circuit

The AVDD_SRDSn_PLLn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal
clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 50. For maximum
effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn_PLLn balls to ensure it filters out as much
noise as possible. The ground connection should be near the AVDD_SRDSn_PLLn balls. The 0.003-µF capacitors closest to the
balls, followed by a 4.7-µF and 47-µF capacitor, and finally the 0.33 Ω resistor to the board supply plane. The capacitors are
connected from AVDD_SRDSn_PLLn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant
frequency. All traces should be kept short, wide, and direct.

0.33 Ω
XVDD AVDD_SRDSn_PLLn
47 µF 4.7 µF 0.003 µF

AGND_SRDSn_PLLn

Figure 50. SerDes PLL power supply filter circuit

Note the following:

• AVDD_SRDSn_PLLn should be a filtered version of XVDD.
• Signals on the SerDes interface are fed from the XVDD power plane.
• Voltage for AVDD_SRDSn_PLLn is defined at the PLL supply filter and not the pin of AVDD_SRDSn_PLLn.
• A 47-µF 0805 XR5 or XR7, 4.7-µF, and 0.003-µF or smaller capacitor are recommended. The size and material type
are important. A 0.33-Ω ± 1% resistor is recommended.
• There needs to be dedicated analog ground, AGND_SRDSn_PLLn for each AVDD_SRDSn_PLLn pin up to the
physical local of the filters themselves.

3.2.4 SVDD power supply filtering

SVDD should be supplied by a dedicated linear regulator. Systems may design to allow flexibility to address system noise
dependencies.
NOTE
For initial system bring-up, the linear regulator option is highly recommended.
An example solution for SVDD filtering, where SVDD is sourced from linear regulator, is illustrated in Figure 51. The
component values in this example filter are system dependent and are still under characterization, component values may need
adjustment based on the system or environment noise.
Where:
C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
F1 to F4 are 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its maximum DC resistance is 0.05,
or 0.0125 for the parallel resultant, and each has about a 120+-25% of AC impedance at 100 MHz, which will be

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148 NXP Semiconductors
 Hardware design considerations

quarter valued for the parallel resultant, with individual maximum DC current carrying capacity of 2Amps. Bulk and
decoupling capacitors are added, as needed, per power supply design.

Bulk and F1
SVDD decoupling Liner regulator output
capacitors C1 C2 C3 F2

F3
GND
F4

Figure 51. SVDD power supply filter circuit

3.2.5 XVDD power supply filtering

XVDD must be supplied by a linear regulator or sourced by a filtered GnVDD. Systems may design in both options to allow
flexibility to address system noise dependencies.

NOTE
For initial system bring-up, the linear regulator option is highly recommended.
An example solution for XVDD filtering, where XVDD is sourced from a linear regulator, is illustrated in Figure 52. The
component values in this example filter are system dependent and are still under characterization, component values may need
adjustment based on the system or environment noise.
Where:
C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
F1 to F4 are 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its maximum DC resistance is 0.05,
or 0.0125 for the parallel resultant, and each has about a 120+-25% of AC impedance at 100 MHz, which will be
quarter valued for the parallel resultant, with individual maximum DC current carrying capacity of 2Amps.Bulk and
decoupling capacitors are added, as needed, per power supply design.

Bulk and F1
XVDD decoupling Linear regulator output
capacitors C1 C2 C3 F2

F3
GND
F4

Figure 52. XVDD power supply filter circuit

3.2.6 Remote power-supply sense recommendations

There is a practice of connecting the remote sense signal of an on-board power supply to one of power supply pins of an IC
device. The advantage of this connection is the ability to compensate for the slow components of the IR droop caused by the
resistive supply current path from the on-board power supply to the C5 pins layer on-package (for flip-chip packages).
However, not every C5 pin is selected to be the remote sense pin. It may be a reserved pin that requires a connection to be a
supply or ground pin, and therefore must remain connected to the corresponding supply. Alternatively, the C5 pin may be

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NXP Semiconductors 149
Hardware design considerations

supplying the critical power-consuming area of the IC die whose usage as non-supply pin may cause shortage in the supply
current during high-current peaks.
It is recommended that these pins be used as the board supply remote sense output, because they do not degrade the power and
ground supply quality:
• VDD/VSS sense pair: K9/J9 or AE12/AD11
Connect to either sense pair and leave the other pair unconnected.

3.3 Decoupling recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the chip system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place decoupling capacitors at each VDD, OVDD, QVDD, DVDD and GnVDD pin of the
device. These decoupling capacitors should receive their power from separate VDD, OVDD, QVDD, DVDD and GnVDD and
GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the
device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to
minimize lead inductance, preferably 0402 or 0603 sizes.
As presented in Section 3.2.2, “Core supply voltage filtering,” it is recommended that there be several bulk storage capacitors
distributed around the PCB, feeding the VDD and other planes (For example, OVDD, QVDD, DVDD and GnVDD), to enable quick
recharging of the smaller chip capacitors.

3.4 SerDes block power supply decoupling

recommendations
The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and
reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.

NOTE
Only SMT capacitors should be used to minimize inductance. Connections from all
capacitors to power and ground should be done with multiple vias to further reduce
inductance.
1. The board should have at least 1 × 0.1-µF SMT ceramic chip capacitor placed as close as possible to each supply ball
of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and
ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the
device as close to the supply and ground connections as possible.
2. Between the device and any SerDes voltage regulator there should be a lower bulk capacitor, for example, a 10-µF,
low ESR SMT tantalum or ceramic chip capacitor and a higher bulk capacitor, for example, a 100-µF–300-µF low
ESR SMT tantalum or ceramic chip capacitor.

3.5 Connection recommendations for unused pins

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active
low inputs and open-drain I/O should be tied to VDD, QVDD, DVDD, OVDD and GnVDD as required. All unused active high
inputs should be connected to GND. All NC (no connect) signals must remain unconnected. Power and ground connections
must be made to all external VDD, QVDD, DVDD, OVDD, GnVDDand GND pins of the chip.
Unused LVCMOS pins recommendations:
• For unused input only and bidirectional pins, connect with a pull-down resistor of 10 kΩ.

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150 NXP Semiconductors
 Hardware design considerations

• Unused output only pins can be left floating.

Unused DDR pins recommendations:
• When the following conditions are met, clocks, address, control, mask, cmd, data, strobes, MAPAR_OUT pin, and
MAPAR_ERR_B pins can be left floating:
— the output buffer is tristated,
— the receiver is in sleep mode,
— and termination is off.
• When the conditions above are not met, connect the clocks, address, control, mask, cmd, data, positive strobes,
MAPAR_OUT pin, and MAPAR_ERR_B pins to GND via a 1 kΩ resistor. Negative strobes should be pulled-up to
GnVDD via a 1 kΩ resistor.
• If the whole DDR module is not used, connect GVDD and MVREF to GND and connect DDR_AVDD to OVDD.
• If the DDR2 interface is not used, D2_DDRCLK can be connected to GND via a 10 kΩ resistor.
• If the DDR1 interface is not used, D1_DDRCLK still needs to toggle.

3.5.1 Legacy JTAG configuration signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 54.
Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion gives unpredictable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST_B signal is optional in the IEEE Std 1149.1
specification, but it is provided on all processors built on Power Architecture technology. The device requires TRST_B to be
asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation.
While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST_B
during the power-on reset flow. Simply tying TRST_B to PORESET_B is not practical because the JTAG interface is also used
for accessing the common on-chip processor (COP), which implements the debug interface to the chip.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging
software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert
PORESET_B or TRST_B in order to fully control the processor. If the target system has independent reset sources, such as
voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged
into these signals with logic.
The arrangement shown in Figure 54 allows the COP port to independently assert PORESET_B or TRST_B, while ensuring
that the target can drive PORESET_B as well.
The COP interface has a standard header, shown in Figure 53, for connection to the target system, and is based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a
connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and
other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.
There is no standardized way to number the COP header; so emulator vendors have issued many different pin numbering
schemes. Some COP headers are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom.
Still others number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the numbering scheme, the signal
placement recommended in Figure 53 is common to all known emulators.

3.5.1.1 Termination of unused signals

If the JTAG interface and COP header are not used, NXP recommends the following connections:
• TRST_B should be tied to PORESET_B through a 0 kΩ isolation resistor so that it is asserted when the system reset
signal (PORESET_B) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. NXP

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 151
Hardware design considerations

recommends that the COP header be designed into the system as shown in Figure 54. If this is not possible, the
isolation resistor will allow future access to TRST_B in case a JTAG interface may need to be wired onto the system
in future debug situations.
• No pull-up/pull-down is required for TDI, TMS or TDO.

COP_TDO 1 2 NC

COP_TDI 3 4 COP_TRST_B

NC 5 6 COP_VDD_SENSE

COP_TCK 7 8 COP_CHKSTP_IN_B

COP_TMS 9 10 NC

COP_SRESET_B 11 12 NC

KEY
COP_HRESET_B 13 No pin

COP_CHKSTP_OUT_B 15 16 GND

Figure 53. Legacy COP Connector Physical Pinout

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152 NXP Semiconductors
 Hardware design considerations

OVDD

HRESET_B 7 10 kΩ
From target 1 kΩ HRESET_B6
board sources
(if any) PORESET_B 10 kΩ
PORESET_B1

COP_HRESET
13
COP_SRESET 10 kΩ
11
B A 10 kΩ

5 10 kΩ

10 kΩ
COP_TRST TRST_B1
1 2 4
COP_VDD_SENSE2 10 Ω
3 4 6
5 NC
5 6

COP_CHKSTP_OUT_B
COP Header

7 8 15 CKSTP_OUT_B
9 10
14 3 10 kΩ
11 12

KEY
13 No pin COP_CHKSTP_IN_B
8 System logic
15 16 COP_TMS
9 TMS
COP Connector COP_TDO
1 TDO
Physical Pinout
COP_TDI
3 TDI
COP_TCK
7 TCK
2 NC
10 NC

12 4

16

Notes:
1. The COP port and target board should be able to independently assert POREST_B and TRST_B to the processor
in order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved
signal integrity.
5.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to avoid accidentally asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed
to position B.
6. Asserting HRESET_B causes a hard reset on the chip.
7. This gate is an open-drain gate.
Figure 54. Legacy JTAG interface connection

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NXP Semiconductors 153
Hardware design considerations

3.5.2 Aurora configuration signals

Correct operation of the Aurora interface requires configuration of a group of system control pins as demonstrated in Figure 56.
Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion gives unpredictable results.
NXP recommends the Aurora 34 or 70 pin duplex connectors be designed into the system as shown in the following figures.
If the Aurora interface is not used, NXP recommends the legacy COP header be designed into the system as described in
Section 3.5.1.1, “Termination of unused signals.”

TX0_P 1 2 VIO (VSense)

TX0_N 3 4 TCK
GND 5 6 TMS
TX1_P 7 8 TDI
TX1_N 9 10 TDO
GND 11 12 TRST
RX0_P 13 14 Vendor I/O 0
RX0_N 15 16 Vendor I/O 1
GND 17 18 Vendor I/O 2
RX1_P 19 20 Vendor I/O 3
RX1_N 21 22 RESET
GND 23 24 GND
TX2_P 25 26 CLK_P
TX2_N 27 28 CLK_N
GND 29 30 GND
TX3_P 31 32 Vendor I/O 4
TX3_N 33 34 Vendor I/O 5

Figure 55. Aurora 34 pin connector duplex pinout

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154 NXP Semiconductors
 Hardware design considerations

TX0_P 1 2 VIO (VSense)

TX0_N 3 4 TCK
GND 5 6 TMS
TX1_P 7 8 TDI
TX1_N 9 10 TDO
GND 11 12 TRST
RX0_P 13 14 Vendor I/O 0
RX0_N 15 16 Vendor I/O 1
GND 17 18 Vendor I/O 2
RX1_P 19 20 Vendor I/O 3
RX1_N 21 22 RESET
GND 23 24 GND
TX2_P 25 26 CLK+
TX2_N 27 28 CLK-
GND 29 30 GND
TX3_P 31 32 Vendor I/O 4
TX3_N 33 34 Vendor I/O 5
GND 35 36 GND
RX2_P 37 38 N/C
RX2_N 39 40 N/C
GND 41 42 GND
RX3_P 43 44 N/C
RX3_N 45 46 N/C
GND 47 48 GND
TX4_P 49 50 N/C
TX4_N 51 52 N/C
GND 53 54 GND
TX5_P 55 56 N/C
TX5_N 57 58 N/C
GND 59 60 GND
TX6_P 61 62 N/C
TX6_N 63 64 N/C
GND 65 66 GND
TX7_P 67 68 N/C
TX7_N 69 70 N/C

Figure 56. Aurora 70 pin connector duplex pinout

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NXP Semiconductors 155
Hardware design considerations

1 kΩ
OVDD

HRESET_B 5 10 kΩ
From Target HRESET _B4
Board Sources
(if any) PORESET_B 10 kΩ PORESET_B1

RESET
22
10 kΩ
20,25 NC
27,31 B 10 kΩ
32,33 A
1 2 3 10 kΩ
3 4
5 6
10 kΩ
7 8 AURORA_TRST_B TRST_B1
9 10 12
11 12
VIO VSense2 1 kΩ
13 14 2
15 16
AURORA_TMS
17 18 6 TMS
Aurora Header

19 20 AURORA_TDO
21 22 10 TDO
23 24 AURORA_TDI
25 26
8 TDI
AURORA_TCK
27 28
4 TCK
29 30
34 Vendor I/O 5 (Aurora_HRESET_B)
31 32
18 Vendor I/O 2 (Aurora_Event_Out_B) 10 kΩ
33 34 EVT[4]
Vendor I/O 1 (Aurora_Event_In_B)
16 EVT[1]
Duplex 34 Connector Vendor I/O 0 (Aurora_HALT_B)
14 CLK_P 100 nF EVT[0]
Physical Pinout 26 SD4_REF_CLKn
28 CLK_N 100 nF
SD4_REF_CLKn_B
TX0_P
1 SD4_TX5_P
TX0_N
3 SD4_TX5_N
TX1_P
7 SD4_TX4_P
TX1_N
9 SD4_TX4_N
RX0_P 0.01 uF
13 SD4_RX5_P
RX0_N 0.01 uF
15 SD4_RX5_N
RX1_P 0.01 uF
19 SD4_RX4_P
RX1_N 0.01 uF
21 SD4_RX4_N
6
5,11,17 6
23,24 REF_CLK1_B REF_CLK1
29,30
REF_CLK_B REF_CLK
Notes:
1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor
in order to fully control the processor as shown here.
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
3. This switch is included as a precaution for BSDL testing. Close the switch to position A during BSDL testing to avoid
accidentally asserting the TRST_B line. If BSDL testing is not being performed, close this switch to position B.
4. Asserting HRESET_B causes a hard reset on the device.
5. This is an open-drain output gate.
6. REF_CLK/REF_CLK_B and REF_CLK1/REF_CLK1_B are buffered clocks from the same common source.
Figure 57. Aurora 34 pin connector duplex interface connection

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156 NXP Semiconductors
 Hardware design considerations

OVDD

HRESET_B 5 10 kΩ
From target HRESET_B4
1 kΩ
board sources
(if any) PORESET_B 10 kΩ PORESET_B1

1 2
22 RESET
3 4
5 6 20,25,27,31, 10 kΩ
7 8
32,33,37,38,
39,40,43,44, B 10 kΩ
9 10
45,46,49,50,
A
11 12
N/C
51,52,55,56, 3 10 kΩ
13 14
57,58,61,62,
15 16
63,64,67,68, 10 kΩ
17 18 69,70
TRST TRST_B1
19 20
21 22
12
23 24 VIO VSense2 1 kΩ
2
25 26 AURORA_TMS
27 28 6 TMS
AURORA_TDO
Aurora Header

29 30
10 TDO
31 32
AURORA_TDI
33 34 8 TDI
35 36 AURORA_TCK
37 38 4 TCK
39 40 Vendor I/O 5 (Aurora HRESET)
34
41 42
43 44
26 CLK+ 10 kΩ SD2_REF1_CLK
28 CLK- SD2_REF1_CLK_B
45 46
47 48 18 Vendor I/O 2 (Aurora Event Out)
EVT[4]
49 50 Vendor I/O 1 (Aurora Event In)
16 EVT[1]
51 52 Vendor I/O 0 (Aurora HALT)
53 54 14 EVT[0]
TX0_P
55 56 1 SD2_TX3
57 58 TX0_N
3 SD2_TX3_B
59 60 TX1_P
62
7 SD2_TX2
61
TX1_N
63 64 9 SD2_TX2_B
65 66 RX0_P 0.01 µF
13 SD2_RX3
67 68 RX0_N 0.01 µF
69
15 SD2_RX3_B
70
RX1_P 0.01 µF
19 SD2_RX2
RX1_N
21 SD2_RX2_B
Duplex 70 0.01 µF 6
Connector 5,11,17,23,24,
29,30,35,36,41, 6
Physical Pinout REF_CLK1_B REF_CLK1
42,47,48,53,54,
REF_CLK_B REF_CLK
59,60,65,66
Notes:
1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor
in order to fully control the processor as shown here.
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
3.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to avoid accidentally asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed
to position B.
4. Asserting HRESET_B causes a hard reset on the chip.
5. This gate is an open-drain gate.
6. REF_CLK/REF_CLK_B and REF_CLK1/REF_CLK1_B are buffered clocks from the same common source.
Figure 58. Aurora 70 pin connector duplex interface connection

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NXP Semiconductors 157
Hardware design considerations

3.5.3 Guidelines for high-speed interface termination

3.5.3.1 SerDes interface entirely unused

If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section.
Note that both SVDD and XVDD must remain powered.
The following pins must be left unconnected:
• SDn_TX[7:0]
• SDn_TX[7:0]_B
The following pins must be connected to SGND:
• SDn_RX[7:0]
• SDn_RX[7:0]_B
• SDn_REF1_CLK, SDn_REF2_CLK
• SDn_REF1_CLK_B, SDn_REF2_CLK_B
The following pins must be left unconnected:
• SDn_IMP_CAL_RX
• SDn_IMP_CAL_TX
In the RCW configuration fields SRDS_PLL_PD_S1, and SRDS_PLL_PD_S2, all bits must be set to power down both PLLs
of the corresponding SerDes module. A module is disabled when both its PLLs are turned off.

3.5.3.2 SerDes interface partly unused

If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as
described in this section.
The following unused pins must be left unconnected:
• SDn_TX[n]
• SDn_TX[n]_B
The following unused pins must be connected to SGND:
• SDn_RX[n]
• SDn_RX[n]_B
• SDn_REF[1:2]_CLK, SDn_REF[1:2]_CLK_B (Clock pair that is not used)
In the RCW configuration field SRDS_PLL_PD_Sn, the respective bits for each unused module must be set to power down the
PLLs of the corresponding SerDes module.
After POR, if an entire SerDes module is unused, it can be powered down by clearing the SDEN fields of its corresponding
PLL1 and PLL2 reset control registers (SRDSn_PLLmRSQCTL).
Unused lanes can be powered down by clearing the RRST and TRST fields and setting the RX_PD and TX_PD fields in the
corresponding lane’s general control register (SRDSn_LxGCR0).

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158 NXP Semiconductors
 Hardware design considerations

3.6 Thermal
This table shows the thermal characteristics for the chip.
Table 99. Package thermal characteristics 6

Rating Board Symbol Value Unit Notes

Junction to ambient, natural convection Single-layer board (1s) RΘJA 16 °C/W 1, 2

Junction to ambient, natural convection Four-layer board (2s2p) RΘJA 11 °C/W 1, 3
Junction to ambient (at 200 ft./min.) Single-layer board (1s) RΘJMA 10 °C/W 1, 2
Junction to ambient (at 200 ft./min.) Four-layer board (2s2p) RΘJMA 7 °C/W 1, 2
Junction to board — RΘJB 3.3 °C/W 3
Junction-to-case top — RΘJCtop 0.37 °C/W 4
Junction-to-lid top — RΘJClid 0.18 °C/W 5
Note:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51–3 and JESD51–6 with the board (JESD51–9) horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51–8. Board temperature is measured on
the top surface of the board near the package.
4. Junction-to-case-top at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Junction-to-lid-top thermal resistance is determined using the MIL-STD 883 Method 1012.1. However, instead of the cold
plate, the lid-top temperature is used here for the reference case temperature. Reported value does not include the thermal
resistance of the interface layer between the package and the cold plate.
6. See Section 3.7, “Thermal management information,” for additional details.

3.7 Thermal management information

This section provides thermal management information for the flip-chip, plastic-ball, grid array (FC-PBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow,
and thermal interface material. The recommended attachment method to the heat sink is illustrated in Figure 59. The heat sink

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NXP Semiconductors 159
Hardware design considerations

should be attached to the printed-circuit board with the spring force centered over the die. This spring force should not exceed
31 lbs (137 Newton).

FC-PBGA package (with lid)

Heat sink

Heat sink clip

Adhesive or
thermal interface material Die lid
Die
Lid adhesive

Printed-circuit board

Figure 59. Package exploded, cross-sectional view—FC-PBGA (with lid)

The system board designer can choose between several types of heat sinks to place on the device. There are several
commercially-available thermal interfaces to choose from in the industry. Ultimately, the final selection of an appropriate heat
sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method,
assembly, and cost.

3.7.1 Internal package conduction resistance

For the package, the intrinsic internal conduction thermal resistance paths are as follows:
• The die junction-to-case thermal resistance
• The die junction-to-lid-top thermal resistance
• The die junction-to-board thermal resistance
This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
External Resistance Radiation Convection

Heat sink Junction to case top

Junction to lid top Thermal interface material

Internal resistance Die/Package

Die junction
Package/Solder balls
Printed-circuit board

External resistance Radiation Convection

(Note the internal versus external package resistance)

Figure 60. Package with heat sink mounted to a printed-circuit board

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160 NXP Semiconductors
 Package information

The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the
silicon and through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case
thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.

3.7.2 Thermal interface materials

A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The
performance of thermal interface materials improves with increasing contact pressure; this performance characteristic chart is
generally provided by the thermal interface vendor. The recommended method of mounting heat sinks on the package is by
means of a spring clip attachment to the printed-circuit board (see Figure 59).
The system board designer can choose among several types of commercially-available thermal interface materials.

3.8 Temperature diode

The chip has temperature diodes that can be used to monitor its temperature using external temperature monitoring devices
(such as Analog Devices, ADT7461A™). These on-chip temperature diodes have pins that may be connected to test points, or
left as a no connect when they are not used.
The following are specifications of the chip temperature diodes:
• Operating range: 10–230μA
• Non-ideality factor over entire temperature range: n = 1.006 ± 0.003

4 Package information
4.1 Package parameters for the FC-PBGA
The package parameters are as provided in the following list. The package type is 33 mm × 33 mm, 1020 flip-chip, plastic-ball,
grid array (FC-PBGA). The device part is designed to be RoHS and Pb-free compliant.
Package outline 33 mm × 33 mm
Interconnects 1020
Ball Pitch 1.0 mm
Ball Diameter (typical) 0.60 mm
Solder Balls 96.5% Sn, 3% Ag, 0.5% Cu
Module height (typical) 2.63 mm to 2.93 mm (maximum)

B4860 QorIQ Qonverge Data Sheet, Rev. 4

NXP Semiconductors 161
Package information

4.2 Mechanical dimensions of the B4860 FC-PBGA

This figure shows the mechanical dimensions and bottom surface nomenclature of the chip.

Figure 61. Mechanical dimensions of the FC-PBGA with full lid

Notes:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. All dimensions are symmetric across the package center lines unless dimensioned otherwise.
4. Maximum solder ball diameter measured parallel to datum A.
5. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
6. Parallelism measurement excludes any effect of mark on top surface of package.

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162 NXP Semiconductors
 Security fuse processor

5 Security fuse processor

This chip implements the trust architecture, supporting capabilities such as secure boot. Use of the trust architecture features is
dependent on programming fuses in the Security Fuse Processor (SFP). The details of the trust architecture and SFP can be
found in the chip reference manual.
To program SFP fuses, the user is required to supply 1.8 V to the POVDD pin per Section 2.2, “Power sequencing.” POVDD
should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles.
All other times POVDD should be connected to GND. The sequencing requirements for raising and lowering POVDD are shown
in Figure 8. To ensure device reliability, fuse programming must be performed within the recommended fuse programming
temperature range per Table 4.

NOTE
Users not implementing the QorIQ platform’s trust architecture features should connect
POVDD to GND.

6 Ordering information
Contact your local NXP sales office or regional marketing team for order information.

6.1 Part numbering nomenclature

This table provides the NXP QorIQ Qonverge platform part numbering nomenclature.
Table 100. Part numbering nomenclature

B 4 8 6 X N S1 E 7 Q U M A

Number
Temperature
of Power Number of Deriv- Qual Encryp- Package CPU DDR DSP Die
Platform range and
core DSP cores ative status tion type speed speed speed revision
power levels
threads

B= 4= 8=8 6 = 6 DSP X= P= S= E= 7= Q= U= M= A=
Base- Macro core cores Generic Prototype Standard SEC FC-PBGA 1600 MHz 1866 MHz 1200 MHz Rev 1.0
band threads temperature present C4/C5 B=
PB = N= (0 to 105) N= Pb-free Rev 2.0
Proto Indust tier and standard No SEC C=
Base- power Rev 2.1
band X= D=
Extended Rev 2.2
temperature
(–40 to 105)
and standard
power

Note:
1. One XVDD = 1.35 V option is available for part ‘X’ extended temperature range.

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NXP Semiconductors 163
Revision history

6.1.1 Part marking

Parts are marked as in the example shown in this figure.

B486XXXX7XXMX
ATWLYYWW

MMMMM CCCCC
YWWLAZ

FC-PBGA
Notes:
B486XXXX7XXMX represents the orderable part number.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
CCCCC is the assembly country code.
ATWLYYWW is the test traceability code.

Figure 62. Part marking for FC-PBGA chip

7 Revision history
This table summarizes changes to this document.
Table 101. Revision history

Revision
Date Description
Number

4 08/2017 • Added Section 2.17.1, “JTAG DC Electrical Characteristics

3 09/2016 • Updated Figure 11
• In Table 15, updated I/O leakage current min value as -50 and max value as 50
• In Table 16, removed rows and note for output high and low current
• Updated the document template for NXP standards
• Replaced all Freescale instances with NXP
• Updated the data Sheet status to “Technical Data”
• Removed footer security for Preliminary and NDA release
2 11/’2015 • Updated Section 6, “Ordering information”
1 09/2015 • Updated Section 2.23.10, “10GBase-KR interface”
0 08/2015 • First release after qualification of silicon

B4860 QorIQ Qonverge Data Sheet, Rev. 4

164 NXP Semiconductors
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Document Number: B4860

Rev. 4
08/2017