International Conference on Inventive Systems and Control (ICISC 2019)

IEEE Xplore Part Number: CFP19J06-ART; ISBN: 978-1-5386-3950-4

FPGA Based Implementation of Symmetrical

Switching in SVPWM for Three Level NPC Converter
Raghuram L Naik, Member IEEE Kavita B. Hunasikatti,Member IEEE
Basaveshwar Engineering College (Autonomous) Angadi Institute of Technology and Management
Bagalkot, Karnataka India Belagavi, Karnataka India

Abstract—This paper presents the FPGA based [7]. This approach does not ensure capacitor voltage balance
implementation of symmetrical switching strategy in SVPWM for under all conditions particularly at low modulation indices.
three level NPC converter. A simplified switching strategy is Researchers have developed various simplified SVM
proposed by exploiting the redundant states of switching vectors approach to overcome problems of three level NPC
available in three level space vector resulting into symmetrical converter [9-13]. The switching signals are generated for
switching sequence. This switching strategy leads to generate NPC converter using half wave, quarter wave and three
switching sequence for all regions of every sector with each phase symmetry [10]. To implement this method, fictitious
switch has to be turned “ON’ once in time period resulting into vector has to be created during the computation of time
lower device stress and reduced switching loss. The proposed intervals for all six sectors, which increases the complexity
switching strategy is developed using FPGA based Xilinx block
and overloads the processor. The switching sequences are
sets and tested on hardware test bench consists of Induction
arranged in symmetrical pattern to reduce the complexity
motor integrated to the three level Neutral Point Clamped (NPC)
converter controlled by FPGA based wavect controller. It is
and computational time of processor [13]. In this approach,
observed from the results, that the complexity of SVPWM for each switch is turned ‘ON’ more than once in each time
three level inverter is reduced to that of two level inverter and period at unequal duty cycles. This will increase stress on
address the problem of narrow pulse width at the midpoint of individual switch, which results in switching losses from
NPC converter medium to higher switching frequencies. In view of these
limitations there is need to develop a simplified procedure
Keywords— SVPWM, FPGA, Xilinx, Wavect, NPC, THD for the implementation of SVPWM for three level NPC
converter. In this paper, focus is on implementation of
I. INTRODUCTION symmetrical switching in SVPWM of three level NPC
converter using FPGA based Xilinx tools. The details of
In recent days FPGA processors are playing a vital role in implementation are given in the following sections.
the field of power electronics and electric drives
applications. This is due to FPGA offers higher II. SYMMETRICAL SWITCHING IN SVPWM (SSSVPWM)
programming flexibility, improved performance in terms of Three level NPC converter has 27 allowable switching states
sequential execution of algorithms, reliable operation due to
for space vector pulse width modulation. These switching
direct communication with hardware and cost effective [3-
4]. Traditional processors such as microcontroller, Digital states are further sorted into four groups based on their
Signal Processor (DSP) and Complex Programmable Logic magnitude as 6-large vectors, 6-medium vectors, 12-small
Devices (CPLD) are used to control power electronic vectors and 3-zero voltage vectors [7, 10]. The zero and
converter employed in electric drives. However, these small vectors having redundant states are exploited to
processors suffer from limitations such as limited number of obtained the switching signals symmetric in nature and each
executions, higher sampling frequency and higher hold up switch has to be turned ON once in each time period Ts. To
time [8]. In view of this FPGA is suitable processor to achieve this, switching sequence is proposed for each region
control power electronic converters employed in electric of all six sectors and the switching direction shown in
drives. In industries nearly 60% of energy consumed by the Fig.1.0
electrical drives such as pumps, fans, air compressors
conveyors etc and nearly 80% motors employed in
industries are of induction motors[1-2]. Multilevel inverters
are the preferred for high rated electric drives, as they
provide reduced device rating, reduced current distortion,
low switching losses and lower electromagnetic interference
[2]. Among various topologies of multilevel inverters,
Neutral Point Clamped (NPC) is popular one for controlling
of electric drives. Space Vector PWM is promising
modulation technique to control NPC as it increases
modulation range by 15 % and DC bus utilization 15.47 %
as compared to sinusoidal PWM [5]. In general the SVPWM
algorithm suffers with problem of narrow pulse and
capacitor imbalance that exist between the capacitors. A
Fig.1.0: Proposed switching sequences for three level space vector
switching algorithm is presented in [6] to address narrow
pulse and capacitor voltage imbalance by switching nearest III. FPGA IMPLEMENTATION OF SSSVPWM
four vectors, but this method results in higher pulsation and
harmonics in the output voltages. Further, the redundancy of This section focuses on the implementation of SSSVPWM
SVPWM algorithm is utilized to avoid narrow pulse and for three level NPC converter using Xilinx block sets of
voltage imbalance problems of three level NPC converter FPGA
FPGA based control of power electronics drive research laboratory is
established under TEQIP-III funding from NPIU New Delhi.

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 International Conference on Inventive Systems and Control (ICISC 2019)
IEEE Xplore Part Number: CFP19J06-ART; ISBN: 978-1-5386-3950-4

A. Identification of Nearest Three Vectors (NTVs)

Block-2
The Space Vector Modulation is based on conversion from
three phases abc into stationary frame of reference αβ is
Block-1
given in Eq(1). The magnitude and phase of reference
voltage vector is obtained by using Eq(2) & Eq(3). The
Xilinx implementation for computation of magnitude and
angle is shown in Fig.2.0 and results are given in Fig.3.0
and Fig.4.0.
V an 
V   2 1  1/ 2  1 / 2  V  Fig. 5.0: Computation of phase and identification of sectors
V    (1)
  bn 
  3 0 3 / 2  3 / 2 The angle delta is computed by dividing 600 and truncating
 V cn
where, Van, Vbn and Vcn are phase voltages the output of the divisor as shown 0in Fig.6.0. The sector is
obtained, dividing the phase by 60 and ceiling the divisor
V ref  V 2  V 2  (2) as shown in Fig.7.0.
1  V   (3)
  tan  
 V 

Fig.6.0: Phase angle of the Vref

Fig 2.0: Calculation of Magnitude and Phase of Reference Voltage

Vector

Fig.7.0: Results indicating the sector numbers

To identify the NTVs, it is necessary to determine small

triangle in which the tip of the reference vector VREF is
located. NTVs are obtained by dividing each sector into four
regions as shown in Fig.8.0. Further, boundaries of each
region are obtained by evaluating signs of linear equations
Fig 3.0: Magnitude of Reference Voltage as given (4)-(5). The linear equations define boundaries of
small triangles in x and y coordinates.

Fig.8.0: Identification of regions in a sector

Fig 4.0: Phase angle of Reference Voltage Vector

k 1  y  V dc 2 (4)
The cordiac bock is used to obtain the phase angle of the
Vref. It is observed from the result that, the variation of the k 2  y  V dc 2  3 ( x  V dc 6 ) (5)
angle is between -1800 to +1800. In order to shift the
negative portion of the phase, the logic is developed and is k 3 y  3 ( x  V pn 3) (6)
implemented as shown the block-1 of Fig .5.0.
If phase ≥ 0 To identify the appropriate region, the logic is given in the
Table-1.0 and Xilinx model is developed as shown in
Angle=phase
Fig.9.0.
Else
Angle=phase+3600
End

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 International Conference on Inventive Systems and Control (ICISC 2019)
IEEE Xplore Part Number: CFP19J06-ART; ISBN: 978-1-5386-3950-4

Table-1: Identification of regions in a Sector

Sl.
Conditions Location
No
1 k1 ≤ 0 & k2 ≤ 0 & k3 ≤ 0 Region-1
2 k1 ≤ 0 & k2 ≥0 & k3 ≤ 0 Region-2
3 If angle<30 o, k2 ≥0 & k3 ≥0 & k1 ≤0 Region-3
o
4 If angle>30 , k1 ≥0 & k2 ≥0 & k3≥0 Region-4

Fig .11: Computation of Duty cycle for Region-1

Fig.9.0: Xilinx model for identification of Regions

B. Computation of Duty Cycle

The reference vector Vr is approximated by time averaging Fig.12: Results indicating the Duty cycles of region-1
to nearest three vectors Vx, Vy and Vz on αβ plane[11] for
the region-1 as given in Eq(7-9) C. Switching Strategy

i. Switching Strategy of SSSVPWM

The switching direction of all the four regions in each sector
are shown in Fig.1.0, in this section the switching sequence are
arranged symmetrically for all the 4- regions of sector-1 as
shown in Fig.13 and Table-2. The similar strategy is followed
to obtain the switching sequence for remaining sectors.
Fig.10: Averaging of reference vector V r

Vr Ts  Vx T x Vy Ty  Vz Tz (7)

Vr  Vx  Tx Vy Ty Vz Tz (8)

Ts  Tx  Ty  Tz (9)
Fig.13: Proposed switching sequence for sector-1
Duty cycle of reference vector for region-1, involves
solving the three simultaneous equations Eq(7-9).
Table-2: Switching sequence for all the 4-regions of first sector
Region-1
d x  m ( 3 cos(  )  sin(  )) Tx/8 Ty/4 Tz/4 Tz/4 Ty/4 Tz/4 Tx/8 Ty/8 Tz/4 Ty/4 Tz/4 Tz/4 Ty/4 Tx/8
SS V2 V5 V7 V3 V4 V6 V1 V1 V6 V4 V3 V7 V5 V2
d y 1  3 m cos(  )  m sin(  ) Sa1 0 0 0 0 1 1 1 1 1 1 0 0 0 0
Sa2 0
d z  2 m sin(  ) (10) Sb1 0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
0
Sb2 0 0 1 1 1 1 1 1 1 1 1 1 0 0
Where, dx dy and dz are the duty cycles of nearest three
Sc1 0 0 0 0 0 0 1 1 0 0 0 0 0 0
vectors for region-1
Sc2 0 0 0 1 1 1 1 1 1 1 1 0 0 0
The Xilinx implementations and results of computation of
duty cycles are shown in Fig.11 and Fig.12 respectively.
Similarly, the Xilinx model are developed for other regions
Viz region-2, region-3 and region-4

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Region-2 on positive integer number on the selection pin as shown in

Ts/6 Ty/3 Tz/2 Tx/3 Tx/3 Tz/2 Ty/3 Tx/6 Fig.16. The complete xilinix model of proposed
SS V5 V7 V17 V4 V4 V17 V7 V5 SSSVPWM is given in Fig.17.
Sa1 0 0 1 1 1 1 0 0
Sa2 1 1 1 1 1 1 1 1
Sb1 0 0 0 0 0 0 0 0
Sb2 0 1 1 1 1 1 1 0
Sc1 0 0 0 0 0 0 0 0
Sc2 0 0 0 1 1 0 0 0
Region-3
Tx/4 Ty/2 Tz/2 Tx/4 Tx/4 Tz/2 Ty/2 Tx/4
SS V5 V16 V17 V4 V4 V17 V16 V5 Sa1
Sa1 0 1 1 1 1 1 1 0
Sa2 1 1 1 1 1 1 1 1
Sb1 0 0 0 0 0 0 0 0
Sb2 0 0 1 1 1 1 0 0
Sc1 0 0 0 0 0 0 0 0
Sb1
Sc2 0 0 0 1 1 0 0 0
Region-4
Tx/4 Ty/2 Tz/2 Tx/4 Tx/4 Tz/2 Ty/2 Tx/4
SS V7 V17 V16 V6 V6 V16 V17 V7
Sa1 0 1 1 1 1 1 1 0
Sa2 1 1 1 1 1 1 1 1 Sc2
Sb1 0 0 0 1 1 0 0 0
Sb2 1 1 0 1 1 0 1 1 Note: Sa2=1, Sb2=1, Sc1=0
Sc1 0 0 0 0 0 0 0 0 Fig 15: The symmetrical switching of the sector-1
Sc2 0 0 0 1 1 0 0 0
Table.3-Selection of Switching Sequence using Multiplexer

Sector-1 Sa1 Sa2 Sb1 Sb2 Sc1 Sc2

ii. PWM pulses generation SSSVPWM Sa1 Sa2 Sb1 Sb2 Sc1 Sc2
Sector-2
To generate the PWM pulses, the triangular wave of 2 KHz Sector-3 Sa1 Sa2 Sb1 Sb2 Sc1 Sc2
is generated using up-down counter and is compared with Sa1 Sa2 Sb1 Sb2 Sc1 Sc2
Sector-4
the duty cycles of corresponding regions of each sector
Sector-5 Sa1 Sa2 Sb1 Sb2 Sc1 Sc2
shown in Fig.14.
Sector-6 Sa1 Sa2 Sb1 Sb2 Sc1 Sc2

Fig.14: Comparison of Triangular signal with duty cycle

The symmetrical switching for sector-1 is shown in

Fig.15. It is observed that each switch is turned “ON” once
in each cycle.

iii. Selection of switching sequences

The maximum possible switching signals available for 6
sector and 6 upper switches of three level NPC converter are
resulting into 36 switching combinations as given in the
Table-3. Appropriate switching sequence is to be switched
based on the sector and region in which reference vector
lies. In view of this a logic is developed using Xilinx Fig.16: Selection of PWM pulse using De-multiplexer and its result
multiplexer, which select one input from many inputs based

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 International Conference on Inventive Systems and Control (ICISC 2019)
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Fig.17: Complete model of proposed SSSVPWM developed by Xilinx of FPGA

Fig.18 (a): Line to line voltages between VRY, VYB and VBR foe modulating index Mi<0.5

Fig.18(b): Line to line voltage between VRY, VYB and VBR foe modulating index 0.5<Mi<1.0

Fig. 18(c): Line to line voltage between VRY, VYB and VBR foe modulating index Mi>1

(a) (b) (c)

Fig.19: Line currents (a) (Mi) <0.5, (b) 0.5<Mi<1 and (c) Mi>1.0

(a) (b) (c)

Fig.20: FFT Analysis panel for (a) (Mi) <0.5, (b) 0.5<Mi<1 and (c) Mi>1.0

(a) (b)
Fig.21 :(a) DC voltage across the both capacitors of NPC converter, (b) Pole voltages at the mid point

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 International Conference on Inventive Systems and Control (ICISC 2019)
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is also observed from the Fig.21 is that SSSVPWM

IV. EXPERIMENTAL VALIDATION OF SSSVPWM maintains 150 DC voltages around both the capacitors and
This section explains validation of proposed SSSVPWM pole voltages are symmetrical in nature
algorithm through experimental setup as shown in Fig.22. V. CONCLUSION
The set up consists of 3-Ф, 50Hz, 415V autotransformer to The performance of algorithm is obtained in-terms of line
supply variable voltage at nominal frequency to the rectifier to line voltage, THD and DF for various modulating
unit. The output of the rectifier is connected to three level indices Viz. lower modulating index, optimal modulating
index and over modulating index. It is observed from the
Neutral Point Voltage source Inverter. The output of the hardware results that, proposed algorithm maintains the
three level inverter is controlled by proposed SSSVPWM equal DC voltage at both the capacitors of NPC converter.
through Wavect controller integrated with 12 PWM ports, 4- Further, it is also observed that THD and DF are lower
Voltage sensors and 4-current sensors, speed encoder and during the optimal modulating index leading to effective
bus DC bus utilization. Finally it is concluded that, the
Ethernet cable for the communication between hardware
complexity of three level SVPWM modulation algorithm is
and algorithm brought to that of two level inverter and address the
problem of narrow pulse width at midpoint of NPC
converter. It is also concluded the FPGA processor
provides adequate computational resources for the
implementation of proposed SSSVPWM.
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