1.1.

Filter Inductor Design

Referring to the worst-case design approach, it is observed that the average inductor voltage crosses
𝑉𝐷𝐶
when the peak-to-peak current variation occurs, so the current variation can be expressed:
2

𝑉𝑇𝐴 𝑉𝐷𝐶 1 𝑇𝑠
∆𝐼 = = ∙ ∙ (1)
𝐿 2 𝐿 4

Thus, the inductance is:

𝑇𝑠 𝑉𝐷𝐶
𝐿= = 15𝑚𝐻 (2)
8∆𝐼
The current in phase with 𝑉𝐴𝐶 is:

𝑃
𝐼𝑃𝐻 = = 10𝐴 (3)
𝑉𝐴𝐶

Thus, the ESR of the inductor is:

𝑃𝑙𝑜𝑠𝑠
𝑅= 2 ≈ 0.12Ω (4)
𝐼𝑃𝐻

1.2. Inverse Voltage Specify

No reactive power exchanged between inverter and the AC grid, thus 𝐼90 = 0. So 𝐼𝐴𝐶 = 𝐼𝑃𝐻 = 10𝐴.

The voltage across the inductor and its ESR is:

𝜔𝐿
𝑉̇𝑅𝐿 = 𝐼𝐴𝐶 ∙ √𝑅 2 + (𝜔𝐿)2 ∠ tan−1 ( ) ≈ 47.14∠88.54 𝑉 (5)
𝑅

The inverter voltage is:

𝑉̇𝑖𝑛𝑣 = 𝑉̇𝑅𝐿 + 𝑉𝐴𝐶

̇ = 47.14∠88.54° + 240∠0° ≈ 245.76∠11.05° 𝑉 (6)

To sum up, the inductor voltage and the inverter voltage can be expressed in the triangular form:

𝑉𝑅𝐿 = 47.14√2 sin(100𝜋𝑡 + 1.55) (7)

𝑉𝑖𝑛𝑣 = 254.76√2 sin(100𝜋𝑡 + 0.193) (8)

1
1.3. Inverter Voltage Validation

Figure 1. inverter schematics for validation

Figure 2. output active power for validation.

To validate the calculations in the preceding 2 sections, a fundamental inverter circuit was
implemented in PLECS, the voltage source is simulated by a controlled voltage source governed by
a sinewave generator. The calculated 𝑉𝑖𝑛𝑣 , 𝑅 and 𝐿 values were filled in the corresponding
components. In addition, the schematic incorporated “RMS” blocks to compute the active AC power,
thereby affirming the accuracy of the calculations.

In reference to figure 2, the output power remains constant at 2.4𝑘𝑊 during steady state condition,
thus the previous calculations are correct.

1.4. Current Controlling System Dynamic Modelling

Substituting the calculated resistance and inductance, the controlling plant can be represented by:

1 25 8
𝐺𝐼 (𝑠) = = ∙ (9)
𝑅 + 𝑠𝐿 3 𝑠+8

2
 Figure 3. Current Control Block Diagram

Assume the controller is a PI controller and the feedback transfer function is unity, so the
corresponding block diagram is shown in figure 3.

1.5. Current Controller Design

Coefficients in the PI controller can be calculated:

200
𝐶𝐿𝑇𝐹 =
𝐺𝑐 (𝑠)𝐺(𝑠)
= 3 𝐾(𝑠 + 𝑎) (10)
1 + 𝐺𝑐 (𝑠)𝐺(𝑠) 𝑠 2 + (200 𝐾 + 8) 𝑠 + 200 𝐾𝑎
3 3

200
2𝜉𝜔0 = ( 𝐾 + 8)
3 𝐾 = 65.85
⇒{ (11)
200 𝑎 = 2248.08
{ 𝜔02 = 𝐾𝑎
3

The current control loop step response was recorded in figure 4, with settling time highlighted. The
settling time serves as a metric for accessing the response speed. In the subsequent voltage controller
design section, the response speed of the voltage controller is expected to be 100 times slower than
that of the current controller.

3
 Figure 4. Inverter close loop step response with current controller.

The poles of the computed transfer function are:

𝑠 = −𝜉𝜔𝑛 ± 𝜔𝑛 √𝜉 2 − 1 ≈ −2199 ± 𝑗2243.55 (12)

With sisotool, the root locus was plotted and shown in figure 4. Notably, the computed poles align
with the those depicted in the root locus, thereby affirming the consistency between the calculated
transfer function and the ones derived in sisotool.

1.6. Current Controller Implementation

Figure 5. Inverter with current controller

Figure 5 demonstrates the schematic of the inverter with current controller incorporated. Full bridge
configuration was employed within the inverter to facilitate the elimination of high frequency
4
switching harmonics. The remaining part of the inverter remains the consistent as the one in section
1.3.

For the controller segment, the 𝐼𝐴𝐶 was directed to the probe while the reference current was
expressed through a sinewave signal. The error input is derived from the subtraction of the 2 current
signals.
∗
A series of mathematical manipulations were conducted to calculate 𝑉𝐵𝑂 (𝑡) and 𝑚(𝑡) (also shown
in the schematics in figure 5).

Figure 6. Current trajectory plot.

Figure 6 illustrates the current trajectory corresponding to the reference current and 𝐼𝐴𝐶 . In general,
the output current closely tracks the desired reference trajectory.

In addition, the ripples in the current waveform are caused by the inductor. There is a slight phase
difference between those 2 current signals, but the impact of the phase difference is negligible.

5
 Figure 7. case (a) system response.

Figure 7 demonstrates the system response when the desired AC power reference was subjected to a
step wise increase. For non-zero reference current situations, the inductor current consistently follows
the reference value. When the reference current is 0, 𝐼𝐴𝐶 is oscillating above and below the zero base
line. Such oscillations are caused by the inverter, the oscillations also account for the non-zero active
power (shown in figure 7 to the right) during the initial phase of the simulation.

Figure 8. case (b) system response.

Referring to figure 8, upon an application of a step wise decrement on the reference current, the
current present a 180° phase shift compared with the one shown in figure 7. Despite this alteration
6
in phase, the response of the output active power remains basically unchanged, but it is slightly higher
than its counterpart shown in figure 7 (notably, the steady state active power notably exceed 2.4𝑘𝑊).

To sum up, the controller had achieved a fast response, as evidenced by the negligible duration in
both case (a) and (b) where 𝐼𝐴𝐶 deviates from tracking the reference value.

1.7. DC Link Capacitor Design

The power through the DC link current is:

𝑅𝑀𝑆 𝑅𝑀𝑆
𝑃𝑐 (𝑡) = 𝑃𝑡𝑜𝑡𝑎𝑙 (𝑡) − 𝑃𝐴𝐶 (𝑡) = 𝑉𝐴𝐶 𝐼𝐴𝐶 cos(2𝜔𝑡) = 𝑉𝐷𝐶 𝐼𝐶 (𝑡) (13)

So, the current through the capacitor is:

𝑅𝑀𝑆 𝑅𝑀𝑆
𝑉𝐴𝐶 𝐼𝐴𝐶 cos(2𝜔𝑡)
𝐼𝐶 (𝑡) = (14)
𝑉𝐷𝐶

𝑑𝑉𝐶 (𝑡)
Referring to the equation 𝐼𝐶 (𝑡) = 𝐶 ∙ , the voltage ripple can be expressed as:
𝑑𝑡

𝑅𝑀𝑆 𝑅𝑀𝑆
1 1 𝑉𝐴𝐶 𝐼𝐴𝐶
𝑉𝑟𝑖𝑝𝑝𝑙𝑒 = ∫ 𝐼𝐶 (𝑡) 𝑑𝑡 = ∙ ∙ sin(2𝜔𝑡) (15)
𝐶 𝐶 2𝑉𝐷𝐶

Substituting sin(2𝜔𝑡) = 1, the maximum voltage ripple can be expressed:

𝑅𝑀𝑆 𝑅𝑀𝑆
𝑚𝑎𝑥 1 𝑉𝐴𝐶 𝐼𝐴𝐶 1
𝑉𝑟𝑖𝑝𝑝𝑙𝑒 = ∙ = ∙ 𝑉𝑟𝑖𝑝𝑝𝑙𝑒 (𝑝𝑒𝑎𝑘 𝑡𝑜 𝑝𝑒𝑎𝑘) = 0.5𝑉 (16)
𝐶 2𝑉𝐷𝐶 2

Thus, the DC link capacitance is:

𝐴𝐶 𝑅𝑀𝑆
𝑉𝑅𝑀𝑆 ∙ 𝐼𝐴𝐶
𝐶= 𝑚𝑎𝑥 ≈ 12.7𝑚𝐹 (17)
2𝜔𝑉𝐷𝐶 𝑉𝑟𝑖𝑝𝑝𝑙𝑒

1.8. Voltage Control System Dynamic Modelling

The energy stored in the DC capacitor is:

1 2
𝐸𝐶 = 𝐶𝑉 (18)
2 𝐷𝐶

The square of 𝑉𝐷𝐶 is:

7
 2
2 2
𝑉𝐷𝐶 = 𝐸𝐶 = 𝑃𝐶 𝑡 (19)
𝐶 𝐶
2
With Laplace Transform, the 𝑉𝐷𝐶 in s domain is:

2 (𝑠)
2 2
𝑉𝐷𝐶 = 𝑃𝐶 = − (𝑃𝐴𝐶 − 𝑃𝑃𝑉 )
𝑠𝐶 𝑠𝐶

Where 𝑉𝐷𝐶 is the reference voltage and the term −(𝑃𝐴𝐶 − 𝑃𝑃𝑉 ) is the error input to the control plant
(namely, the DC-link capacitor). So, the control plant transfer function is:

2 156.99
𝐺(𝑠) = ≈ (20)
𝑠𝐶 𝑠

The control block diagram for voltage control is shown in figure 9.

Figure 9. voltage controlling system block diagram.

1.9. DC Voltage Controller Design

Since the voltage controller output signal is fed to the current controlling system as reference, it is
imperative for the voltage control loop to possess a significantly reduced natural frequency (thereby
a decreased response speed) while maintaining the oscillation pattern unchanged. Consequently, for
the voltage controller, the natural frequency is adjusted to 10𝜋 𝑟𝑎𝑑 ∙ 𝑠 −1 and the damping ratio
retained at 0.7. Assuming that a PI controller is still sufficient, following the same logic in current
controller design, the controller transfer function can be derived:

𝐺𝑐 (𝑠)𝐺(𝑠) 156.99𝐾(𝑠 + 𝑎)
𝐶𝐿𝑇𝐹 = = 2 (21)
1 + 𝐺𝑐 (𝑠)𝐺(𝑠) 𝑠 + 156.99𝐾𝑠 + 156.99𝐾𝑎

2𝜉𝜔0 = 156.99𝐾 𝐾 = 0.28

{ ⇒{ (22)
𝜔02 = 156.99𝐾𝑎 𝑎 = 22.45

0.28(𝑠 + 22.45)
𝐺𝑐 (𝑠) = (23)
𝑠

8
 Figure 10. Voltage control loop schematics.

Figure 10 shows the schematics of the voltage controller. The reference voltage and the PV power
values are denoted by constant blocks. The DC-link capacitor plant is characterized by a controlled
voltage source and a capacitor possessing the designated capacitance value. A 1𝑝Ω resistor was
connected in series with the capacitor since the PLECS does not allow a single capacitor connected
in parallel with a voltage source.

A square root mathematical block was employed to the output signal, so the expected output
waveform should be roughly 600𝑉, identical to the reference DC voltage.

Figure 11. Controlled DC output response.

Figure 11 demonstrates the output response of the voltage controller. The output voltage becomes
steady after roughly 1.2𝑠, which proved that the system response is much slower than current control
loop. Furthermore, the output DC remains constant at 600𝑉 in steady state so the voltage controller
is reliable.

9
 Figure 12. The overall control diagram.

The control diagram including inverter, current and voltage control loop is shown in figure 10.
Following the same logic, the corresponding schematic was constructed in PLECS, the schematic is
shown in figure 13 below.

Figure 13. Inverter with voltage and current control circuit.

𝑃
For the integrated system, the power source in the inverter was replaced by a 4𝐴 (𝐼𝐷𝐶 = 𝑉 ) DC
𝐷𝐶

current source to simulate the function of the PV array. Both figure 7 and figure 8 in the previous
section have shown that during the initial phase, the output AC power is much lower than 2.4𝑘𝑊, so
the DC-link capacitor must discharge during the that period, thus the capacitor initial voltage was set
to be 600V. The other section of the inverter remains unchanged.

No alteration was made to the current control circuit.

10
For the voltage control circuit, all sections after the “-1 gain” block were removed, the output
representing the AC power was fed to the reference current calculator to compute the reference current
value.

Figure 14. DC-link Capacitor voltage (left) & Overall system response (right).

Referring to the waveform of the DC-link capacitor shown on the left of figure 14, the steady state
voltage fluctuates periodically, from roughly 599.5𝑉 to 600.5𝑉 (identical to the specification),
proving that the capacitance was chosen appropriately.

The output AC active power becomes stable within approximately 0.3𝑠 , and remains basically
constant at 2.4𝑘𝑊, so the overall control system is valid.

11