Sample Paper

FINALTERM EXAMINATION
Fall 2022
CS501 – Advance Computer Architecture

Time: 90 min
Marks: 60

Question No: 1 (Marks: 01) - Please choose the correct option

A collection of all possible machine language commands that a computer can
understand and execute is called ___________.

A. Bytecodes
B. Instruction Set
C. Mnemonics
D. Opcodes

Answer B)

Question No: 2 (Marks: 01) - Please choose the correct option

From the given subsets of the systems, to which subset does a computer
belong?

a) Mechanical System
b) Electrical System
c) Optical System
d) Biological System

Answer b)

Question No: 3 (Marks: 01) - Please choose the correct option

Which one of the followings is NOT related to the architecture of a computer?

A) Instruction Set
B) Control Signals
C) I/O mechanisms
D) I/O mechanics
E) Memory addressing modes

Answer: B)
Question No: 4 (Marks: 01) - Please choose the correct option
Which one of the following is the highest level of abstraction in digital design in which
the computer architect views the system for the description of system components and
their interconnections?

A) Processor-Memory-Switch level (PMS level)

B) Instruction Set Level
C) Register Transfer Level
D) Control Transfer Level

Answer: A)

Question No: 5 (Marks: 01) - Please choose the correct option

What is the working of Processor Status Word (PSW)?

A) To hold the address of the current process

B) To hold the current status of the processor.

C) To hold the instruction that the computer is currently processing

D) To hold the address of the next instruction in memory that is to be executed

Answer B)

Question No: 6 (Marks: 01) - Please choose the correct option

Which one of the following is the highest level of abstraction in digital design in
which the computer architect views the system for the description of system
components and their interconnections?

A) Processor-Memory-Switch level (PMS level)

B) Instruction Set Level
C) Register Transfer Level
D) None of the given

Answer A)

Question No: 7 (Marks: 01) - Please choose the correct option

Question No: 8 (Marks: 01) - Please choose the correct option

Which one of the following instructions is used to load register from memory using a
relative address?

A) la
B) lar
C) ldr
D) str

Answer C)

Question No: 9 (Marks: 01) - Please choose the correct option

In which of the following instructions, the data moves between a register in the processor
and a memory location (or another register)?

A) Arithmetic/logic
B) Load/store
C) Test/branch
D) None of the given

Answer B)

Question No: 10 (Marks: 01) - Please choose the correct option

Almost every commercial computer has its own particular ---------- language

A) 3GL
B) English language
C) Higher level language
D) Assembly language

Answer: D)

Question No: 11 (Marks: 01) - Please choose the correct option

In register-based machines, a _________ field is required in the instruction to identify a

register.

A) 4-bit
B) 6-bit
C) 8-bit
D) 16-bit

Answer B)

Question No: 12 (Marks: 01) - Please choose the correct option

Which of the following are the code size and the Number of bytes accessed from
memory, respectively for a 2-address instruction?

A) 4 bytes, 7 bytes
B) 7 bytes, 16 bytes
C) 10 bytes, 19 bytes
D) 13 bytes, 22 bytes

Answer B)

Question No: 13 (Marks: 01) - Please choose the correct option

Which of the following are the code size and the Number of bytes accessed from
memory, respectively for a 3-address instruction?

A) 0 bytes, 10 bytes
B) 4 bytes, 7 bytes
C) 7 bytes, 16 bytes
D) 10 bytes, 19 bytes

Answer D)

Question No: 14 (Marks: 01) - Please choose the correct option

Almost every commercial computer has its own particular ---------- language

A) 3GL
B) English language
C) Higher level language
D) Assembly language

Answer D)

Question No: 15 (Marks: 01) - Please choose the correct option

In which one of the following addressing modes, the value to be stored in memory is
obtained by directly retrieving it from another memory location?

A) Direct Addressing Mode

B) Immediate addressing mode
C) Indirect Addressing Mode
D) Register (Direct) Addressing Mode

Answer A)

Question No: 16 (Marks: 01) - Please choose the correct option

Which one of the following are the code size and the Number of memory bytes
respectively for a 2-address instruction?

A) 4 bytes, 7 bytes
B) 7 bytes, 16 bytes
C) 10 bytes, 19 bytes
D) 13 bytes, 22 bytes

Answer B)

Question No: 17 (Marks: 01) - Please choose the correct option

Which one of the following is an address (binary bit pattern) issued by CPU?

A) Memory
B) Effective
C) Base
D) Next instruction

Answer: B)

Question No: 18 (Marks: 01) - Please choose the correct option

Which one of the following are the code size and the Number of memory bytes
respectively for a 3-address instruction?

A) 0 bytes, 10 bytes
B) 4 bytes, 7 bytes
C) 7 bytes, 16 bytes
D) 10 bytes, 19 bytes

Answer D)

Question No: 19 (Marks: 01) - Please choose the correct option

In which of the following instructions the data move between a register in the processor
and a memory location (or another register) and are also called data movement?

A) Arithmetic/logic
B) Load/store
C) Test/branch
D) None of the given

Answer B)

Question No: 20 (Marks: 01) - Please choose the correct option

Which of the following statements is/are true about RISC processors’ claimed advantages
over CISC processors? (a) Keeping regularly accessed variables in registers as opposed to
keeping them in memory facilitates faster execution. (b) RISC CPUs outperform CISC
CPU’s in procedural programming environments. (c) Instruction pipelining has helped
RISC CPU’s to attain a target of 1 cycle per instruction. (d) It is easier to maintain the
“family concept” in RISC CPUs.

A) (a), (b) &(c)

B) (b), (c) & (e)
C) (c), (d) & (e)
D) (a), (c) & (d)

Answer A)

Question No: 21 (Marks: 01) - Please choose the correct option

What does the instruction “ldr R3, 58” of SRC do?

A) It will load the register R3 with the contents of the memory location M [PC+58]
B) It will load the register R3 with the relative address itself (PC+58).
C) It will store the register R3 contents to the memory location M [PC+58]
D) No operation

Answer A)
Question No: 22 (Marks: 01) - Please choose the correct option

What functionality is performed by the instruction “lar R3, 36” of SRC?

A) It will load the register R3 with the contents of the memory location M [PC+36]
B) It will load the register R3 with the relative address itself (PC+36).
C) It will store the register R3 contents to the memory location M [PC+36]
D) No operation

Answer B)

Question No: 23 (Marks: 01) - Please choose the correct option

In SRC, all the instructions are ___________ bits long.

A) 8
B) 16
C) 32
D) 64

Answer C)

Question No: 24 (Marks: 01) - Please choose the correct option

___________ instruction is used to load a register with an immediate data value.

a) la
b) lar
c) ld
d) None of the given

Answer A)

Question No: 25 (Marks: 01) - Please choose the correct option

Type D of SRC instruction format include.

3 ALU registers
4 ALU registers
1 ALU registers
2 ALU registers

Answer B)
Question No: 26 (Marks: 01) - Please choose the correct option

The instruction ---------------will load the register R3 with the contents of the memory
location M [PC+56]

A) Add R3, 56
B) lar R3, 56
C) ldr R3, 56
D) str R3, 56

Answer C)

Question No: 27 (Marks: 01) - Please choose the correct option

The data movement instructions ___________ data within the machine and to or from
input/output devices.

A) Store
B) Load
C) Move
D) None of given

Answer C)

Question No: 28 (Marks: 01) - Please choose the correct option

Which type of Instruction is stored in instruction register (IR)?

A) Current instruction
B) Next instruction
C) Previous instruction
D) Next and current instruction

Answer A)

Question No: 29 (Marks: 01) - Please choose the correct option

Which of the following bits of SRC instruction are used to hold an operand, an address
index, or a branch target register?

A) The bits 16 through 0

B) The bits 26 through 22
C) The bits 21 through 17
D) The bits 17 through 0

Answer C)

Question No: 30 (Marks: 01) - Please choose the correct option

Which operator is used to “name” registers, or part of registers, in the Register Transfer
Language (RTL)?

A) &
B) :=
C) :
D) ,

Answer B)

Question No: 31 (Marks: 01) - Please choose the correct option

Which type of Instruction holds by instruction register (IR)?

a) Current instruction
b) Next instruction
c) Previous instruction
d) Next and current instruction

Answer A)

Question No: 32 (Marks: 01) - Please choose the correct option

Which one of the following languages presents a simple, human-oriented language to

specify the operations, register communication and timing of the steps that take place
within a CPU to carry out higher level (user programmable) instructions?

A) Assembly Language
B) OOP(Object Oriented Language)
C) RTL (Register Transfer Language)
D) UML(Unified Modeling language)

Answer C)

Question No: 33 (Marks: 01) - Please choose the correct option

How much connections are required in a “point-to-point” scheme, whereas we have five
(5) m-bit registers.

A) 25
B) 30
C) 20
D) 24

Answer C)

Question No: 34 (Marks: 01) - Please choose the correct option

What does the RTL expression [M(1234)] means?

A) The contents of memory whose address is 1234.

B) The contents of data register 1234
C) The effective address of register 1234
D) The address of memory whose address is 1234.

Answer: A)

Question No: 35 (Marks: 01) - Please choose the correct option

Which of the following can be defined as an address of the operand in a computer type
instruction or the target address in a branch type instruction?

A) Base address
B) Binary address
C) Effective address
D) All of the given

Answer C)

Question No: 36 (Marks: 01) - Please choose the correct option

What does the word ‘D’ in the ‘D-flip-Flop’ stands for?

A) Data
B) Digital
C) Dynamic
D) Double

Answer A)

Question No: 37 (Marks: 01) - Please choose the correct option

Which one of the following is a binary cell capable of storing one bit of information?
A) Decoder
B) Flip-flop
C) Multiplexer
D) Diplexer

Answer A)

Question No: 38 (Marks: 01) - Please choose the correct option

mul is an _________ operation.

A) Logic
B) Shift
C) Arithmetic
D) Data Transfer

Answer C)

Question No: 39 (Marks: 01) - Please choose the correct option

________ is a miscellaneous instruction.

A) Shiftl
B) Store
C) Halt
D) Call

Answer C)

Question No: 40 (Marks: 01) - Please choose the correct option

In FALCON-A processor memory word size is of

A) 1 byte
B) 4 byte
C) 2 byte
D) 8 byte

Answer C)
[06 sample questions each of Marks 03]

Question No: 41 (Marks: 03)

Enlist the key components used to define any instruction set architecture.

Answer:

The following three key components define any instruction set architecture.

1. The operations the processor can execute

2. Data access mode for use as operands in the operations defined

3. Representation of the operations in memory

Question No: 42 (Marks: 03)

Explain the difference between Type-W and Type-V instruction formats of
EAGLE processor with respect to following attributes:

1.Size of opcode field

2.Number of destination operands
3.Size of constant field

Answer:

Size of opcode field

Type-W: 8-bits (0.5 marks)

Type-V: 5-bits (0.5 marks)

Number of destination operands

Type-W: 0 operand (0.5 marks)

Type-V: 1 operand (0.5 marks)

Size of constant field

Type-W: 8-bits (0.5 marks)

Type-V: 8-bits (0.5 marks)

Question No: 43 (Marks: 03)

Name any three addressing modes for SPARC Processor.

Answer:

1. Register

2. Immediate

3. Relative

Question No: 43 (Marks: 03)

Name any three addressing modes for SPARC Processor.

Answer:

1. Register

2. Immediate

3. Relative

Question No: 44 (Marks: 03)

In context of uni-bus SRC data path implementation, discuss the function of following
units.

1.Registers A and C
2.ALSU (Arithmetic Logic Shift Unit)

Solution:

Registers A and C
The registers A and C are required to hold an operand or result value while the bus is
busy transmitting some other value. Both these registers are programmer invisible.
ALSU

There is a 32-bit Arithmetic Logic Shift Unit, as shown in the diagram. It takes input
from memory or registers via the bus, computes the result according to the control signals
applied to it, and places it in the register C, from where it is finally transferred to its
destination.

Question No: 47 (Marks: 05)

Answer: Discuss any three units present in "UniBus DataPath" implementation of the
SRC.

Answer:

1. The Register File

The general-purpose register file includes 32 registers R0 to R31 each 32 bit wide. These
registers communicate with other components via the internal processor bus.

2. MAR

The Memory Address Register takes input from the ALSU as the address of the memory
location to be accessed and transfers the memory contents on that location onto the
memory sub-system.

3. MBR

The Memory Buffer Register has a bi-directional connection with both the memory sub-
system and the registers and ALSU. It holds the data during its transmission to and from
memory.

4. PC

The Program Counter holds the address of the next instruction to be executed. Its value is
incremented after loading of each instruction. The value in PC can also be changed based
on a branch decision in ALSU. Therefore, it has a bi-directional connection with the
internal processor bus.

5. IR

The Instruction Register holds the instruction that is being executed. The instruction
fields are extracted from the IR and transferred to the appropriate registers according to
the external circuitry (not shown in this diagram).

6. Registers A and C

The registers A and C are required to hold an operand or result value while the bus is
busy transmitting some other value. Both these registers are programmer invisible.

7. ALSU

There is a 32-bit Arithmetic Logic Shift Unit, as shown in the diagram. It takes input
from memory or registers via the bus, computes the result according to the control signals
applied to it, and places it in the register C, from where it is finally transferred to its
destination.

Question No: 48 (Marks: 05)

Write down any four characteristics of SPARC Register Windows.

Answer:
1) SPARC introduced the concept of overlapping register windows to avoid the procedure call
and return delays.

2) The register set is divided into groups, and only a subset of it is visible to the programmer at a
given time.

3) There are 120 registers in total, with first 8 devoted to global variables and remaining 112 for
register window system.

4) Using register windows, parameters are passed between procedures at zero cost.

Question No: 49 (Marks: 05)

What are the two privilege levels in Motorola MC68000 microprocessor? Explain the
difference between these levels.

Answer:
The MC68000 has two privilege levels:

1. Supervisor
2. User
When the S bit of status register is 1, the processor is in Supervisor state, the machine is
in supervisor mode. In supervisor mode, all the machine instructions can be executed,
including privileged instructions that allow manipulation of the status word and the
system stack pointer, A7'.
When S = 0, these privileged instructions cannot be executed.

Question No: 50 (Marks: 05)

How one can differentiate between Branch Hazards and Structural Hazards?

Answer:

Branch Hazards
The instruction following a branch is always executed whether the branch is taken. This
is called the branch delay slot. The compiler might issue a “nop” instruction in the branch
delay slot. Branch delays cannot be avoided by forwarding schemes.

Structural Hazards
A structural hazard occurs when attempting to access the same resource in different ways
at the same time. It occurs when the hardware is not enough to implement pipelining
properly e.g. when the machine does not support separate data and instruction memories.