W78E365/W78E365A Data Sheet

8-BIT MICROCONTROLLER

Table of Contents-

1. GENERAL DESCRIPTION.......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. PIN CONFIGURATIONS ............................................................................................................. 4
4. PIN DESCRIPTION ..................................................................................................................... 5
5. BLOCK DIAGRAM ...................................................................................................................... 6
6. FUNCTIONAL DESCRIPTION.................................................................................................... 7
6.1 RAM ................................................................................................................................ 7
6.2 Timers 0, 1, and 2 ........................................................................................................... 8
6.2.1 Timer 2 Output ................................................................................................................. 8
6.3 Clock ............................................................................................................................... 8
6.3.1 Crystal Oscillator .............................................................................................................. 8
6.3.2 External Clock .................................................................................................................. 8
6.4 Power Management ........................................................................................................ 8
6.4.1 Idle Mode.......................................................................................................................... 8
6.4.2 Power-down Mode............................................................................................................ 9
6.4.3 Reduce EMI Emission ...................................................................................................... 9
6.5 Reset ............................................................................................................................... 9
6.5.1 W78E365 Special Function Registers (SFRs) and Reset Values .................................... 9
6.6 Port 4 ............................................................................................................................ 10
6.6.1 Port Options Register ..................................................................................................... 11
6.6.2 INT2 / INT3 .................................................................................................................. 11
6.6.3 Port 4 Base Address Registers ...................................................................................... 13
6.7 Pulse Width Modulated Outputs (PWM) ....................................................................... 15
6.8 Watchdog Timer ........................................................................................................... 18
6.9 In-System Programming (ISP) Mode ............................................................................ 20
6.9.1 In-System Programming Control Register (CHPCON) ................................................... 21
6.10 Software Reset ............................................................................................................. 21
6.11 H/W Reboot Mode (Boot from LDROM) ....................................................................... 22
6.12 Security ......................................................................................................................... 25
7. ELECTRICAL CHARACTERISTICS ......................................................................................... 27
7.1 Absolute Maximum Ratings .......................................................................................... 27
7.2 D.C. Characteristics ...................................................................................................... 27
7.3 A.C. Characteristics ...................................................................................................... 29

Publication Release Date: January 12, 2009

-1- Revision A12
 W78E365/W78E365A

8. TIMING WAVEFORMS ............................................................................................................. 30

8.1 Program Fetch Cycle .................................................................................................... 30
8.2 Data Read Cycle ........................................................................................................... 31
8.3 Data Write Cycle ........................................................................................................... 32
8.4 Port Access Cycle ......................................................................................................... 33
9. TYPICAL APPLICATION CIRCUIT ........................................................................................... 34
9.1 External Program Memory and Crystal ......................................................................... 34
9.2 Expanded External Data Memory and Oscillator .......................................................... 35
10. PACKAGE DIMENSIONS ......................................................................................................... 36
10.1 40-pin DIP ..................................................................................................................... 36
10.2 44-pin PLCC ................................................................................................................. 36
10.3 44-pin PQFP ................................................................................................................. 37
10.4 48-pin LQFP .................................................................................................................. 38
11. APPLICATION NOTE ............................................................................................................... 39
11.1 In-system Programming Software Examples................................................................ 39
12. REVISION HISTORY ................................................................................................................ 44

Publication Release Date: January 12, 2009

-2- Revision A11
 W78E365/W78E365A

1. GENERAL DESCRIPTION
The W78E365 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E365 is fully compatible with the standard 8052. The
W78E365 contains a 64K bytes of main Flash APROM and a 4K bytes of auxiliary Flash LDROM
which allows the contents of the 64KB main APROM to be updated by the loader program located at
the LDROM; 256+1K bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an
additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a
eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside
the W78E365 allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security.
The W78E365 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

2. FEATURES
 Fully static design 8-bit CMOS microcontroller
 64K bytes of in-system programmable Flash EPROM for Application Program (APROM)
 4K bytes of auxiliary ROM for Loader Program (LDROM)
 256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable)
 Four 8-bit bi-directional ports; Port 0 has internal pull-up resisters enabled by software
 One 4-bit multipurpose programmable port (I/O, interrupt, Chip select function)
 Three 16-bit timer/counters
 One full duplex serial port
 Watchdog timer
 5 channel PWM
 Software Reset
 P1.0 T2 programmable clock out
 Eight-sources, two-level interrupt capability
 Built-in power management
 Code protection
 Packaged in
 Lead Free (RoHS) DIP 40: W78E365A40DL
 Lead Free (RoHS) PLCC 44: W78E365A40PL
 Lead Free (RoHS) PQFP 44: W78E365A40FL
 Lead Free (RoHS) LQFP 48: W78E365A40LL

Publication Release Date: January 12, 2009

-3- Revision A12
 W78E365/W78E365A

3. PIN CONFIGURATIONS
40-pin DIP 44-pin PLCC
/
T I
2 N A A A A
T2, P1.0 1 40 VDD E T T D D D D
T2EX, P1.1 2 39 P0.0, AD0 X 2 3 0 1 2 3
, , , , , , ,
P1.2 3 38 P0.1, AD1 P P P P P P P P P P
P1.3 4 37 P0.2, AD2 1 1 1 1 1 4 V 0 0 0 0
. . . . . . D . . . .
P1.4 5 36 P0.3, AD3 4 3 2 1 0 2 D 0 1 2 3
P1.5 6 35 P0.4, AD4
P1.6 7 34 P0.5, AD5 6 5 4 3 2 1 44 43 42 41 40
8 33 P0.6, AD6 P1.5 7 39 P0.4, AD4
P1.7
9 P1.6 8 38 P0.5, AD5
RST 32 P0.7, AD7
10 P1.7 9 37 P0.6, AD6
RXD, P3.0 31 EA
TXD, P3.1 11 RST 10 36 P0.7, AD7
30 ALE
12 RXD, P3.0 11 35 EA
INT0, P3.2 29 PSEN
13 INT2, P4.3 12 34 P4.1
INT1, P3.3 28 P2.7, A15
TXD, P3.1 13 33 ALE
T0, P3.4 14 27 P2.6, A14
T1, P3.5 15 INT0, P3.2 14 32 PSEN
26 P2.5, A13
16 P2.4, A12 INT1, P3.3 15 31 P2.7, A15
WR, P3.6 25
17 P2.3, A11 T0, P3.4 16 30 P2.6, A14
RD, P3.7 24
T1, P3.5 17 29
XTAL2 18 23 P2.2, A10 P2.5, A13
18 19 20 21 22 23 24 25 26 27 28
XTAL1 19 22 P2.1, A9
VSS 20 21 P2.0, A8 P P X X V P P P P P P
3 3 T T S 4 2 2 2 2 2
. . A A S . . . . . .
6 7 L L 0 0 1 2 3 4
, , 2 1 , , , , ,
/ / A A A A A
W R 8 9 1 1 1
R D 0 1 2

44-pin PQFP 48-pin LQFP

/
T I
VDD
P1.4
P1.3
P1.2
P1.1
P1.0
P4.2

P0.0
P0.1
P0.2
P0.3
NC

2 N A A A A
E T T D D D D
X 2 3 0 1 2 3
, , , , , , ,
48
47
46
45
44
43
42
41
40
39
38
37
P P P P P P P P P P
1 1 1 1 1 4 V 0 0 0 0 P1.5 1 36 NC
. . . . . . D . . . . P1.6 2 35 P0.4
4 3 2 1 0 2 D 0 1 2 3
P1.7 3 34 P0.5
RST 4 33 P0.6
44 43 42 41 40 39 38 37 36 35 34 P3.0 5 32 P0.7
P1.5 1 33 P0.4, AD4
2 32 P0.5, AD5 P4.3 6 31 EA
P1.6
3 31 P0.6, AD6 P3.1 7 30 P4.1
P1.7
4 30 P0.7, AD7 P3.2 8 29 ALE
RST
RXD, P3.0 5 29 EA P3.3 9 28 PSEN
INT2, P4.3 6 28 P4.1 P3.4 10 27 P2.7
TXD, P3.1 7 27 ALE P3.5 11 26 P2.6
INT0, P3.2 8 26 NC 12 25 P2.5
PSEN
13
14
15
16
17
18
19
20
21
22
23
24

INT1, P3.3 9 25 P2.7, A15

T0, P3.4 10 24 P2.6, A14
11 23
P3.6
P3.7
XTAL2
XTAL1
VSS
P4.0
P2.0
P2.1
P2.2
P2.3
P2.4
NC

T1, P3.5 P2.5, A13

12 13 14 15 16 17 18 19 20 21 22

P P X X V P P P P P P
3 3 T T S 4 2 2 2 2 2
. . A A S . . . . . .
6 7 L L 0 0 1 2 3 4
, , 2 1 , , , , ,
/ / A A A A A
W R 8 9 1 1 1
R D 0 1 2

Publication Release Date: January 12, 2009

-4- Revision A11
 W78E365/W78E365A

4. PIN DESCRIPTION
SYMBOL TYPE DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
EA I external ROM. The ROM address and data will not be presented on the bus if
the EA pin is high.
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
PSEN O H Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
ALE O H separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RESET: A high on this pin for two machine cycles while the oscillator is running
RST I L
resets the device.
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
XTAL1 I
external clock.
XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS I GROUND: ground potential.
VDD I POWER SUPPLY: Supply voltage for operation.
PORT 0: Function is the same as that of standard 8052.
P0.0  P0.7 I/O D This port also provides a multiplexed low order address/data bus during
accesses to external memory. Port 0 has internal pull-up resisters enabled by
software.
P1.0  P1.7 I/O H PORT 1: Function is the same as that of standard 8052.
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory. The P2.6
P2.0  P2.7 I/O H
and P2.7 also provide the alternate function REBOOT which is H/W reboot
from LD flash.
P3.0  P3.7 I/O H PORT 3: Function is the same as that of the standard 8052.
PORT 4: A bi-directional I/O. The P4.3 also provides the alternate function
P4.0  P4.7 I/O H
REBOOT which is H/W reboot from LD flash.

* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

Publication Release Date: January 12, 2009

-5- Revision A12
 W78E365/W78E365A

5. BLOCK DIAGRAM

P1.0
Port Port 1
1
Latch
P1.7
ACC B
P0.0
Port 0
Interrupt
Port
Latch 0
T1 T2
Timer P0.7
2
DPTR
Timer
0 PSW Stack Temp Reg.
ALU Pointer
Timer PC
1
Incrementor
UART
Addr. Reg.
P3.0
64KB
Port Port 3 SFR RAM
Address Flash APROM
3
Latch Instruction
Decoder
P3.7 & 4KB
Sequencer 256+1K bytes Flash LDROM
RAM & SFR
P2.0
Port
Port 2 2
Bus & Clock Latch
Controller P2.7
Port 4
P4.0 Port Latch
4
P4.3

Oscillator Reset Block Pow er control

ALE
XTAL1 XTAL2 PSEN RST VCC Vs s

Publication Release Date: January 12, 2009

-6- Revision A11
 W78E365/W78E365A

6. FUNCTIONAL DESCRIPTION
The W78E365 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 256+1K bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.

6.1 RAM
The internal data RAM in the W78E365 is 256+1K bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 1K bytes of AUX-RAM. These RAMs are addressed by different ways.
 RAM 0H  7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
 RAM 80H  FFH can only be addressed indirectly as the same as in 8051. Address pointers are
R0, R1 of the selected registers bank.
 AUX-RAM 0H  3FFH is addressed indirectly as the same way to access external data memory
with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than 3FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is enabled after a reset.
Clearing the bit 4 in CHPCON register will disable the access to AUX-RAM. When executing from
internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD .

Example:
CHPENR REG F6H
CHPCON REG BFH
XRAMAH REG A1H

MOV CHPENR , #87H

MOV CHPENR, #59H
ORL CHPCON, #00010000B ; enable AUX-RAM
MOV CHPENR, #00H
MOV XRAMAH, #01H ; internal high address
MOV R0, #23H
MOV A, #55H
MOVX @R0, A ; Write 55h data to 0123h AUX-RAM address.
MOV XRAMAH, #02H
MOV R1, #FFH ; Read data from 02FFh AUX-RAM address.
MOVX A, @R1
MOV DPTR, #0134H
MOV A, #78H
MOVX @DPTR, A ; Write 78h data to 0134h AUX-RAM address.
MOV DPTR, #7FFFH
MOVX A, @DPRT ; Read data from the external 7FFFh address SRAM

Publication Release Date: January 12, 2009

-7- Revision A12
 W78E365/W78E365A

6.2 Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.

6.2.1 Timer 2 Output

If set T2OE (T2MOD.1) bit and clear C/T2 (T2CON.1) bit at auto-reload mode, P1.0 will be toggled
once overflow.
TIMER 2 Mode
Bit: 7 6 5 4 3 2 1 0
T2OE
Mnemonic: T2MOD Address: C9H
T2OE: Enable this bit to toggle P1.0 pin while Timer2 has been overflowed.

6.3 Clock
The W78E365 is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78E365 relatively insensitive to duty cycle
variations in the clock.

6.3.1 Crystal Oscillator

The W78E365 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground.

6.3.2 External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.

6.4 Power Management

6.4.1 Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the
processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will
exit idle mode when either an interrupt or a reset occurs.

Publication Release Date: January 12, 2009

-8- Revision A11
 W78E365/W78E365A

6.4.2 Power-down Mode

When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware
reset or external interrupts INT0 to INT1 when enabled and set to level triggered.

6.4.3 Reduce EMI Emission

The W78E365 allows user to diminish the gain of on-chip oscillator amplifier by using programmer to
clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the
external crystal operating improperly at high frequency. The value of C1 and C2 may need some
adjustment while running at lower gain.

ALE Off Function

Auxiliary Register
Bit: 7 6 5 4 3 2 1 0
- - - - - - - ALEOFF
Mnemonic: AUXR Address: 8EH
ALEOFF: Set this bit to disable ALE output.

6.5 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E365 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.

6.5.1 W78E365 Special Function Registers (SFRs) and Reset Values

F8
+B CHPENR
F0
00000000 00000000

E8
+ACC
E0
00000000
+P4 PWMP PWM0 PWM1 PWMCON1 PWM2 PWM3
D8
11111111 00000000 00000000 00000000 00000000 00000000 00000000
+PSW
D0
00000000
+T2CON T2MOD RCAP2L RCAP2H TL2 TH2 PWMCON2 PWM4
C8
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+XICON P4CONA P4CONB SFRAL SFRAH SFRFD SFRCN
C0
00000000 00000000 00000000 00000000 00000000 00000000 00000000

Publication Release Date: January 12, 2009

-9- Revision A12
 W78E365/W78E365A

W78E365 Special Function Registers (SFRs) and Reset Values, continued

+IP CHPCON
B8
00000000 00x11000
+P3 P43AL P43AH
B0
11111111 00000000 00000000
+IE P42AL P42AH P4CSIN
A8
00000000 00000000 00000000 00000000
+P2 XRAMAH
A0
11111111 00000000
+SCON SBUF
98
00000000 xxxxxxxx
+P1 P41AL P41AH
90
11111111 00000000 00000000
+TCON TMOD TL0 TL1 TH0 TH1 AUXR WDTC
88
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+P0 SP DPL DPH P40AL P40AH POR PCON
80
11111111 00000111 00000000 00000000 00000000 00000000 00000000 00110000
Notes:
1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable.
2. The text of SFR with bold type characters are extension function registers.

6.6 Port 4
Port 4, address D8H, is a 8-bit multipurpose programmable I/O port. Each bit can be configured
individually by software. The Port 4 has four different operation modes.
Mode 0: P4.0P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as
external interrupt PSEN and INT2 if enabled.
Mode 1: P4.0P4.3 are read strobe signals that are synchronized with RD signal at specified
addresses. These signals can be used as chip-select signals for external peripherals.

Mode 2: P4.0P4.3 are write strobe signals that are synchronized with WR signal at specified
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 3: P4.0P4.3 are read/write strobe signals that are synchronized with RD or WR signal at
specified addresses. These signals can be used as chip-select signals for external
peripherals.
When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.

Publication Release Date: January 12, 2009

- 10 - Revision A11
 W78E365/W78E365A

6.6.1 Port Options Register

Bit: 7 6 5 4 3 2 1 0
- - - - - - - P0UP
Mnemonic: POR Address: 86H

P0UP: Enable Port 0 weak up. The pins of Port 0 can be configured with either the open drain or
standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When
the P0UP bit in the POR register is set, the pins of port 0 will perform a bi-directional I/O port with
internal pull-up that is structurally the same Port2.

6.6.2 INT2 / INT3

Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown
by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable
but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the
XICON register, one can use the "SETB ( CLR ) bit" instruction. For example, "SETB 0C2H" sets the
EX2 bit of XICON.

XICON - external interrupt control (C0H)

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Publication Release Date: January 12, 2009

- 11 - Revision A12
 W78E365/W78E365A

Eight-source interrupt information:

POLLING ENABLE INTERRUPT
VECTOR
INTERRUPT SOURCE SEQUENCE WITHIN REQUIRED TYPE
ADDRESS
PRIORITY LEVEL SETTINGS EDGE/LEVEL
External Interrupt 0 03H 0 (highest) IE.0 TCON.0
Timer/Counter 0 0BH 1 IE.1 -
External Interrupt 1 13H 2 IE.2 TCON.2
Timer/Counter 1 1BH 3 IE.3 -
Serial Port 23H 4 IE.4 -
Timer/Counter 2 2BH 5 IE.5 -
External Interrupt 2 33H 6 XICON.2 XICON.0
External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

P4CONB (C3H)
BIT NAME FUNCTION
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
P43FUN1 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address
7, 6
P43FUN0 range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register
P43AH, P43AL.
01: Compare the 15 high bits (A15A1) of address bus with the base address
P43CMP1
5, 4 register P43AH, P43AL.
P43CMP0
10: Compare the 14 high bits (A15A2) of address bus with the base address
register P43AH, P43AL.
11: Compare the 8 high bits (A15A8) of address bus with the base address
register P43AH, P43AL.
P42FUN1 The P4.2 function control bits which are the similar definition as P43FUN1,
3, 2
P42FUN0 P43FUN0.
P42CMP1 The P4.2 address comparator length control bits which are the similar definition
1, 0
P42CMP0 as P43CMP1, P43CMP0.

Publication Release Date: January 12, 2009

- 12 - Revision A11
 W78E365/W78E365A

P4CONA (C2H)
BIT NAME FUNCTION
P41FUN1 The P4.1 function control bits which are the similar definition as P43FUN1,
7, 6
P41FUN0 P43FUN0.
P41CMP1 The P4.1 address comparator length control bits which are the similar definition
5, 4
P41CMP0 as P43CMP1, P43CMP0.
P40FUN1 The P4.0 function control bits which are the similar definition as P43FUN1,
3, 2
P40FUN0 P43FUN0.
P40CMP1 The P4.0 address comparator length control bits which are the similar definition
1, 0
P40CMP0 as P43CMP1, P43CMP0.

P4CSIN (AEH)
BIT NAME FUNCTION
The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe
signal.
= 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe
7 P43CSINV
signal.
= 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe
signal.
6 P42CSINV The similarity definition as P43SINV.
5 P41CSINV The similarity definition as P43SINV.
4 P40CSINV The similarity definition as P43SINV.
3 - Reserve
2 - Reserve
1 - 0
0 - 0

6.6.3 Port 4 Base Address Registers

P40AH, P40AL:
The Base address register for comparator of P4.0. P40AH contains the high-order byte of address,
P40AL contains the low-order byte of address.
P41AH, P41AL:
The Base address register for comparator of P4.1. P41AH contains the high-order byte of address,
P41AL contains the low-order byte of address.
P42AH, P42AL:
The Base address register for comparator of P4.2. P42AH contains the high-order byte of address,
P42AL contains the low-order byte of address.
P43AH, P43AL:
The Base address register for comparator of P4.3. P43AH contains the high-order byte of address,
P43AL contains the low-order byte of address.

Publication Release Date: January 12, 2009

- 13 - Revision A12
 W78E365/W78E365A

P4 (D8H)
BIT NAME FUNCTION
7 P47 I/O pin
6 P46 I/O pin.
5 P45 I/O pin.
4 P44 I/O pin.
3 P43 Port 4 Data bit which outputs to pin P4.3 at mode 0.
2 P42 Port 4 Data bit. which outputs to pin P4.2 at mode 0.
1 P41 Port 4 Data bit. which outputs to pin P4.1at mode 0.
0 P40 Port 4 Data bit which outputs to pin P4.0 at mode 0.

Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H 
1237H and positive polarity, and P4.1  P4.3 are used as general I/O ports.
MOV P40AH, #12H
MOV P40AL, #34H ; Base I/O address 1234H for P4.0
MOV P4CONA, #00001010B ; P4.0 a write strobe signal and address line A0 and A1 are masked.
MOV P4CONB, #00H ; P4.1  P4.3 as general I/O port which are the same as PORT1
MOV P2ECON, #10H ; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity
; default is negative.
Then any instruction MOVX @DPTR, A (with DPTR = 1234H  1237H) will generate the positive
polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of
data #XX to pin P4.3  P4.1.
P4xCSINV
P4 REGISTER
P4.x DATA I/O

RD_CS
MUX 4->1
WR_CS
READ
WRITE RD/WR_CS

PIN
P4.x

ADDRESS BUS P4xFUN0

EQUAL P4xFUN1

REGISTER
P4xAL Bit Length
P4xAH P4.x INPUT DATA BUS
Selectable
comparator
REGISTER
P4xCMP0
P4xCMP1

Publication Release Date: January 12, 2009

- 14 - Revision A11
 W78E365/W78E365A

6.7 Pulse Width Modulated Outputs (PWM)

There are five pulse width modulated output channels to generate pulses of programmable length and
interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for
the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts
modular 255 (0 ~ 254). The value of the 8-bit counter compared to the contents of five registers:
PWM0, PWM1, PWM2, PWM3 and PWM4. Provided the contents of either these registers is greater
than the counter value, the corresponding PWM0, PWM1, PWM2, PWM3 or PWM4 output is set
HIGH. If the contents of these registers are equal to, or less than the counter value, the output will be
LOW. The pulse-width-ratio is defined by the contents of the registers PWM0, PWM1, PWM2, PWM3
and PWM4. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of
1/255. ENPWM0, ENPWM1, ENPWM2, ENPWM3 and ENPWM4 bit will enable or disable PWM
output.
Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be
proportional to the contents of PWM0/1/2/3/4. The repetition frequency fpwm , at the PWM0/1/2/3/4
output is given by:
fosc
fpwm 
2  (1  PWMP )  255

Prescaler division factor = PWM + 1

(PWMn)
PWMn high/low ratio of PWMn 
255 - (PWMn)

This gives a repetition frequency range of 123 Hz to 31.4K Hz ( fosc = 16M Hz). By loading the PWM
registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level,
respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the
PWM registers when they are loaded with FFH.
When a compare register (PWM0, PWM1, PWM2, PWM3, PWM4) is loaded with a new value, the
associated output updated immediately. It does not have to wait until the end of the current counter
period. There is weakly pulled high on PWM output.

Publication Release Date: January 12, 2009

- 15 - Revision A12
 W78E365/W78E365A

PWM0 PWM0
ENPWM 0/1/2/3/4/5 Register Counter
X
+
PWM0
>
PWMP Y (P1.3)
1/2 8-bits Counter PWM0OE
Counter --
Fosc
PWM1 PWM1 X
Register Counter +
PWM1
> (P1.4)
Y PWM1OE
-

PWM2 PWM2 X
Register Counter +
PWM2
>
Y PWM2OE
(P1.5)
-

X
PWM3 PWM3 +
Register Counter PWM3
Y > (P1.6)
- PWM3OE

PWM4 PWM4
X
+
Register Counter
PWM4
Y >
(P1.7)
PWM4OE
-

FIGURE 1 PWM DIAGRAM

Please refer as below code.

mov pwmcon1, #00110011b ; enable pwm3, 2, 1, 0
mov pwmcon2, #00000101b ; enable pwm4
mov pwmp, #40h ; Fpwm = XT/(2*(1+pwmp)*255)
jb p1.3, $
mov pwm0, #14h ; duty cycle high/low = pwm0/(255-pmw0)
jb p1.4, $
mov pwm1, #18h
jb p1.5, $
mov pwm2, #20h
jb p1.6, $
mov pwm3, #b0h
jb p1.7,$
mov pwm4, #40h
mov pwmcon1, #11111111b ; output enable pwm3, 2, 1, 0

Publication Release Date: January 12, 2009

- 16 - Revision A11
 W78E365/W78E365A

PWM3 Register
Bit: 7 6 5 4 3 2 1 0

Mnemonic: PWM3 Address: DEH

PWM2 Register
Bit: 7 6 5 4 3 2 1 0

Mnemonic: PWM2 Address: DDH

PWM Control 1 Register

Bit: 7 6 5 4 3 2 1 0
PWM3OE PWM2OE ENPWM3 ENPWM2 PWM1OE PWM0OE ENPWM1 ENWPM0

Mnemonic: PWMCON1 Address: DCH

PWM3OE: Output enable for PWM3
PWM2OE: Output enable for PWM2
ENPWM3: Enable PWM3
ENPWM2: Enable PWM2
PWM1OE: Output enable for PWM1
PWM0OE: Output enable for PWM0
ENPWM1: Enable PWM1
ENPWM0: Enable PWM0

PWM1 Register
Bit: 7 6 5 4 3 2 1 0

Mnemonic: PWM1 Address: DBH

PWM0 Register
Bit: 7 6 5 4 3 2 1 0

Mnemonic: PWM0 Address: DAH

PWMP Register
Bit: 7 6 5 4 3 2 1 0

Mnemonic: PWMP Address: D9H

Publication Release Date: January 12, 2009

- 17 - Revision A12
 W78E365/W78E365A

PWM4 Register
Bit: 7 6 5 4 3 2 1 0

Mnemonic: PWM4 Address: CFH

PWM Control 2 Register

Bit: 7 6 5 4 3 2 1 0
- - - - - PWM4OE - ENWPM4
Mnemonic: PWMCON2 Address: CEH
PWM4OE: Output enable for PWM4
ENPWM: Enable for PWM4

6.8 Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro-
magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit: 7 6 5 4 3 2 1 0
ENW CLRW WIDL - - PS2 PS1 PS0
Mnemonic: WDTC Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.

Publication Release Date: January 12, 2009

- 18 - Revision A11
 W78E365/W78E365A

PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS20 as follows:

PS2 PS1 PS0 PRESCALER SELECT

0 0 0 2
0 0 1 4
0 1 0 8
0 1 1 16
1 0 0 32
1 0 1 64
1 1 0 128
1 1 1 256

The time-out period is obtained using the following equation:

1
 214  PRESCALER  1000  12 mS
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.

WIDL ENW

IDLE
EXTERNAL
RESET
INTERNAL
14-BIT TIMER RESET
OSC 1/12 PRESCALER
CLEAR

Watchdog Timer Block Diagram CLRW

Typical Watch-Dog time-out period when OSC = 20 MHz

PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD

0 0 0 19.66 mS
0 0 1 39.32 mS
0 1 0 78.64 mS
0 1 1 157.28 mS
1 0 0 314.57 mS
1 0 1 629.14 mS
1 1 0 1.25 S
1 1 1 2.50 S

Publication Release Date: January 12, 2009

- 19 - Revision A12
 W78E365/W78E365A

6.9 In-System Programming (ISP) Mode

The W78E365 equips one 64K byte of main ROM bank for application program (called APROM) and
one 4K byte of auxiliary ROM bank for loader program (called LDROM). In the normal operation, the
microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the
W78E365 allows user to activate the In-System Programming (ISP) mode by setting the CHPCON
register. The CHPCON is read-only by default, software must write two specific values 87H, then
59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing
CHPENR register with the values except 87H and 59H will close CHPCON register write
attribute. The W78E365 achieves all in-system programming operations including enter/exit ISP
Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the
device will enter in-system programming mode after a wake-up from idle mode. Because device needs
proper time to complete the ISP operations before awaken from idle mode, software may use timer
interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for
revising contents of APROM, software located at APROM setting the CHPCON register then enter idle
mode, after awaken from idle mode the device executes the corresponding interrupt service routine in
LDROM. Because the device will clear the program counter while switching from APROM to LDROM,
the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The
device offers a software reset for switching back to APROM while the content of APROM has been
updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset
to reset the CPU. The software reset serves as a external reset. This in-system programming feature
makes the job easy and efficient in which the application needs to update firmware frequently. In some
applications, the in-system programming feature make it possible to easily update the system firmware
without opening the chassis.

SFRAH, SFRAL: The objective address of on-chip ROM in the in-system programming mode.
SFRAH contains the high-order byte of address, SFRAL contains the low-order byte of address.

SFRFD: The programming data for on-chip ROM in programming mode.

SFRCN: The control byte of on-chip ROM programming mode.

SFRCN (C7)
BIT NAME FUNCTION
7 - Reserve.
On-chip ROM bank select for in-system programming.
6 WFWIN = 0: 64K bytes ROM bank is selected as destination for re-programming.
= 1: 4K bytes ROM bank is selected as destination for re-programming.
5 OEN ROM output enable.
4 CEN ROM chip enable.
3, 2, 1, 0 CTRL[3:0] The flash control signals

Publication Release Date: January 12, 2009

- 20 - Revision A11
 W78E365/W78E365A

MODE WFWIN CTRL<3:0> OEN CEN SFRAH, SFRAL SFRFD

Erase 64KB APROM 0 0010 1 0 X X
Program 64KB APROM 0 0001 1 0 Address in Data in
Read 64KB APROM 0 0000 0 0 Address in Data out
Erase 4KB LDROM 1 0010 1 0 X X
Program 4KB LDROM 1 0001 1 0 Address in Data in
Read 4KB LDROM 1 0000 0 0 Address in Data out

6.9.1 In-System Programming Control Register (CHPCON)

CHPCON (BFH)
BIT NAME FUNCTION
When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
7 SWRESET
will enforce microcontroller reset to initial condition just like power on reset.
6 - Reserve.
This bit is read only. 1: CPU is running LDROM program. 0: CPU is running
5 LD/AP
APROM program.
1: Enable on-chip AUX-RAM.
4 ENAUXRAM
0: Disable the on-chip AUX-RAM
3 1 Must be 1
2 - Reserve.
When this bit is set to 1, and both SWRESET and FPROGEN are set to 1. It
1 FBOOTSL
will enforce microcontroller reset to initial condition just like power on reset.
When this bit is set to 1, and both SWRESET and FBOOTSL are set to 1. It
0 FPROGEN
will enforce microcontroller reset to initial condition just like power on reset.
This register is protected by CHPENR register. Please write as below procedures while you would like
to write CHPCON register.
Mov CHPENR, #87h
Mov CHPENR, #59h
Anl CHPCON, #EFh ; Disable AUX-RAM
Mov CHPENR, #0h

6.10 Software Reset

Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFLASH after
time out.

Publication Release Date: January 12, 2009

- 21 - Revision A12
 W78E365/W78E365A

6.11 H/W Reboot Mode (Boot from LDROM)

By default, the W78E365 boots from APROM program after a power on reset. On some occasions,
user can force the W78E365 to boot from the LDROM program via following settings. The possible
situation that you need to enter H/W REBOOT mode when the APROM program can not run properly
and device can not jump back to LDROM to execute in-system programming function. Then you can
use this H/W REBOOT mode to force the W78E365 jumps to LDROM and executes in-system
programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to
switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY
and EJECT buttons on the panel. When the APROM program fails to execute the normal application
program. User can press both two buttons at the same time and then turn on the power of the personal
computer to force the W78E365 to enter the H/W REBOOT mode. After power on of personal
computer, you can release both buttons and finish the in-system programming procedure to update the
APROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN
pin value at reset to prevent from accidentally activating the programming mode or H/W REBOOT
mode. It is necessary to add 10K resistor on these P2.6, P2.7 and P4.3 pins.

H/W Reboot Mode

P4.3 P2.7 P2.6 MODE
X L L REBOOT
L X X REBOOT

The Reset Timing For Entering

F04KBOOT Mode

P2.7 Hi-Z

P2.6 Hi-Z

RST
30 mS
10 mS

Publication Release Date: January 12, 2009

- 22 - Revision A11
 W78E365/W78E365A

The Algorithm of In-System Programming

Part 1:32KB APROM

START procedure of entering
In-System Programming Mode

Enter In-System No
Programming Mode ?
(conditions depend on
user's application)

Yes

Setting control registers

MOV CHPENR,#87H Execute the normal application
MOV CHPENR,#59H
MOV CHPCON,#03H program

Setting Timer (about 1.5 us)

and enable timer interrupt

END

Start Timer and enter idle Mode.

(CPU will be wakened from idle mode
by timer interrupt, then enter In-System
Programming mode)

CPU w ill be w akened by interrupt and

re-boot f rom 4KB LDROM to execute
the loader program.

Go

Publication Release Date: January 12, 2009

- 23 - Revision A12
 W78E365/W78E365A

Part 2: 4KB LDROM

Go Procedure of Updating
the 32KB APROM

Timer Interrupt Service Routine:

Stop Timer & disable interrupt

PGM

Yes
Is F04KBOOT Mode? Yes
End of Programming ?
(CHPCON.7=1)

No
No
Reset the CHPCON Register:
MOV CHPENR,#87H
Setting Timer and enable Timer Yes
MOV CHPENR,#59H interrupt for w ake-up . Is currently in the
MOV CHPCON,#03H (50us for program operation) F04KBOOT Mode ?

No

Softw are reset CPU and

Get the parameters of new code
re-boot from the 32KB
Setting Timer and enable Timer (Address and data bytes)
APROM.
interrupt for w ake-up . through I/O ports, UART or
MOV CHPENR,#87H
(15 ms for erasing operation) other interfaces.
MOV CHPENR,#59H
MOV CHPCON,#83H

Setting erase operation mode:

MOV SFRCN,#22H
(Erase 32KB APROM) Setting control registers for
programming:
Hardw are Reset
MOV SFRAH,#ADDRESS_H to re-boot from
MOV SFRAL,#ADDRESS_L new 32 KB APROM.
Start Timer and enter IDLE MOV SFRFD,#DATA (S/W reset is
Mode. MOV SFRCN,#21H
(Erasing...) invalid in F04KBOOT
M ode)

End of erase
operation. CPU w ill
be w akened by Timer END
interrupt.
Executing new code
from address
00H in the 32KB APROM.

PGM

Publication Release Date: January 12, 2009

- 24 - Revision A11
 W78E365/W78E365A

6.12 Security
During the on-chip ROM programming mode, the ROM can be programmed and verified repeatedly.
Until the code inside the ROM is confirmed OK, the code can be protected. The protection of ROM and
those operations on it are described below.
The W78E365 has a Security Register that can be accessed in programming mode. Those bits of the
Security Registers can not be changed once they have been programmed from high to low. They can
only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the
LDROM space.

0000h
4KB On-chip ROM
Program Memory 32KB On-chip ROM
Security Bits Program Memory
B7 Reserved B2 B1 B0 LDROM
0FFFh
APROM
B0: Lock bit, logic 0: active
B1: MOVC inhibit,
logic 0: the MOVC instruction in external memory
cannot access the code in internal memory. 7FFFh
logic 1: no restriction. Reserved
Reserved
B2: Encryption
logic 0: the encryption logic enable
logic 1: the encryption logic disable
B07: Osillator Control
logic 0: 1/2 gain Security Register FFFFh
logic 1: Full gain
Default 1 for all security bits.
Reserved bits must be kept in logic 1.

Special Setting Register

Lock bit
This bit is used to protect the customer's program code in the W78E365. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
ROM data and Security Register can not be accessed again.

MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.

Publication Release Date: January 12, 2009

- 25 - Revision A12
 W78E365/W78E365A

Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.

Oscillator Control
W78E365/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to
set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly
affect the external crystal operation at high frequency above 24 MHz. The value of R and C1, C2 may
need some adjustment while running at lower gain.

Publication Release Date: January 12, 2009

- 26 - Revision A11
 W78E365/W78E365A

7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
PARAMETER SYMBOL MIN. MAX. UNIT
DC Power Supply VDDVSS -0.3 +6.0 V
Input Voltage VIN VSS -0.3 VDD +0.3 V
Operating Temperature TA 0 70 C
Storage Temperature TST -55 +150 C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

7.2 D.C. Characteristics

(VDD  VSS= 5V 10%, TA = 25C, Fosc = 20 MHz, unless otherwise specified.)

SPECIFICATION
SYMBOL PARAMETER TEST CONDITIONS
MIN. MAX. UNIT
VDD Operating Voltage 4.5 5.5 V RST = 1, P0 = VDD
No load
IDD Operating Current - 20 mA
VDD = 5.5V
Idle mode
IIDLE Idle Current - 6 mA
VDD = 5.5V
10 Power-down mode
IPWDN Power Down Current - A
VDD = 5.5V
Input Current VDD = 5.5V
IIN1 -50 +10 A
P1, P2, P3, P4 VIN = 0V or VDD
Input Current VDD = 5.5V
IIN2 -10 +300 A
RST 0<VIN<VDD
Input Leakage Current VDD = 5.5V
ILK -10 +10 A
P0, EA 0V<VIN<VDD

[*4] Logic 1 to 0 Transition Current VDD = 5.5V

ITL -500 -200 A
P1, P2, P3, P4 VIN = 2.0V
Input Low Voltage
VIL1 0 0.8 V VDD = 4.5V
P0, P1, P2, P3, P4, EA
Input Low Voltage
V IL2 0 0.8 V VDD = 4.5V
RST

Publication Release Date: January 12, 2009

- 27 - Revision A12
 W78E365/W78E365A

D.C. Characteristics, continued

SPECIFICATION
SYMBOL PARAMETER TEST CONDITIONS
MIN. MAX. UNIT
Input Low Voltage
V IL3 [*4] 0 0.8 V VDD = 4.5V
XTAL1
Input High Voltage
VIH1 2.4 VDD +0.2 V VD D = 5.5V
P0, P1, P2, P3, P4, EA
Input High Voltage VDD = 5.5V
VIH2 3.5 VDD +0.2 V
RST
Input High Voltage VDD = 5.5V
VIH3 [*4] 3.5 VDD +0.2 V
XTAL1
Output Low Voltage VDD = 4.5V
VOL1 - 0.45 V
P1, P2, P3, P4 IOL = +2 mA
Output Low Voltage VDD = 4.5V
VOL2 [*3]
- 0.45 V
P0, ALE, PSEN IOL = +4 mA
Sink current VDD = 4.5V
Isk1 4 8 mA
P1, P3, P4 VOL = 0.45V
Sink current VDD=4.5V
Isk2 10 14 mA
P0, P2, ALE, PSEN VOL = 0.45V
Output High Voltage VDD = 4.5V
VOH1 2.4 - V
P1, P2, P3, P4 IOH = -100 A
Output High Voltage VDD = 4.5V
VOH2 2.4 - V
P0, ALE, PSEN
[*3]
IOH = -400 A
Source current VDD = 4.5V
Isr1 -120 -180 A
P1, P2, P3, P4 VOH = 2.4V
Source current VDD =4.5V
Isr2 -10 -14 mA
P0, P2, ALE, PSEN VOH = 2.4V
Notes:
*1. RST pin is a Schmitt trigger input.
*2. P0, ALE and PSEN are tested in the external access mode.
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.

Publication Release Date: January 12, 2009

- 28 - Revision A11
 W78E365/W78E365A

7.3 A.C. Characteristics

The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (T CP), and actual parts will usually
experience less than a 20 nS variation.

Clock Input Waveform

XTAL1
TCH
TCL

FOP, TCP

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Operating Speed FOP 0 - 40 MHz 1
Clock Period TCP 25 - - nS 2
Clock High TCH 20 - - nS 3
Clock Low TCL 20 - - nS 3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.

Publication Release Date: January 12, 2009

- 29 - Revision A12
 W78E365/W78E365A

8. TIMING WAVEFORMS
8.1 Program Fetch Cycle

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
XTAL1

TALW
ALE
TAPL

PSEN
TPSW
TAAS

PORT 2
TPDA
TAAH TPDH, TPDZ

PORT 0
Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Address Valid to ALE Low TAAS 1 TCP- - - nS 4
Address Hold from ALE Low TAAH 1 TCP- - - nS 1, 4
ALE Low to PSEN Low TAPL 1 TCP- - - nS 4

PSEN Low to Data Valid TPDA - - 2 TCP nS 2

Data Hold after PSEN High TPDH 0 - 1 TCP nS 3

Data Float after PSEN High TPDZ 0 - 1 TCP nS
ALE Pulse Width TALW 2 TCP- 2 TCP - nS 4
PSEN Pulse Width TPSW 3 TCP- 3 TCP - nS 4
Notes:
1. P0.0P0.7, P2.0P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "" (due to buffer driving delay and wire loading) is 20 nS.

Publication Release Date: January 12, 2009

- 30 - Revision A11
 W78E365/W78E365A

8.2 Data Read Cycle

S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3
XTAL1

ALE

PSEN

PORT 2 A8-A15

A0-A7 DATA
PORT 0
T DAR T DDA
T DDH, T DDZ
RD

T DRD

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

ALE Low to RD Low TDAR 3 TCP- - 3 TCP+ nS 1, 2
RD Low to Data Valid TDDA - - 4 TCP nS 1
Data Hold from RD High TDDH 0 - 2 TCP nS
Data Float from RD High TDDZ 0 - 2 TCP nS
RD Pulse Width TDRD 6 TCP- 6 TCP - nS 2

Notes:
1. Data memory access time is 8 TCP.
2. "" (due to buffer driving delay and wire loading) is 20 nS.

Publication Release Date: January 12, 2009

- 31 - Revision A12
 W78E365/W78E365A

8.3 Data Write Cycle

S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3
XTAL1

ALE

PSEN

PORT 2 A8-A15

PORT 0 A0-A7 DATA OUT

TDAD T DWD
WR

T DAW T DWR

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

ALE Low to WR Low TDAW 3 TCP- - 3 TCP+ nS

Data Valid to WR Low TDAD 1 TCP- - - nS

Data Hold from WR High TDWD 1 TCP- - - nS

WR Pulse Width TDWR 6 TCP- 6 TCP - nS

Note: "" (due to buffer driving delay and wire loading) is 20 nS.

Publication Release Date: January 12, 2009

- 32 - Revision A11
 W78E365/W78E365A

8.4 Port Access Cycle

S5 S6 S1

XTAL1

ALE
TPDS TPDH T PDA

PORT DATA OUT

INPUT
SAMPLE

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Port Input Setup to ALE Low TPDS 1 TCP - - nS
Port Input Hold from ALE Low TPDH 0 - - nS
Port Output to ALE TPDA 1 TCP - - nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.

Publication Release Date: January 12, 2009

- 33 - Revision A12
 W78E365/W78E365A

9. TYPICAL APPLICATION CIRCUIT

9.1 External Program Memory and Crystal

V DD
31 P0.0 39 AD0 AD0 3 D0 Q0 2 A0 A0 10 11 AD0
EA A0 O0
P0.1 38 AD1 AD1 4 D1 Q1 5 A1 A1 9 A1 O1 12 AD1
19 XTAL1 P0.2 37 AD2 AD2 7 D2 Q2 6 A2 A2 8 A2 O2 13 AD2
10 u P0.3 36 AD3 AD3 8 D3 Q3 9 A3 A3 7 A3 O3 15 AD3
P0.4 35 AD4 AD4 13 D4 Q4 12 A4 A4 6 A4 O4 16 AD4
R 18 34 AD5 14 15 A5 A5 17
XTAL2 P0.5 AD5 D5 Q5 5 A5 O5 AD5
CRYSTAL P0.6 33 AD6 AD6 17 D6 Q6 16 A6 A6 4 A6 O6 18 AD6
P0.7 32 AD7 AD7 18 D7 Q7 19 A7 A7 3 A7 O7 19 AD7
8.2 K 9 RST A8 25
21 GND 1 A8
P2.0 A8 OC A9 24
C1 C2 A9
P2.1 22 A9 11 G A10 21 A10
12 INT0 23 A10 A11 23
P2.2 A11
13 INT1 P2.3 24 A11 A12 2
74LS373 A12
14 T0 P2.4 25 A12 A13 26 A13
15 T1 P2.5 26 A13 A14 27 A14
P2.6 27 A14 A15 1 A15
1 P1.0 P2.7 28 A15
2 P1.1 GND 20 CE
3 P1.2 RD 17 22
P1.3 16 OE
4 WR
5 P1.4 29 27512
P1.5 PSEN 30
6 ALE
7 P1.6 11
TXD
8 P1.7 10
RXD

W78E365/W78E365A

Figure A

CRYSTAL C1 C2 R
6 MHz 47P 47P -
16 MHz 30P 30P -
24 MHz 15P 15P -
32 MHz 10P 10P 6.8K
40 MHz 5P 5P 4.7K

Above table shows the reference values for crystal applications.

Notes:
1. C1, C2, R components refer to Figure A
2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.
Typical Application Circuit, continued

Publication Release Date: January 12, 2009

- 34 - Revision A11
 W78E365/W78E365A

9.2 Expanded External Data Memory and Oscillator

VDD

V DD
31 P0.0 39 AD0 AD0 3 D0 Q0 2 A0 A0 10 A0 D0 11 AD0
EA P0.1 38 AD1 AD1 4 5 A1 A1 9 12 AD1
D1 Q1 A1 D1
19 P0.2 37 AD2 AD2 7 D2 Q2 6 A2 A2 8 A2 D2 13 AD2
XTAL1
10 u OSCILLATOR P0.3 36 AD3 AD3 8 D3 Q3 9 A3 A3 7 A3 D3 15 AD3
P0.4 35 AD4 AD4 13 D4 Q4 12 A4 A4 6 A4 D4 16 AD4
18 XTAL2 P0.5 34 AD5 AD5 14 D5 Q5 15 A5 A5 5 A5 D5 17 AD5
P0.6 33 AD6 AD6 17 D6 Q6 16 A6 A6 4 A6 D6 18 AD6
P0.7 32 AD7 AD7 18 D7 Q7 19 A7 A7 3 A7 D7 19 AD7
8.2 K 9 25
RST A8 A8
P2.0 21 A8 GND 1 OC A9 24 A9
P2.1 22 A9 11 G A10 21 A10
12 INT0 P2.2 23 A10 A11 23 A11
13 INT1 P2.3 24 A11 74LS373 A12 2 A12
14 P2.4 25 A12 A13 26 A13
T0
15 P2.5 26 A13 A14 1
T1 A14
P2.6 27 A14
1 P1.0 P2.7 28 GND 20 CE
2 P1.1 22 OE
3 RD 17 27
P1.2 WR
4 P1.3 WR 16
5 P1.4 29 20256
6 PSEN 30
P1.5 ALE
7 P1.6 11
8 TXD
P1.7 RXD 10

W78E365/W78E365A

Figure B

Publication Release Date: January 12, 2009

- 35 - Revision A12
 W78E365/W78E365A

10. PACKAGE DIMENSIONS

10.1 40-pin DIP

Dimension in inch Dimension in mm

Symbol
Min. Nom. Max. Min. Nom. Max.
A 0.210 5.334

A1 0.010 0.254

A2 0.150 0.155 0.160 3.81 3.937 4.064

B 0.016 0.018 0.022 0.406 0.457 0.559

B1 0.048 0.050 0.054 1.219 1.27 1.372

c 0.008 0.010 0.014 0.203 0.254 0.356

D
D 2.055 2.070 52.20 52.58
40 21
E 0.590 0.600 0.610 14.986 15.24 15.494

E1 0.540 0.545 0.550 13.72 13.84 13.97

e1 0.090 0.100 0.110 2.286 2.54 2.794

E1 L 0.120 0.130 0.140 3.048 3.302 3.556

a 0 15 0 15

eA 0.630 0.650 0.670 16.00 16.51 17.01

1 20
S 0.090 2.286

Notes:
E 1. Dimens ion D Max. & S inc lude mold flas h or
S
c tie bar burrs .
A A2
2. Dimens ion E1 does not inc lude interlead flas h.
A1 Base Plane
3. Dimens ion D & E 1 inc lude mold mis matc h and
are determined at the mold . parting line.
L Seating Plane
4. Dimens ion B1 does not inc lude dambar
protrus ion/intrusion.
B
e1 eA 5. Controlling dimens ion: Inc hes .
a
B1
6. General appearanc e s pec . s hould be bas ed on
final vis ual ins pec tion s pec .

10.2 44-pin PLCC

HD
D

6 1 44 40
Dimension in inch Dimension in mm
Symbol Min. Nom. Max. Min. Nom. Max.
7 39
A 0.185 4.699

A1 0.020 0.508

A2 0.145 0.150 0.155 3.683 3.81 3.937

b1 0.026 0.028 0.032 0.66 0.711 0.813

b 0.016 0.018 0.022 0.406 0.457 0.559

E HE GE
c 0.008 0.010 0.014 0.203 0.254 0.356

D 0.648 0.653 0.658 16.46 16.59 16.71

E 0.648 0.653 0.658 16.46 16.59 16.71

e 0.050 BSC 1.27 BSC
17 29 GD 0.590 0.610 0.630 14.99 15.49 16.00

GE 0.590 0.610 0.630 14.99 15.49 16.00

18 28
c
HD 0.680 0.690 0.700 17.27 17.53 17.78

HE 0.680 0.690 0.700 17.27 17.53 17.78

L 0.090 0.100 0.110 2.296 2.54 2.794

y 0.004 0.10
L
A2 A Notes:
1. Dimension D & E do not include interlead
flash.

2. Dimension b1 does not include dambar
e b A1 protrusion/intrusion.
Seating Plane b1 y 3. Controlling dimension: Inches
4. General appearance spec. should be based
GD on final visual inspection spec.

Publication Release Date: January 12, 2009

- 36 - Revision A11
 W78E365/W78E365A

10.3 44-pin PQFP

HD
D Dimens ion in inc h Dimens ion in mm
Symbol
44 34
Min. Nom. Max. Min. Nom. Max.
A --- --- --- --- --- ---

A1 0.002 0.01 0.02 0.05 0.25 0.5

A2 0.075 0.081 0.087 1.90 2.05 2.20

1 33
b 0.01 0.014 0.018 0.25 0.35 0.45

c 0.004 0.006 0.010 0.101 0.152 0.254

D 0.390 0.394 0.398 9.9 10.00 10.1

E HE E 0.390 0.394 0.398 9.9 10.00 10.1

e 0.025 0.031 0.036 0.635 0.80 0.952

HD 0.510 0.520 0.530 12.95 13.2 13.45

11
HE 0.510 0.520 0.530 12.95 13.2 13.45

L 0.025 0.031 0.037 0.65 0.8 0.95

L1 0.051 0.063 0.075 1.295 1.6 1.905

y 0.003 0.08
12 e b
22
 0 7 0 7

Notes:
1. Dimension D & E do not include interlead
c flash.
2. Dimension b does not include dambar
A2 A protrusion/intrusion.
3. Controlling dimension: Millimeter

A1 4. General appearance spec. should be based
See Detail F y L
Seating Plane on final visual inspection spec.
L1 Detail F

Publication Release Date: January 12, 2009

- 37 - Revision A12
 W78E365/W78E365A

10.4 48-pin LQFP

Publication Release Date: January 12, 2009

- 38 - Revision A11
 W78E365/W78E365A

11. APPLICATION NOTE

11.1 In-system Programming Software Examples
This application note illustrates the in-system programmability of the Nuvoton W78E365 ROM
microcontroller. In this example, microcontroller will boot from 64KB APROM bank and waiting for a
key to enter in-system programming mode for re-programming the contents of 64KB APROM. While
entering in-system programming mode, microcontroller executes the loader program in 4KB LDROM
bank. The loader program erases the 64KB APROM then reads the new code data from external
SRAM buffer (or through other interfaces) to update the 64KB APROM.

Example 1:
;*******************************************************************************************************************
;* Example of 64K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system
;* programming mode for updating the content of APROM code else executes the current ROM code.
;* XTAL = 16 MHz
;*******************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols

CHPCON EQU BFH

CHPENR EQU F6H
SFRAL EQU C4H
SFRAH EQU C5H
SFRFD EQU C6H
SFRCN EQU C7H

ORG 0H
LJMP 100H ; JUMP TO MAIN PROGRAM
;************************************************************************
;* TIMER0 SERVICE VECTOR ORG = 000BH
;************************************************************************
ORG 00BH
CLR TR0 ; TR0 = 0, STOP TIMER0
MOV TL0, R6
MOV TH0, R7
RETI
;************************************************************************
;* 64K APROM MAIN PROGRAM
;************************************************************************
ORG 100H

MAIN_64K:
MOV A,P1 ; SCAN P1.0
ANL A, #01H
CJNE A, #01H,PROGRAM_64K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE
JMP NORMAL_MODE

PROGRAM_64K:
MOV CHPENR, #87H ; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE
MOV CHPENR, #59H ; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE
MOV CHPCON, #03H ; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE
MOV TCON, #00H ; TR = 0 TIMER0 STOP

Publication Release Date: January 12, 2009

- 39 - Revision A12
 W78E365/W78E365A

MOV IP, #00H ; IP = 00H

MOV IE, #82H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE
MOV R6, #F0H ; TL0 = F0H
MOV R7, #FFH ; TH0 = FFH
MOV TL0, R6
MOV TH0, R7
MOV TMOD, #01H ; TMOD = 01H, SET TIMER0 A 16-BIT TIMER
MOV TCON, #10H ; TCON = 10H, TR0 = 1,GO
MOV PCON, #01H ; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM
; PROGRAMMING
;********************************************************************************
;* Normal mode 64KB APROM program: depending user's application
;********************************************************************************
NORMAL_MODE:
. ; User's application program
.
.
.

Example 2:
;******************************************************************************************************************************
Example of 4 KB LDROM program: This loader program will erase the 64KB APROM first, then reads the new ;*
code from external SRAM and program them into 32 KB APROM bank. XTAL = 16 MHz
;*****************************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols

CHPCON EQU BFH

CHPENR EQU F6H
SFRAL EQU C4H
SFRAH EQU C5H
SFRFD EQU C6H
SFRCN EQU C7H

ORG 000H
LJMP 100H ; JUMP TO MAIN PROGRAM
;************************************************************************
;* 1. TIMER0 SERVICE VECTOR ORG = 0BH
;************************************************************************
ORG 000BH
CLR TR0 ; TR0 = 0, STOP TIMER0
MOV TL0, R6
MOV TH0, R7
RETI

Publication Release Date: January 12, 2009

- 40 - Revision A11
 W78E365/W78E365A

;************************************************************************
;* 4KB LDROM MAIN PROGRAM
;************************************************************************
ORG 100H
MAIN_4K:
MOV SP, #C0H
MOV CHPENR, #87H ; CHPENR = 87H, CHPCON WRITE ENABLE.
MOV CHPENR, #59H ; CHPENR = 59H, CHPCON WRITE ENABLE.
MOV CHPCON, #03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING.
MOV CHPENR, #00H ; DISABLE CHPCON WRITE ATTRIBUTE

MOV TCON, #00H ; TCON = 00H, TR = 0 TIMER0 STOP

MOV TMOD, #01H ; TMOD = 01H, SET TIMER0 A 16BIT TIMER
MOV IP, #00H ; IP = 00H
MOV IE, #82H ; IE = 82H, TIMER0 INTERRUPT ENABLED
MOV R6, #F0H
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO
MOV PCON, #01H ; ENTER IDLE MODE

UPDATE_64K:
MOV TCON, #00H ; TCON = 00H, TR = 0 TIM0 STOP
MOV IP, #00H ; IP = 00H
MOV IE, #82H ; IE = 82H, TIMER0 INTERRUPT ENABLED
MOV TMOD, #01H ; TMOD = 01H, MODE1
MOV R6, #E0H ; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS. DEPENDING
; ON USER'S SYSTEM CLOCK RATE.
MOV R7, #B1H
MOV TL0, R6
MOV TH0, R7

ERASE_P_4K:
MOV SFRCN, #22H ; SFRCN(C7H) = 22H ERASE 64K
MOV TCON, #10H ; TCON = 10H, TR0 = 1,GO
MOV PCON, #01H ; ENTER IDLE MODE (FOR ERASE OPERATION)

;*********************************************************************
;* BLANK CHECK
;*********************************************************************
MOV SFRCN, #0H ; READ 64KB APROM MODE
MOV SFRAH, #0H ; START ADDRESS = 0H
MOV SFRAL, #0H
MOV R6, #FEH ; SET TIMER FOR READ OPERATION, ABOUT 1.5 S.
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7

BLANK_CHECK_LOOP:
SETB TR0 ; ENABLE TIMER 0
MOV PCON, #01H ; ENTER IDLE MODE
MOV A, SFRFD ; READ ONE BYTE
CJNE A, #FFH, BLANK_CHECK_ERROR
INC SFRAL ; NEXT ADDRESS
MOV A, SFRAL

Publication Release Date: January 12, 2009

- 41 - Revision A12
 W78E365/W78E365A

JNZ BLANK_CHECK_LOOP
INC SFRAH
MOV A, SFRAH
CJNE A, #80H, BLANK_CHECK_LOOP ; END ADDRESS = 7FFFH
JMP PROGRAM_64KROM

BLANK_CHECK_ERROR:
MOV P1, #F0H
MOV P3, #F0H
JMP $

;*******************************************************************************
;* RE-PROGRAMMING 64KB APROM BANK
;*******************************************************************************
PROGRAM_64KROM:
MOV DPTR, #0H ; THE ADDRESS OF NEW ROM CODE
MOV R2, #00H ; TARGET LOW BYTE ADDRESS
MOV R1, #00H ; TARGET HIGH BYTE ADDRESS
MOV DPTR, #0H ; EXTERNAL SRAM BUFFER ADDRESS
MOV SFRAH, R1 ; SFRAH, TARGET HIGH ADDRESS
MOV SFRCN, #21H ; SFRCN(C7H) = 21 (PROGRAM 64K)
MOV R6, #BEH ; SET TIMER FOR PROGRAMMING, ABOUT 50 S.
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7

PROG_D_64K:
MOV SFRAL, R2 ; SFRAL(C4H) = LOW BYTE ADDRESS
MOVX A, @DPTR ; READ DATA FROM EXTERNAL SRAM BUFFER. BY ACCORDING USER?
; CIRCUIT, USER MUST MODIFY THIS INSTRUCTION TO FETCH CODE
MOV SFRFD, A ; SFRFD(C6H) = DATA IN
MOV TCON, #10H ; TCON = 10H, TR0 = 1,GO
MOV PCON, #01H ; ENTER IDLE MODE (PRORGAMMING)
INC DPTR
INC R2
CJNE R2, #0H, PROG_D_64K
INC R1
MOV SFRAH, R1
CJNE R1, #80H, PROG_D_64K

;*****************************************************************************
; * VERIFY 64KB APROM BANK
;*****************************************************************************
MOV R4, #03H ; ERROR COUNTER
MOV R6, #FEH ; SET TIMER FOR READ VERIFY, ABOUT 1.5 S.
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV DPTR, #0H ; The start address of sample code
MOV R2, #0H ; Target low byte address
MOV R1, #0H ; Target high byte address
MOV SFRAH, R1 ; SFRAH, Target high address
MOV SFRCN, #00H ; SFRCN = 00 (Read ROM CODE)
READ_VERIFY_64K:
MOV SFRAL, R2 ; SFRAL(C4H) = LOW ADDRESS
MOV TCON, #10H ; TCON = 10H, TR0 = 1,GO

Publication Release Date: January 12, 2009

- 42 - Revision A11
 W78E365/W78E365A

MOV PCON, #01H

INC R2
MOVX A, @DPTR
INC DPTR
CJNE A, SFRFD, ERROR_64K
CJNE R2, #0H, READ_VERIFY_64K
INC R1
MOV SFRAH, R1
CJNE R1, #80H, READ_VERIFY_64K

;******************************************************************************
;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU
;******************************************************************************
MOV CHPENR, #87H ; CHPENR = 87H
MOV CHPENR, #59H ; CHPENR = 59H
MOV CHPCON, #83H ; CHPCON = 83H, SOFTWARE RESET.

ERROR_64K:
DJNZ R4, UPDATE_64K ; IF ERROR OCCURS, REPEAT 3 TIMES.
. ; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.
.
.
.

Publication Release Date: January 12, 2009

- 43 - Revision A12
 W78E365/W78E365A

12. REVISION HISTORY

VERSION DATE PAGE DESCRIPTION
A1 May, 2003 - Initial Issued
A2 August, 2004 32 Revise title of 9.1
A3 Sep. 14, 2004 2 Remove P4.4 ~ P4.7
A4 Dec. 23, 2004 2, 15 Add PWM in feature list and modify PWM block diagram
A5 April 20, 2005 41 Add Important Notice
3 Add lead free(RoHS) part number
A6 June 22, 2005
33 Add 32M/40Mhz items in the table
A7 Aug. 25, 2005 3, 5 Add Port 0 pull-up resisters information
A8 Dec 4, 2006 3 Remove all Leaded package parts
3 Add 48-pin LQFP part.
A9 January 10, 2007 4 Add 48-pin LQFP package
37 Add 48-pin LQFP package dimension
A10 April 22, 2008 10 Modified P3 reset state
7 Revise typo
A11 July 15, 2008 Incorrect: AUX-RAM is enable after a reset
Correct: AUX-RAM is disabled after a reset
7 Revise typo, on-chip AUX-RAM is enabled after a reset.
(Ver A11 is incorrect)
A12 January 12, 2009
10 Revise CHPCON initial value from 0xx00000b to
00x11000b.

Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Nuvoton products are not intended for applications wherein failure of Nuvoton
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper
use or sales.

Publication Release Date: January 12, 2009

- 44 - Revision A11