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Answer Key - Set B

The document provides information about an exam for the course "Computer Organization and Architecture" including: - The exam is offline and will take place on August 18, 2023 for 2 periods. It is for second year, third semester students and has 50 multiple choice questions. - The questions cover topics related to computer organization and architecture like binary, hexadecimal, ASCII conversions, binary addition, logic gates, memory organization, instruction execution cycle, and components of the CPU. - Details about the course outcomes and Bloom's taxonomy level coverage of the questions are also included for assessment purposes. The test has been approved by the audit professor/course coordinator.

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0% found this document useful (0 votes)
29 views5 pages

Answer Key - Set B

The document provides information about an exam for the course "Computer Organization and Architecture" including: - The exam is offline and will take place on August 18, 2023 for 2 periods. It is for second year, third semester students and has 50 multiple choice questions. - The questions cover topics related to computer organization and architecture like binary, hexadecimal, ASCII conversions, binary addition, logic gates, memory organization, instruction execution cycle, and components of the CPU. - Details about the course outcomes and Bloom's taxonomy level coverage of the questions are also included for assessment purposes. The test has been approved by the audit professor/course coordinator.

Uploaded by

du vignesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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SRM Institute of Science and Technology

Mode of Exam
College of Engineering and Technology
OFFLINE
School of Computing
(Common to all Branches)
SRM Nagar, Kattankulathur – 603203, Chengalpattu District, Tamilnadu
Academic Year: 23-24/ODD

Test: CLAT-1 Date: 18/08/2023


Course Code & Title: 21CSS201T – Computer Organization and Architecture Duration: 2 periods
Year & Sem: II Yr, III sem SET B Max. Marks: 50 marks

Q. Question
No
1 The given hexadecimal number (1E.53)16 is equivalent to ____________
a) (35.684)8
b) (36.246)8
c) (34.340)8
d) (35.599)8

2 The number of characters that can be represented in ASCII-8 are ______________


a) 128
b) 256
c) 32
d) 64
3 What would be the gray code equal to the number 14?
a. 1000
b. 1110
c. 1111
d. 1001
4 The 2’s complement of binary number 1010 is ___________
a. 0101
b. 1010
c. 0110
d. 1110

The above truth table refers to


a. XNOR
b. NOR
c. XOR
d. NAND

6 ___ is the decimal based equivalent form of binary number 0.0111?


Ans: 0.43750( Option is not given below so give 1 mark)
a. -0.8750
b. 0. 3750
c. 0. 8750
d. 8.750

7 . The sign magnitude representation of -9 is ___________


a)00001001
b)11111001
c)10001001
d) 11001

8 Which of the following is the BCD representation of 357?


a. 0011 0101 0111
b. 1011 0101 0111
c. 0011 0111 0111
a. 0011 0101 1111

9 Consider a CPU that has 64- bit, the address of the contents are 1000, 1008,1016, 1024. Now MAR
is holding an address is 1008 to fetch the content from the memory. Analyze the operation and
select the following address of the content which is held by the Program Counter (PC).
a. 1000
b. 1008
c. 1016
d. 1024

10 If the data “0010” is to be stored in a little-endian machine, it will be stored as


a. 0010
b. 0100
c. 1000
d. 0001

11 Add the following signed binary number


a. 111000
+ 001101
000101

b. 11001100
+ 00010010
11011110

c. 111100001111
+ 001100001101
001000011100

d. 11000011
+ 00011000
11011011

12 Draw the circuit diagram for the following logic expression AB + BC(B + C)
13 Convert the given binary string to gray code
i) 011001=010101
i) 110011=101010
14 Convert decimal (62)10 to Excess-3
10010101

15 List out the drawbacks of single bus structure

The devices connected to a bus vary widely in their speed of operation.


Some devices are relatively slow, such as printer and keyboard.
Some devices are considerably fast, such as optical disks.
Memory and processor units operate are the fastest parts of a computer.

20 Perform the following conversion


(i) (176.35)8 to Binary
001111110.011101
(ii) (1011100011001.01)2 to decimal
5913.5
iii)(7892) 10 to hexadecimal
1ED4
iv) Perform BCD addition on the following numbers 652.21 and 345.12
Addition: 100110010111.00110011

(OR)
b. i) Subtract (23) from (-19) using 2’s complement notation
Ans: 0101010

ii) Find the multiplication of 01101 and 01011?


010001111

iii) Divide 20/4


Q=11
R=00

21 i) Convert decimal (61.81)10 to excess-3.


10010100.11000100
ii) Convert (00110110)2 to Excess-3
01101001
iii) Convert Excess-3 (36) to binary
00000011

(OR)

i) Using the neat diagram, what are the main elements of the operational idea of computer
organization write in detail?
The operational concept of computer organization refers to how a computer system is
designed and structured to perform its tasks efficiently and effectively. It encompasses
various aspects such as the organization of hardware components, memory hierarchy,
instruction execution cycle, and the interaction between different components to execute
programs. Here are the key components of the operational concept of computer
organization:

a. Instruction Execution Cycle: This is the fundamental process by which a computer


executes instructions. It typically involves fetching an instruction from memory,
decoding it to understand the operation to be performed, fetching the operands if
necessary, executing the operation, and storing the result back in memory or a
register.

b. Memory Hierarchy: Computers use a memory hierarchy that includes different types
of memory with varying speeds and capacities. This hierarchy includes registers
(fastest but smallest), cache memory (faster but limited in size), main memory
(slower but larger), and secondary storage (even slower but with much larger
capacity). The memory hierarchy aims to provide a balance between speed and cost.

c. Central Processing Unit (CPU): The CPU is the heart of the computer and is
responsible for executing instructions. It contains the Arithmetic Logic Unit (ALU)
for performing arithmetic and logical operations, and the Control Unit (CU) for
managing the execution of instructions and coordinating data movement within the
system.

d. Instruction Set Architecture (ISA): The ISA defines the set of instructions that a
computer can execute. It includes the instruction format, addressing modes, data
types, and operations supported by the CPU. The ISA serves as an interface between
software and hardware.

e. Pipelining and Parallelism: To improve performance, modern CPUs often use


pipelining and various forms of parallelism. Pipelining divides the instruction
execution cycle into stages, allowing multiple instructions to be processed
concurrently at different stages. Parallelism involves executing multiple instructions
simultaneously to increase overall throughput.

f. Input/Output (I/O) Operations: Computers interact with the outside world through
input and output operations. These operations involve transferring data between the
computer's internal memory and external devices such as keyboards, displays,
storage devices, and network interfaces.

g. Interrupts and Exception Handling: Interrupts are signals that interrupt the normal
execution of a program to handle external events, such as hardware device requests
or errors. Exception handling involves managing unexpected events, errors, and
exceptional conditions during program execution.

h. Bus Architecture: Computers use a bus system to facilitate communication between


various components, including the CPU, memory, and I/O devices. The bus
connects these components and allows them to exchange data and control signals.

i. Clock and Synchronization: The computer's clock generates regular electrical pulses
that synchronize the operations of various components. The clock speed influences
the computer's overall performance, as it determines how many instructions can be
executed in a given time frame.

j. Micro-architecture: Also known as the internal architecture or organization, micro-


architecture refers to the specific design implementation of a CPU or other hardware
component. It includes details about how instructions are executed, data paths,
control signals, and pipeline stages.

*Performance Indicators are available separately for Computer Science and Engineering in AICTE examination
reforms policy.

Course Outcome (CO) and Bloom’s level (BL) Coverage in Questions

Approved by the Audit Professor/Course Coordinator

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