® PCM

171
8
® PCM1718E

Stereo Audio TM

DIGITAL-TO-ANALOG CONVERTER

FEATURES DESCRIPTION
● ACCEPTS 16- or 18-BIT I2S, OR 18-BIT The PCM1718 is a complete low cost stereo, audio
NORMAL INPUT DATA digital-to-analog converter, including digital interpo-
● COMPLETE STEREO DAC: lation filter, 3rd-order delta-sigma DAC, and analog
8X Oversampling Digital Filter output amplifiers. PCM1718 is fabricated on a highly
Multi-Level Delta-Sigma DAC advanced 0.6µ CMOS process. PCM1718 accepts 18-
Analog Low Pass Filter bit normal input data format, or 16- or 18-bit I2S data
Output Amplifier format.
● HIGH PERFORMANCE: The digital filter performs an 8X interpolation func-
–90dB THD+N tion, as well as special functions such as soft mute and
96dB Dynamic Range digital de-emphasis.
100dB SNR PCM1718 is suitable for a wide variety of cost-sensitive
● SYSTEM CLOCK: 256fs or 384fs consumer applications where good performance is re-
quired. Its low cost, small size, and single power supply
● WIDE POWER SUPPLY: +2.7V to +5.5V
make it ideal for BS tuners, keyboards, MPEG audio,
● SELECTABLE FUNCTIONS: PCMCIA audio cards (ZV port), MIDI applications,
Soft Mute and set-top boxes.
Digital De-emphasis
● SMALL 20-PIN SSOP PACKAGE

Output Amp
BCKIN Multi-level VOUTL
and
Serial Delta-Sigma DAC
Low-pass
LRCIN Input Modulator D/C_L
8X Oversampling Filter
I/F
DIN Digital Filter with
Multi Function
Control Output Amp
Multi-level VOUTR
and
Delta-Sigma DAC
MUTE Low-pass
Mode Modulator D/C_R
Filter
DM0 Control
I/F
DM1 ZERO

FORMAT
Open Drain
RSTB Reset

Clock/OSC Manager Power Supply

XTI XTO CLKO VCC AGND VDD DGND

InternationalAirportIndustrialPark • MailingAddress:POBox11400,Tucson,AZ85734 • StreetAddress:6730S.TucsonBlvd.,Tucson,AZ 85706 • Tel:(520)746-1111 • Twx:910-952-1111

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© 1996 Burr-Brown Corporation 1

PDS-1325A PCM1718E
Printed in U.S.A. June, 1996

SBAS050
SPECIFICATIONS
All specifications at +25°C, +VCC = +VDD = +5V, fs = 44.1kHz, and 18-bit input data, SYSCLK = 384fs, unless otherwise noted. Measurement bandwidth is 20kHz.

PCM1718E
PARAMETER CONDITIONS MIN TYP MAX UNITS

RESOLUTION 16 18 Bits
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Input Logic Level:
VIH(2) 70% of VDD V
VIL(2) 30% of VDD V
VIH(3) 70% of VDD V
VIL(3) 30% of VDD V
VIH(4) 64% of VDD V
VIL(4) 28% of VDD V
Input Logic Current:
IIH(5) –6.0 µA
IIL(5) –120 µA
IIH(6) –2 µA
IIL(6) 0.02 µA
IIH(4) VIN = 3.2V 40 µA
IIL(4) VIN = 1.4V –40 µA
Output Logic Level: (+VDD = +5V)
VOH(7) IOH = –5mA 3.8 V
VOL(7) IOL = +5mA 1.0 V
VOL(8) IOL = +5mA 1.0 V
Interface Format Selectable Normal, I2S
Data Format 16/18 Bits MSB First Binary Two’s Complement
Sampling Frequency 32 44.1 48 kHz
System Clock Frequency 256fs/384fs 8.192/12.288 11.2896/16.9344 12.288/18.432 MHz
DC ACCURACY
Gain Error ±1.0 ±5.0 % of FSR
Gain Mismatch Channel-to-Channel ±1.0 ±5.0 % of FSR
Bipolar Zero Error VO = 1/2 VCC at Bipolar Zero ±30 mV
DYNAMIC PERFORMANCE(1) VCC = +5V, f = 991Hz
THD+N at FS (0dB) –90 –80 dB
THD+N at –60dB –34 dB
Dynamic Range EIAJ, A-weighted 90 96 dB
Signal-To-Noise Ratio EIAJ, A-weighted 92 100 dB
Channel Separation 90 97 dB
Level Linearity Error (–90dB) ±0.5 dB
DYNAMIC PERFORMANCE(1) VCC = +3V, f = 991Hz
THD+N at FS (0dB) –86 dB
Dynamic Range EIAJ, A-weighted 91 dB
Signal-To-Noise Ratio EIAJ, A-weighted 94 dB
DIGITAL FILTER PERFORMANCE
Pass Band Ripple ±0.17 dB
Stop Band Attenuation –35 dB
Pass Band 0.445 fs
Stop Band 0.555 fs
De-emphasis Error (fs = 32kHz ~ 48kHz) –0.2 +0.55 dB
Delay Time (Latency) 11.125/fs sec
ANALOG OUTPUT
Voltage Range FS (0dB) OUT 62% of VCC Vp-p
Load Impedance 5 kΩ
Center Voltage 50% of VCC V
POWER SUPPLY REQUIREMENTS
Voltage Range: +VCC +2.7 +5.5 VDC
+VDD +2.7 +5.5 VDC
Supply Current: +ICC +IDD(9) +VCC = +VDD = +5V 18.0 25.0 mA
+VCC = +VDD = +3V 9.0 15.0 mA
Power Dissipation +VCC = +VDD = +5V 90 125 mW
+VCC = +VDD = +3V 27 45 mW
TEMPERATURE RANGE
Operation –25 +85 °C
Storage –55 +100 °C

NOTES: (1) Tested with Shibasoku #725 THD. Meter 400Hz HPF, 30kHz LPF On, Average Mode with 20kHz bandwidth limiting. (2) Pins 4, 5, 6, 14: LRCIN, DIN,
BCKIN, FORMAT. (3) Pins 15, 16, 17, 18: RSTB, DM0, DM1, MUTE (Schmitt trigger input). (4) Pin 1: XTI. (5) Pins 15, 16, 17, 18: RSTB, DM0, DM1, MUTE (if
pull-up resistor is used). (6) Pins 4, 5, 6: LRCIN, DIN, BCKIN (if pull-up resistor is not used). (7) Pin 19: CLKO. (8) Pin 7: ZERO. (9) No load on pins 19 (CLKO)
and 20 (XTO).

PCM1718E 2
PIN CONFIGURATION PIN ASSIGNMENTS
TOP VIEW SSOP PIN NAME FUNCTION
Data Input Interface Pins
4 LRCIN Sample Rate Clock Input. Controls the update rate (fs).
XTI 1 20 XTO
5 DIN Serial Data Input. MSB first, right justified (Sony format,
DGND 2 19 CLKO 18 bits) or I2S (Philips format, 16 or 18 bits).
6 BCKIN Bit Clock Input. Clocks in the data present on DIN input.
VDD 3 18 MUTE
Mode Control and Clock Signals
LRCIN 4 17 DM1
1 XTI Oscillator Input (External Clock Input). For an internal
DIN 5 16 DM0 clock, tie XTI to one side of the crystal oscillator. For an
external clock, tie XTI to the output of the chosen
BCKIN 6 15 RSTB external clock.
14(1) FORMAT A “HIGH” selects I2S input data format, and a “LOW”
ZERO 7 14 FORMAT
selects Normal (Sony) input data format.
D/C_R 8 13 DC_L 16(1) DM0 De-emphasis selection.
17(1) DM1 De-emphasis selection.
VOUTR 9 12 VOUTL
18(1) MUTE Soft Mute Control. When set “LOW”, the outputs are
AGND 10 11 VCC muted.
19 CLKO Buffered Output of Oscillator. Equivalent to XTI.
20 XTO Oscillator Output. When using the internal clock, tie to
the opposite side (from pin 1) of the crystal oscillator.
When using an external clock, leave XTO open.
Operational Controls and Flags
PACKAGE INFORMATION 7 ZERO Infinite Zero Detection Flag, open drain output. When
the input is continuously zero for 65,536 cycles of
PACKAGE DRAWING
BCKIN, ZERO is “LOW”.
PRODUCT PACKAGE NUMBER(1)
15(1) RSTB Resets DAC operation with an active “LOW” pulse.
PCM1718E 20-Pin SSOP 334-1
Analog Output Functions
NOTE: (1) For detailed drawing and dimension table, please see end of data 8 D/C_R Right Channel Output Amplifier Common. Bypass to
sheet, or Appendix C of Burr-Brown IC Data Book. ground with 10µF capacitor.
9 VOUTR Right Channel Analog Output. VOUT max = 0.62 x VCC.
12 VOUTL Left Channel Analog Output. VOUT max = 0.62 x VCC.
ABSOLUTE MAXIMUM RATINGS 13 D/C_L Left Channel Output Amplifier Common. Bypass to
ground with 10µF capacitor.
Power Supply Voltage ....................................................................... +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V Power Supply Connections
Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V) 2 DGND Digital Ground.
Power Dissipation .......................................................................... 200mW
3 VDD Digital Power Supply (+5V or +3V).
Operating Temperature Range ......................................... –25°C to +85°C
Storge Temperature ........................................................ –55°C to +125°C 10 AGND Analog Ground.
Lead Temperature (soldering, 5s) .................................................. +260°C 11 VCC Analog Power Supply (+5V or +3V).
Thermal Resistance, θJA ....................................................................................... +70°C/W
NOTE: (1) With internal pull-up.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

3 PCM1718E
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = +5V, RL = 100Ω, CL = 2pF, and RFB = 402Ω, unless otherwise noted.
DYNAMIC PERFORMANCE

THD+N vs VCC, VDD DYNAMIC RANGE vs INPUT DATA

fIN = 1kHz, 384fs fIN = 1kHz
–84 –30 100

–86 98 256fs

THD+N at –60dB (dB)

Dynamic Range (dB)

–60dB
THD+N at FS (dB)

–88 –34 96
384fs

–90 94

–92 –38 92
0dB

–94 90
3.5 4.0 4.5 5.0 5.5 6.0 16-Bit 18-Bit
VCC, VDD (V) Input Data

THD+N vs TEMPERATURE THD+N vs INPUT DATA

fIN = 1kHz, 384fs fIN = 1kHz, FS (0dB)
–84 –30 –84

–86 –86
THD+N at –60dB (dB)
THD+N at FS (dB)

THD+N (dB)

–88 –34 –88

–60dB
384fs
–90 –90

–92 –38 –92

0dB 256fs
–90 –94
–25 0 25 50 75 85 100 16-Bit 18-Bit
Temperature (°C) Input Data

DYNAMIC RANGE AND SNR vs VCC, VDD

fIN = 1kHz, 384fs
100

SNR
98

96
(dB)

Dynamic
Range
94

92

90
3.5 4.0 4.5 5.0 5.5 6.0
VCC, VDD

PCM1718E 4
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = +5V, RL = 44.1kHz, fSYS = 384fs, and 18-bit input data, unless otherwise noted.
DIGITAL FILTER

OVERALL FREQUENCY CHARACTERISTIC PASSBAND RIPPLE CHARACTERISTIC

0 0

–20 –0.2

–40 –0.4
dB

dB
–60 –0.6

–80 –0.8

–100 –1
0 0.4536fs 1.3605fs 2.2675fs 3.1745fs 4.0815fs 0 0.1134fs 0.2268fs 0.3402fs 0.4535fs
Frequency (Hz) Frequency (Hz)

DE-EMPHASIS FREQUENCY RESPONSE (32kHz) DE-EMPHASIS ERROR (32kHz)

0 0.6
–2 0.4
Level (dB)

Error (dB)
–4 0.2
–6 0
–8 –0.2
–10 –0.4
–12 –0.6
0 5k 10k 15k 20k 25k 0 3628 7256 10884 14512
Frequency (Hz) Frequency (Hz)

DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) DE-EMPHASIS ERROR (44.1kHz)

0 0.6
–2 0.4
Level (dB)

Error (dB)

–4 0.2
–6 0
–8 –0.2
–10 –0.4
–12 –0.6
0 5k 10k 15k 20k 25k 0 4999.8375 9999.675 14999.5125 19999.35
Frequency (Hz)
Frequency (Hz)

DE-EMPHASIS ERROR (48kHz)

DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
0.6
0
0.4
–2
Error (dB)
Level (dB)

0.2
–4
0
–6
–0.2
–8
–0.4
–10
–0.6
–12 0 5442 10884 16326 21768
0 5k 10k 15k 20k 25k
Frequency (Hz)
Frequency (Hz)

5 PCM1718E
SYSTEM CLOCK ference internally. If the phase difference between left-right
The system clock for PCM1718 must be either 256fs or and system clocks is greater than 6 bit clocks (BCKIN), the
384fs, where fs is the audio sampling frequency (typically synchronization is performed internally. While the synchro-
32kHz, 44.1kHz, or 48kHz). The system clock is used to nization is processing, the analog output is forced to a DC
operate the digital filter and the modulator. level at bipolar zero. The synchronization typically occurs in
less than 1 cycle of LRCIN.
The system clock can be either a crystal oscillator placed
between XTI (pin 1) and XTO (pin 20), or an external clock
input to XTI. If an external system clock is used, XTO is DATA INTERFACE FORMATS
open (floating). Figure 1 illustrates the typical system clock Digital audio data is interfaced to PCM1718 on pins 4, 5,
connections. and 6—LRCIN (left-right clock), DIN (data input) and
PCM1718 has a system clock detection circuit which auto- BCKIN (bit clock). PCM1718 can accept both normal and
matically senses if the system clock is operating at 256fs or I2S data formats. Normal data format is MSB first, two’s
384fs. The system clock should be synchronized with LRCIN complement, right-justified. I2S data is compatible with
(pin 4) clock. LRCIN (left-right clock) operates at the Philips serial data protocol. Figures 3 and 4 illustrate the
sampling frequency fs. In the event these clocks are not input data formats.
synchronized, PCM1718 can compensate for the phase dif-

CLKO CLKO

Internal System Clock Internal System Clock

C1
X’tal XTI XTI
External Clock

C2

XTO XTO

C1, C2 = typ 22pF

PCM1718E PCM1718E
CRYSTAL RESONATOR CONNECTION EXTERNAL CLOCK INPUT
XTO pin = No Connection

FIGURE 1. Internal Clock Circuit Diagram and Oscillator Connection.

FUNCTIONAL CONTROLS
tXTIH 1/256fs or 1/384fs
PCM1718 allows the user to control the input data format,
64% OF VDD soft mute, and digital de-emphasis frequency. Table I illus-
28% OF VDD trates the selectable functions:
tXTIL FUNCTION CONTROL PIN

Data Input Format FORMAT (Pin 14)

Normal
External System Clock High tXTIH 10ns (min)
I2S
External System Clock Low tXTIL 10ns (min)
De-emphasis DM0, DM1 (Pins 16, 17)
32kHz
FIGURE 2. External Clock Timing Requirements. 44.1kHz
48kHz
Soft Mute MUTE (Pin 18)
Reset RSTB (Pin 15)

TABLE I. Selectable Functions.

PCM1718E 6
 1 f/s

Left-channel Data Right-channel Data

LRCIN (pin 4)

BCKIN (pin 6)

Audio Data Word = 18-Bit MSB LSB MSB LSB

DIN (pin 5) 16 17 18 1 2 3 16 17 18 1 2 3 16 17 18

FIGURE 3. “Normal” Data Input Timing.

1 f/s

Left-channel Data Right-channel Data

LRCIN (pin 4)

BCKIN (pin 6)

Audio Data Word = 16-Bit MSB LSB MSB LSB

DIN (pin 5) 1 2 3 14 15 16 1 2 3 14 15 16 1 2

Audio Data Word = 18-Bit MSB LSB MSB LSB

DIN (pin 5) 1 2 3 16 17 18 1 2 3 16 17 18 1 2

FIGURE 4. “I2S” Data Input Timing.

Data Format
A “HIGH” on pin 14 (FORMAT) sets the input format to
LRCIN 50% of VDD I2S, and a “LOW” sets the format to Normal (MSB-first,
right-justified Sony format).
tBCH tBCL tLB

50% of VDD Soft Mute

BCKIN
tBL A “LOW” on pin 18 (MUTE) causes both outputs to be
tBCY
muted. This muting is done in the digital domain so there is
DIN 50% of VDD no audible “click” when the soft mute is enacted.

tDH tDS
De-Emphasis
BCKIN Pulsewidth (High Level) tBCH 50ns (min) PCM1718 allows for digital de-emphasis for all three stan-
BCKIN Pulsewidth (Low Level) tBCL 50ns (min) dard sampling frequencies:
BCKIN Pulse Cycle Time tBCY 100ns (min)
BCKIN Rising Edge ➝ LRCIN Edge tBL 30ns (min)
LRCIN Edge ➝ BCKIN Rising Edge tLB 30ns (min) DM1 (Pin 17) DM0 (Pin 16) De-Emphasis Mode
DIN Setup Time tDS 30ns (min) 0 0 OFF
DIN Hold Time tDH 30ns (min) 0 1 48kHz
1 0 44.1kHz
FIGURE 5. Data Input Timing. 1 1 32kHz

7 PCM1718E
Reset
PCM1718 has both internal power on reset circuit and the For the RSTB-pin, PSTB-pin accepts external forced reset by
RSTB-pin (pin 15) which accepts external forced reset by RSTB = L. During RSTB = L, the output of the DAC is
RSTB = LOW. For internal power on reset, initialize (reset) invalid and the analog outputs are forced to VCC/2 after
is done automatically at power on VDD >2.2V (typ). During internal initialize (1024 system clocks count after RSTB = H.)
internal reset = LOW, the output of the DAC is invalid and Figure 7 illustrates the timing of RSTB-pin reset.
the analog outputs are forced to VCC/2. Figure 6 illustrates
the timing of internal power on reset.

2.6V
VCC/VDD 2.2V
1.8V

Reset
Reset Removal
Internal Reset

1024 system (= XTI) clocks

XTI Clock

FIGURE 6. Internal Power-On Reset Timing.

RSTB-pin
50% of VDD
tRST(1)
Reset
Reset Removal
Internal Reset

1024 system (XTI) clocks

XTI Clock
NOTE: (1) tRST = 20ns min

FIGURE 7. RSTB-Pin Reset Timing.

0.1µF ~ 10µF
Bypass Capacitor
+5V or +3 Analog Power Supply

2 3
10pF ~ 22pF DGND VDD FOUT = Inverted XTI (1 pin)
1 XTI CLKO 19
to Other System

20 XTO
10pF ~ 22pF
Post
VOUTR 9 Low Pass
Filter
4 LRCIN D/C_R 8
PCM + (optional)
Audio Data 5 DIN 10µF
Processor
6 BCKIN

10µF
+ Post
Format Control Low Pass
14 FORMAT D/C_L 13
VDD Filter
18 MUTE VOUTL 12 (optional)

17 DM1 4.7kΩ
16 DM0 ZERO 7 To External Mute Circuit

15 RSTB
AGND VCC
Reset
10 11

0.1µF ~ 10µF
Bypass Capacitor

FIGURE 8. Typical Connection Diagram of PCM1718.

®

PCM1718E 8
POWER SUPPLY
CONNECTIONS
PCM1718 has two power supply connections: digital (VDD) A block diagram of the 5-level delta-sigma modulator is
and analog (VCC). Each connection also has a separate shown in Figure 10. This 5-level delta-sigma modulator has
ground. If the power supplies turn on at different times, there the advantage of stability and clock jitter sensitivity over the
is a possibility of a latch-up condition. To avoid this condi- typical one-bit (2 level) delta-sigma modulator.
tion, it is recommended to have a common connection The combined oversampling rate of the delta-sigma modu-
between the digital and analog power supplies. If separate lator and the internal 8-times interpolation filter is 48fs for
supplies are used without a common connection, the delta a 384fs system clock, and 64fs for a 256fs system clock. The
between the two supplies during ramp-up time must be less theoretical quantization noise performance of the 5-level
than 0.6V. delta-sigma modulator is shown in Figure 11.
An application circuit to avoid a latch-up condition is shown
in Figure 9.

Digital Analog
Power Supply Power Supply

VDD VCC

DGND AGND 3rd-ORDER ∆Σ MODULATOR

20

FIGURE 9. Latch-up Prevention Circuit. –20

–40
Gain (–dB)

BYPASSING POWER SUPPLIES –60

The power supplies should be bypassed as close as possible –80

to the unit. Refer to Figure 8 for optimal values of bypass –100
capacitors. –120

–140

THEORY OF OPERATION –160

0 5 10 15 20 25
The delta-sigma section of PCM1718 is based on a 5-level Frequency (kHz)
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level delta-
sigma format. FIGURE 11. Quantization Noise Spectrum.

+ + +
+ + +
In Z–1 Z–1 Z–1
8fs – –
18-Bit

+
+ +

5-level Quantizer
4
3
Out 2
48fs (384fs)
1
64fs (256fs)
0

FIGURE 10. 5-Level ∆Σ Modulator Block Diagram.

®

9 PCM1718E
APPLICATION
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
CONSIDERATIONS (20Hz~24kHz, Expanded Scale)
1.0
DELAY TIME
There is a finite delay time in delta-sigma converters. In A/D
converters, this is commonly referred to as latency. For a 0.5
delta-sigma D/A converter, delay time is determined by the
order number of the FIR filter stage, and the chosen sampling

dB
0
rate. The following equation expresses the delay time of
PCM1718:
TD = 11.125 x 1/fs –0.5

For fs = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs –1.0

20 100 1k 10k 24k
Applications using data from a disc or tape source, such as
Frequency (Hz)
CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time. For some profes-
sional applications such as broadcast audio for studios, it is FIGURE 12. Low Pass Filter Frequency Response.
important for total delay time to be less than 2ms.

OUTPUT FILTERING INTERNAL ANALOG FILTER FREQUENCY RESPONSE

(10Hz~10MHz)
For testing purposes all dynamic tests are done on the 10
PCM1718 using a 20kHz low pass filter. This filter limits 5
0
the measured bandwidth for THD+N, etc. to 20kHz. Failure –5
to use such a filter will result in higher THD+N and lower –10
SNR and Dynamic Range readings than are found in the –15
–20
specifications. The low pass filter removes out of band
dB

–25
noise. Although it is not audible, it may affect dynamic –30
specification numbers. –35
–40
The performance of the internal low pass filter from DC to –45
24kHz is shown in Figure 12. The higher frequency rolloff –50
–55
of the filter is shown in Figure 13. If the user’s application –60
has the PCM1718 driving a wideband amplifier, it is recom- 10 100 1k 10k 100k 1M 10M
mended to use an external low pass filter. A simple 3rd- Frequency (Hz)
order filter is shown in Figure 14. For some applications, a
passive RC filter or 2nd-order filter may be adequate. FIGURE 13. Low Pass Filter Frequency Response.

GAIN vs FREQUENCY
6 90

Gain
–14 0

1500pF –34 –90

Gain (dB)

OPA604
Phase (°)

+
10kΩ 10kΩ 10kΩ –54 –180
VSIN 680pF 100pF Phase
–
–74 –270

–94 –360
100 1k 10k 100k 1M
Frequency (Hz)

FIGURE 14. 3rd-Order LPF.

PCM1718E 10
 Test Disk Shibasoku #725
Through
Lch

CD DEM- THD
DAI PGA
Player Digital PCM1718 Meter
11th-order
LPF
Rch
0dB/60dB 30KHz LPF on
For test of S/N ratio and Dynamic Range, A-filter ON.

FIGURE 15. Test Block Diagram.

TEST CONDITIONS
Figure 15 illustrates the actual test conditions applied to 110

PCM1718 in production. The 11th-order filter is necessary 105

in the production environment for the removal of noise 100

Dynamic Range (dB)

Multi-level
resulting from the relatively long physical distance between 95
the unit and the test analyzer. In most actual applications, the 90
3rd-order filter shown in Figure 14 is adequate. Under 85
normal conditions, THD+N typical performance is –70dB 80
with a 30kHz low pass filter (shown here on the THD 75 PWM
meter), improving to –89dB when the external 20kHz 11th- 70
order filter is used. For cost-sensitive applications, a single 65
RC filter, as shown in Figure 18, may be adequate. 60
0 100 200 300 400 500 600
Clock Jitter (ps)
EVALUATION FIXTURES
DEM-PCM1718 FIGURE 16. Simulation Results of Clock Jitter Sensitivity.
This evaluation fixture is primarily intended for quick evalu-
ation of the PCM1718’s performance. DEM-PCM1718 can
accept either an external clock or a user-installed crystal
2
oscillator. All of the functions can be controlled by on-board
switches. DEM-PCM1718 does not contain a receiver chip
1
or an external low pass filter. DEM-PCM1718 requires a
single +2.7V to +5V power supply. 14.4ps
0

OUT-OF-BAND NOISE CONSIDERATIONS

–1
Delta-sigma DACs are by nature very sensitive to jitter on 48fs
the master clock. Phase noise on the clock will result in an 2
increase in noise, ultimately degrading dynamic range. It is
difficult to quantify the effect of jitter due to problems in
synthesizing low levels of jitter. One of the reasons delta- FIGURE 17. Simulation Method for Clock Jitter.
sigma DACs are prone to jitter sensitivity is the large
quantization noise when the modulator can only achieve two
discrete output levels (0 or 1). The multi-level delta-sigma
DAC has improved theoretical SNR because of multiple PCM1718 Output
output states. This reduces sensitivity to jitter. Figure 16 1kΩ
contrasts jitter sensitivity between a one-bit PWM type DAC 1800pF
and multi-level delta-sigma DAC. The data was derived
using a simulator, where clock jitter could be completely fC = 88kHz
synthesized.

FIGURE 18. RC Output Filter.

11 PCM1718E
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

PCM1718E ACTIVE SSOP DB 20 65 RoHS & Green NIPDAU Level-1-260C-UNLIM PCM1718E

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
PCM1718E DB SSOP 20 65 500 10.6 500 9.6

Pack Materials-Page 1
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