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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Table of Contents
44th DAC Call For Papers ........................................................................................64-65 Keynote Addresses
Additional Conference and Hotel Information........................................inside back cover • Monday Keynote Address ................................................................................6
• Conference Shuttle Bus Service • Tuesday Keynote Address................................................................................7
• First Aid Rooms • Thursday Keynote Address..............................................................................8
• Guest/Family Program MEGa Sessions..............................................................................................................5
• Hotel Locations Monday Schedule ........................................................................................................13
• On-Site Information Desk Monday Tutorial Descriptions ..................................................................................42
• San Francisco Attractions New Exhibitors ............................................................................................................4
• Weather Panel Committee ........................................................................................................67
• Wednesday Night Party Pavilion Panels ..............................................................................................................9-12
Additional Meetings ....................................................................................................61-63 Proceedings ..................................................................................................................56
Awards............................................................................................................................57-59 Registration Hours ......................................................................................................2
Birds-of-a-Feather ........................................................................................................63 SIGDA Ph.D Forum/Member Meeting....................................................................62
Conference Floorplan ................................................................................................71 Sponsor Information ..................................................................................................54-56
DACnet-2006 ..............................................................................................................2 Student Design Contest ............................................................................................57, 60
DAC Pavilion ................................................................................................................9-12 Student Design Contest Judges ................................................................................68
DAC Thanks ................................................................................................................153 Technical Program Committee ................................................................................66-67
Executive Committee ................................................................................................69 Technical Program Highlights....................................................................................3
Exhibit Floorplan ..........................................................................................................72 Technical Sessions........................................................................................................20-41
Exhibit Highlights..........................................................................................................4 Thursday Schedule ......................................................................................................16
Exhibit Hours ................................................................................................................2 Tuesday Schedule ........................................................................................................14
Exhibit-Only Registration ..........................................................................................4 Topics and Related Sessions ....................................................................................18
Exhibitor Company Descriptions ............................................................................78-165 Wednesday Schedule ..................................................................................................15
Exhibitor Liaison Committee ..................................................................................68 Week in Review ..........................................................................................................2
Exhibitor Listing............................................................................................................75-76
Workshops
Exhibitor Supplemental Listing..................................................................................151-153
• Introduction to EDA Workshop..............................................................49
General Chair’s Welcome ........................................................................................inside front cover
• Second Integrated Design Systems Workshop ....................................47
General Keynote Address ........................................................................................7
• UML for SoC Workshop ..........................................................................46
General Session ............................................................................................................19
• Workshop for Women in Design Automation....................................48
Hands-On Tutorials ....................................................................................................50-53
Important Information at a Glance..........................................................................2
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Important Information At-A-Glance

Exhibit Hours Tutorial Registration Friday, July 28, 7:00 am to 6:00 pm
Monday, July 24 ................................9:00 am to 6:00 pm Tutorial registration is located in the Esplanade Lobby in the South Hall.
Tuesday, July 25 ................................9:00 am to 6:00 pm DACnet-2006
Wednesday, July 26 ..........................9:00 am to 6:00 pm
DACnet stations are located in the Esplanade Lobby in the South Hall, and in the Concourse
Thursday, July 27 ..............................9:00 am to 1:00 pm
Hallway between the North and South Halls.
Registration Hours
The registration desk is located in the North Lobby of The Moscone Center,
and is open during the following hours:
Sunday, July 23..................................8:30 am to 6:00 pm
Monday, July 24 ................................7:00 am to 6:00 pm
Tuesday, July 25................................7:00 am to 6:00 pm
Wednesday, July 26 ..........................7:00 am to 6:00 pm
Thursday, July 27 ..............................7:00 am to 6:00 pm

The 43rd Design Automation Conference Week in Review

Sunday, July 23 Monday, July 24 Tuesday, July 25 Wednesday, July 26 Thursday, July 27 Friday, July 28

• UML for SoC Design • FREE Monday Exhibits • General Session • Technical Sessions • Keynote Address • Full-Day Tutorials
Workshop • Keynote Address • Keynote Address • MEGa Theme • Best Paper Awards
• Full-Day Tutorials • Technical Sessions • Pavilion Panels • Technical Sessions
• Pavilion Panels • Management Day • Hands-on Tutorials • Pavilion Panels
• Hands-on Tutorials • Pavilion Panels • Exhibits • Hands-on Tutorials
• Workshops • Hands-on Tutorial • DAC Party (AT&T Ballpark) • Exhibits
• Exhibit Floor Happy • Exhibits
Hour (5:00 pm - 6:00 pm) • SIGDA Ph.D. Forum

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Technical Program Highlights

This year DAC is celebrating its 43rd year with a technical program that includes nearly 200 Tutorials - details on pgs. 17, 42 - 45
papers, panels, tutorials, and keynote presentations covering a wide range of design issues. The
Monday, July 24 • 9:00 am - 5:00 pm
program covers sessions in eleven topic areas: Business, System Level and Embedded, MEGa,
Low Power and Power, Analog and Circuit Interconnect, Reliability and DFM, Verification and 1) Practical Aspects of Coping with Variability: An Electrical View
Test, Synthesis and FPGA, Physical Design, Beyond the Die, and New and Emerging 2) ESL Design Methodology Using SystemC
Technologies.
Friday, July 28 • 9:00 am - 5:00 pm
In each of these areas the sessions will cover aspects of both design methodology and design
tools. The themed sessions for the 43rd DAC focus on multimedia, entertainment and games. 3) Real DFM Solutions, Tools Methodologies and Successes
The theme is woven into the keynote addresses, technical sessions and panels, and pavilion 4) Surviving and Thriving in the World of Chip and Package Co-Design
panels. Management Day on Tuesday, July 25, includes sessions and functions discussing topics 5) SystemVerilog: Language Tutorial and Industrial Verification Experience
at the intersection of technology and business for design management.
6) Tools for Hybrid Embedded Systems: Modeling, Verification, and Design
Hands-on Tutorials - details on pgs. 50 - 53 7) From Basic to Advanced Techniques for Silicon Debug and Diagnosis
Hands-on Tutorials are three-hour tutorials presented by exhibitors to demonstrate their
solutions to issues in Low Power Design. MONDAY KEYNOTE - details on pg. 6
Management Day - details on pgs. 5, 7, 19, 20, 23, 25
Monday, July 24 - 2:00 pm Gateway Ballroom
DAC has dedicated a full day of keynotes, panels and special presentations by experts on
business topics that affect technology decisions and directions. Management Day includes:
Joe Costello - Chairman of the Board, Orb Networks, Inc.
General Session Keynote Address GENERAL SESSION AND KEYNOTE - details on pgs. 7, 19
Session 1: PANEL: How Will the Fabless Model Survive Tuesday, July 25 - 8:30 am Gateway Ballroom
EDA Business Forum Luncheon
Session 100: Decision-Making for Complex SoCs in Consumer Electronic Products Hans Stork - Senior Vice President and Chief Technology Officer, Director of Silicon
Session 150: Tradeoffs and Choices for Emerging SoCs in High-End Applications Technology Department, Texas Instruments Inc.

MEGa (Multimedia, Entertainment, and Games) - details on pg. 5 THURSDAY KEYNOTE - details on pg. 8
The themed sessions for the 43rd DAC focus on multimedia, entertainment and games. The Thursday, July 27 - 12:45 pm Gateway Ballroom
theme is woven into the keynote addresses, technical sessions and panels, and pavilion panels. Alessandro Cremonesi - Strategy and System Technology Group
These sessions will highlight CAD challenges for multimedia designs, and look at next Vice-President and Advanced System Technology
generation MEGa designs and power constraints of consumer devices. General Manager, STMicroelectronics
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Exhibitor Highlights
Exhibit Floor New Exhibitors at DAC
Monday – Wednesday, July 24-26, 9:00 am – 6:00 pm DAC has always been the best place to see the industry’s newest companies, and this year is
Thursday, July 27, 9:00 am – 1:00 pm no exception. With over 50 new exhibitors, DAC is the place to be to find out what the hot
The 43rd DAC Exhibition is located in the North (Booths 3000-4367) and in the South (Booths 101- startups are up to. Among the companies participating in DAC for the first time are:
2323) Halls of The Moscone Center
Advanced Circuit Engineers, LLC Lynguent, Inc.
The DAC Exhibit floor is bursting with over 240 vendors offering products for all phases of Algotronix Ltd. Magwel NV
the electronic design process including EDA tools, IP cores, embedded system and system- Altos Design Automation Malico Inc.
level tools, silicon vendors, and a host of new design-for-manufacturing companies. The DAC ArchPro Design Automation Inc. MunEDA-ChipMD
show floor features its unique exhibit booth and private suite combination, which gives you Barth Electronics, Inc. National Instruments Corp.
Catalytic Inc. NSCore, Inc.
the freedom to deeply explore the products on the show floor and find a solution that is right CebaTech, Inc. Oasis Tooling, Inc.
for your design. Visit the DAC exhibition and find out how you can improve performance and Certess Inc. OneSpin Solutions GmbH
shorten the time-to-market on your next product.. Certicom Corp. Perfectus Technology Inc.
Exhibitor Listing ................................................Pages 75 - 76 Coupling Wave Solutions Polyscale Computing Inc.
Exhibiting Company Descriptions ................Pages 78 - 165 Fenix Design Automation B.V. Rio Design Automation Inc.
Formal Sciences Inc. Semifore, Inc.
Hands-on Tutorials ..........................................Pages 50 - 53 Fortelink Inc. Silistix, Inc.
Children under the age of 14 will NOT be allowed in the exhibit hall. Helic S.A. SimPlus Verification
Imperas, Inc. Solido Design Automation Inc.
Exhibits-Only Registration INFINISCALE Space Codesign
• Free Monday Exhibits-Only Passes - Attend the exhibition free of charge Monday, July 24. Ingot Systems SynCira Corp.
• $60 Exhibits-Only registration will allow you to attend exhibits Monday through Thursday. Innovative Silicon Inc. Takumi Technology Corp.
Institution of Engineering and TurboTools Corp.
DAC Pavilion Technology (The) Tuscany Design Automation, Inc.
DAC has an exciting line-up of panels and presentations in the DAC Pavilion, booth 2228 on Invarium UniqueICs, LLC
the exhibit floor. The DAC Pavilion sessions are open to all attendees at no charge and feature Liga Systems, Inc. Uniquify
18 provocative technical, business and strategy discussions. See pages 9-12 for details. Lizotech, Inc. Western Scientific, Inc.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Management Day/MEGa Sessions

Management Day - Tuesday, July 25 MEGa Sessions: Multimedia, Entertainment, and Games
DAC’s Management Day is where the technology and the business of IC and system design
intersect. This full day of sessions is designed for managers and executives of semiconductor, For 2006, the 43rd DAC is presenting MEGa Sessions: the design challenges and design
technology requirements for creating advanced multimedia, entertainment, and game (MEGa)
communications and consumer electronics companies. Participants meet, interact with, and
products. The MEGa theme is woven into all three keynote addresses and is a full-track of
learn from peers who are facing the issues of how to make the right business and technology
decisions in the dynamic world of electronic design. The Management Day $75 registration sessions on Wednesday, July 26th. The presentations include a special session highlighting
selected papers from ISSCC in the multimedia area, with presentations from
fee includes the 11th Annual EDA Business Forum luncheon, and the wrap-up cocktail party.
Renesas/DoCoMo, MediaTek, National Chiao-Tung University, and Samsung, and continues
Minimum Conference Registration required: Exhibits Only
with two complementary events: an invited session on CAD challenges for leading-edge
Management Day Sessions include: multimedia designs, followed by a panel on design challenges for next generation multimedia,
General Session Keynote Address - Gateway Ballroom • 8:30 am - 10:15 am entertainment, and game platforms. These two sessions include experts from
STMicroelectronics, IBM, nVidia, PixelWorks, Qualcomm, and Intel. The sessions conclude
Structuring Process and Design for Future Mobile Communication Devices with four papers on power-constrained design for multimedia.
Hans Stork - Senior Vice President and Chief Technology Officer,
Texas Instruments Inc. Complementing the MEGa sessions will be Pavilion Panels, taking place throughout the week
on the exhibit floor. These include presentations on Inside the iPod, technology requirements
Session 1: PANEL: - Rm: 306/308 • 10:30 am - 12:00 pm for 3D graphics in feature films, and a discussion on the Xbox 360 and getting chips into high-
How Will the Fabless Model Survive? volume products.
Chair: Don Clark - Wall Street Journal All full-conference attendees are invited to attend the MEGa technical sessions, and all
EDA Business Forum Luncheon - Rm: 124/125 - 12:00 pm - 1:00 pm registrants are invited to attend the DAC Pavilion sessions in Booth 2228 on the exhibit floor.
Management Day Session 100 - Rm: 301 - 2:00 pm - 4:00 pm
Decision-Making for Complex SoCs in Consumer Electronic Products
Chair: Ron Wilson - EDN
100.1 Qualcomm: Lessons Learned at the 65nm Node
100.2 Low Power Challenges in Wireless ICs
100.3 Consumer Electronics Development Tradeoffs in the High-Tech Startup
100.4 Architecture Planning Criteria for a System-in-a-Package
Portable Multimedia Platform
Management Day Session 150 - Rm: 301 - 4:30 pm - 6:30 pm
Tradeoffs and Choices for Emerging SoCs in High-End Applications
Chair: Nic Mokhoff - EE Times, Manhasset, NY
150.1 Assessing Process Nodes and IP for SoC Development
150.2 Open-IP: How Your Selection of IP Drives Your ASIC Success
150.3 Yield, Manufacturability and Test: The Criteria to Judge the Right Design Investment
Cocktail Reception - Rm: 302 - 6:00 pm - 6:30 pm 5
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Monday Keynote 2:00 pm • Gateway Ballroom

iPod or Iridium - Which One Are You Going To Be?

Joe Costello
Chairman of the Board, Orb Networks, Inc.

Abstract: An incredible amount of time, resources and investment is being made by Biography: Joe Costello is chairman, co-founder, and an investor in Orb
EDA, chip, and electronics companies to win in the exploding multi-media, gaming, and Networks, Inc. He is highly regarded for his business acumen and bold moves in the
entertainment applications markets. With the 2006 DAC conference doing a much- high-tech industry. In 1997, Chief Executive Magazine named Costello the top
needed "deep dive" into how the semiconductor industry meets technical challenges, performing CEO of all publicly traded companies in North America. He also made
Joe Costello, Chairman of Orb Networks, Inc., will turn the spotlight away from Upside Magazine’s 1997 “Elite 100” list of the top executives leading the digital
technology and onto today's macro consumer trends. revolution. He serves as CEO and chairman of think3, a developer of computer-aided
design software used throughout the product development process. He is also
During this session, Joe challenges participants with this fundamental question: are chairman of other privately-held companies that include Readio, Abazab and
you going in the right direction? As you bend your minds with the complexity of SpeakESL. In addition, Costello is on the board of Mercury Interactive, a publicly-held
implementing modern day systems and chips, are you racing toward the right company. Prior to think3, Costello played a pivotal role as president and CEO at
finish line? What are consumers really looking for? What will convergence really Cadence Design Systems, Inc. for more than a decade. Under his leadership, Cadence
lead to and are you positioned to take advantage of all it will bring our industry became the world’s leading supplier of electronic EDA software and services, and one
and our world? Join Joe as he reveals lessons learned and offers a simple view of of the ten highest-grossing software vendors in the world. Costello holds a bachelor
the future of electronics. of science degree in mathematics and physics from Harvey Mudd College, a master of
science degree in physics from Yale University, and a master of science degree in
physics from the University of California, Berkeley.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

8:30 am • Gateway Ballroom Tuesday Keynote

Structuring Process and Design for Future Mobile Communication Devices
Hans Stork
Senior Vice President and Chief Technology Officer, Director of Silicon Technology Department,
Texas Instruments Inc.

Abstract: The density and speed of sub-50nm CMOS technology enables the design Dr. Stork has written or co-authored approximately 90 papers and holds five patents.
of multi-functional SoCs for highly integrated, mobile communication devices. At the He was elected IEEE Fellow in 1994 for his contributions to SiGe devices and
same time, process variations, power issues, and complexity of scope are challenging technology. He is a fellow member of the IEEE Electron Devices Society, where he has
even the most advanced simulation capabilities. The growing design complexity is served on and chaired a number of committees. Dr. Stork joined the Sematech board
addressed by rapidly improving modeling of systematic manufacturing variations and of directors in 2002 after several years service on the organization’s Executive
design sensitivities. Physical design is becoming more structured to allow for process Technical Advisory Board, has been a board member of the Semiconductor Research
optimized design rules and efficient automation. While challenges remain in the scaling Corporation since 1999, and serves on the Semiconductor Industry Association’s (SIA)
and optimization of analog and I/O functions, highly integrated, mobile communication Technology Strategy Committee. Additionally, he served as a technical advisor to
devices are a major driving force for continued economies of scaling. government efforts on high-performance computing benchmarks and the national
security issues emerging from Internet computing. Born in Soest, The Netherlands, Dr.
Biography: With a doctorate from Stanford University, Dr. Stork joined TI in 2001 Stork received the Ingenieur degree in electrical engineering from Delft University of
from Hewlett-Packard, where he served as Director of the Internet Systems and Technology, Delft, The Netherlands.
Storage Lab at HP Laboratories, and earlier as the Director of the ULSI Research Lab.
He began his professional career at IBM's T.J. Watson Research Center, where he
researched advanced bipolar technology and circuits, and later SiGe (silicon germanium)
technology, finally assuming responsibility for the Exploratory Device and Technology
programs at IBM Research.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Thursday Keynote 12:45 pm • Gateway Ballroom

The Challenges of Convergence

Alessandro Cremonesi
Strategy and System Technology Group Vice-President and Advanced System Technology General Manager,
STMicroelectronics

Abstract: In this talk, the trends of the major application fields in the era of Biography: Alessandro Cremonesi received a Doctorate in Electronics Engineering
convergence are analyzed. The emphasis is on the challenges the semiconductor from the University of Pavia, Italy, in 1984. After a period of research activity in the
industry will have to face to address these new trends and opportunities. opto-electronics field at the University of Pavia, he joined STMicroelectronics working
in different fields from telecommunications to audio/video digital signal processing and
Applications are becoming increasingly complex and the need to guarantee the multimedia applications. At present, Alessandro Cremonesi is V.P. of Strategy and
coexistence of a wider range of applications on a single chip makes system-level System Technology Group and General Manager of Advanced System Technology
integration a real challenge. Most of the applications will run on platforms designed for (AST) Group at STMicroelectronics with the responsibility of the Corporate System
portable products, pushing the industry to emphasize power budgets for new designs, R&D and the Corporate Strategic Marketing activities across 14 different
both at silicon and at system level. From the platform architecture perspective, STMicroelectronics Labs worldwide.
multiprocessing is already a reality, and the industry will have to find new paradigms to
handle the increased complexity at the system, embedded software, and at the silicon
implementation levels.
The talk concludes with future perspectives from the viewpoint of ST's advanced
research organization.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

DAC Pavilion Panels – Booth# 2228

DAC has an exciting line-up of panels and presentations in the DAC Pavilion (Booth 2228) Monday, July 24 • 3:00 pm - 4:00 pm Track: MEGa
on the exhibit floor. The DAC Pavilion sessions are open to all attendees and feature Inside the iPod
provocative technical, business, and strategy discussions. Moderator: Aurangzeb Khan - Cadence Design Systems, Inc., San Jose, CA
Monday, July 24 • 9:30 am - 10:30 am Track: Business Panelist: Chris Crotty - iSuppli Corp., El Segundo, CA
Dataquest at DAC with Gary Smith: EDA Trends and What's Hot at DAC The iPod energized the personal audio player market, becoming the latest in "must-have"
Moderator: Shishpal Rawat - Intel Corp., Folsom, CA consumer products. Apple's strategy includes quickly bringing new products to market,
Panelist: Gary Smith - Gartner Dataquest, San Jose, CA addressing multiple price points and form factors tailored for different market segments,
A retrospective of the ever popular annual Sunday Gartner Dataquest EDA and while creating an optimized supply-chain. The iPod is a brilliant combination of off-the-shelf
semiconductor industry presentation followed by a review of the hot products at DAC for parts, ASICs, and IP. This panel gives attendees a unique perspective into the electronics
2006 and a Q&A . product value chain behind Apple's number one selling product.
Monday, July 24 • 11:00 am - 12:00 pm Track: Business Monday, July 24 • 4:15 pm - 5:15 pm Track: Business
What Will it Take to Break the $4B Revenue Cap? Mass Book Signing
Moderator: Kathryn Kranen - Jasper Design Automation, Inc., Mountain View, CA Moderator: Lee Wood - MP Associates, Inc., Boulder, CO
Panelists: Lucio Lanza - Lanza techVentures, Palo Alto, CA Authors of popular electronic design or design automation books in 2006 are invited to
Nick Pappas - Canaccord Adams, San Francisco, CA participate in a book signing session in the DAC Pavilion. The session is designed to give
Jim Hogan - Private Investor, Santa Cruz, CA attendees the opportunity to meet the authors and have copies signed of popular technical
Today's design teams are facing challenges 10x greater than just 18 months ago. Can EDA books published in 2005/2006. Publishers of the invited authors' books will be available with
keep up, or has it become the limiting factor for chip design? Some believe ESL and DFM have copies for sale.
the potential to drive future growth beyond the $4B revenue cap into double digits. This
panel will discuss and debate the emergence of new tools and technologies, business
partnerships and business models to explore what the future holds for the EDA industry.
Monday, July 24 • 1:00 pm - 2:00 pm Track: Business
Ask the CTO
Moderator: Kurt Keutzer - Univ. of California, Berkeley, CA
Panelists: Raul Camposano - Synopsys, Inc., Mountain View, CA
Ted Vucurevich - Cadence Design Systems, Inc., San Jose, CA
Continuing in the tradition of the popular "Ask the CTO" panels, this year's group will answer
your toughest questions about your critical SoC design challenges. This year we will expand
the focus to examine what's driving these design issues (and solutions), including leading-edge
consumer gaming and multimedia, traditionally some of the most demanding applications. 9
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

DAC Pavilion Panels – Booth# 2228

Tuesday, July 25 • 10:15 am - 11:00 am Track: Verification & Test Tuesday, July 25 • 1:00 pm - 1:45 pm Track: Business
The Do's and Don'ts of Verification Exporting in the Hallway
Moderator: Alan Hu - Univ. of British Columbia, Vancouver, BC, Canada Moderator: Walden C. Rhines - Mentor Graphics Corp., Wilsonville, OR
Panelists: Hillel Miller - Freescale Semiconductor, Inc., Herzlia Pituach, Israel Panelists: Larry Disenhof - Cadence Design Systems, Inc., Chelmsford, MA
Narendra Konda - NVIDIA Corp., San Jose, CA Douge Martin - Mentor Graphics Corp., Wilsonville, OR
Mike Beaver - Transmeta Corp., Santa Clara, CA Erik Oliver - Rambus, Los Altos, CA
The pain of verification is relentless. Companies designing increasingly complex SoCs are When you employ a "non-US person" in the US, and allow them access to your software or your customer's
spending considerable time and applying more and more resources to tackle the IP, you are effectively exporting this technology to their country of citizenship. Have you just broken a law?
Pending proposals in Washington may restrict exports to China – will this affect the industry? As companies
challenges of verification. Today, many companies still rely heavily upon simulation to
broaden their global sales and operations, they need to stay abreast of coming changes in export regulations.
address their functional verification needs, yet most would agree that simulation alone is
Working through the EDA Consortium, this panel's team members have successfully rewritten US and
simply not enough. Promising new hardware methods are proliferating -- acceleration, international export regulations, easing these regulations as they affect the industry. The panelists will
emulation and FPGA prototyping -- and there is growing usage of formal techniques. provide the latest news from Washington -- what you don't know “can” hurt you. Organized by EDAC.
How do you decide what to use, and when? This panel brings together a few experts in
verification to examine how to get the most out of your verification environment. Tuesday, July 25 • 2:00 pm - 2:45 pm Track: Business
Verification veterans will discuss what they are doing that works and what doesn't. Learn Shattering the Glass Ceiling: A Decade of Growth for Women
what leading edge companies are doing to resolve the verification challenge. Moderator: Peggy Aycinena - EDA Confidential, San Mateo, CA
Panelists: Mary Jane Irwin - Pennsylvania State Univ., University Park, PA
Tuesday, July 25 • 11:30 am - 12:15 pm Track: Business Jan Willis - Cadence Design Systems, Inc., San Jose, CA
Design Team Collaboration: Tools Challenge or Ellen J. Yoffa - IBM Research, Hawthorne, NY
Organization Responsibility (Winner 2006 Marie R. Pistilli Women in EDA Achievement Award)
Moderator: Penny Herscher - firstRain, Foster City, CA The Workshop for Women in Design Automation is celebrating 11 years. Are women in the electronics
Panelists: Marty Deneroff - DE Shaw Research & Dev., New York, NY industry better off? What strategies do today's women leaders use to break through the 'glass ceiling'? This
Prasad Subramanian - eSilicon Corp., Murray Hill, NJ panel will interview three of today's most successful women for their business acumen and insights into
Taguchi Hirofumi - Matsushita Electric Industrial Co., Ltd., Kyoto, Japan where women will go next in the next decade.
Expanding system chip complexity is driving increasing specialization. Multi- Tuesday, July 25 • 4:00 pm - 4:45 pm Track: Interconnect Reliability & DFM
site/multinational design teams are rapidly becoming the norm for 90 and 65nm SoC The Fabless Model: Is DFM Our Salvation or Demise?
design. Systems designers, chip integrators, RTL designers, layout engineers, and Moderator: Dennis Wassung - Canaccord Adams, Boston, MA
verification engineers are feeling the pressure to synchronize development efforts across Panelists: Walter Ng - Chartered Semiconductor Manufacturing, Inc., Milpitas, CA
these multidiscipline groups. How should existing design practices evolve? Matt Nowak - Qualcomm, San Diego, CA
Thomas Blaesi - SIGMA-C Software AG, Santa Clara, CA
At 90nm and below, iterations put the quest for timely, reasonable yields in peril. Despite urgent need for
exchange of critical information, fabs and fabless companies still struggle to overcome obstacles preventing that
exchange. So who controls the yield – fabs or fabless companies? Panelists will examine enablers for critical
10 data exchange between the two and if EDA can bring salvation.
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

DAC Pavilion Panels – Booth# 2228

Wednesday, July 26 • 10:00 am - 10:45 am Wednesday, July 26 • 2:15 pm - 3:15 pm Track: System Level & Embedded
Student Design Contest Award Presentations ESL: Software Engineers Are from Pluto and Hardware
Moderators: Alan Mantooth - Univ. of Arkansas, Fayetteville, AR Engineers Are from Mercury: Can ESL Bridge the Gap?
Bill Bowhill - IBM Corp., Hudson, MA Moderator: John Blyler - ChipDesign Magazine, Portland, OR
Presentation of winners of the Student Design Contest, organized by the Design Automation Panelists: Maurizio Vitale - Philips Semiconductors, Pittsburgh, PA
Conference and the International Solid State Circuits Conference (ISSCC). Michael Uhner - MIPS Technologies, Inc., Mountain View, CA
Kazu-Yoshi Kikuta - D-Clue Technologies CO. Ltd., Yokohama, Japan
Wednesday, July 26 • 11:15 am - 12:00 pm Track: MEGa
Hardware engineers talk RTL. Software engineers talk C/C++. Communication is not just a
The Xbox 360 Uncloaked: Doing What it Takes to translation problem. Software engineers use system processing, traffic, and storage behavior as
Get Chips into High-Volume Consumer Electronics their development context, while the hardware engineers' context is bit- and nanosecond-
Moderator: Jayaram Bhasker - eSilicon Corp., Allentown, PA accurate implementation. Hardware and software must be co-developed with system design
Panelist: Dean Takahashi - San Jose Mercury News, San Jose, CA
intent as context. So, what do the software guys need from the hardware guys? The panel will
Dean Takahashi, author of "The Xbox 360 Uncloaked," will talk about a case study in the video answer this question in plain English.
game business on how Microsoft designed its newest video game console and what it required
from the chip vendors in order to get the project finished on time. Vendors such as IBM and Wednesday, July 26 • 4:00 pm - 4:45 pm Track: Business
ATI Technologies had to embrace new business models to win Microsoft's business. The Accidental Pirate
Moderator: Sanjay Srivastava - Denali Software, Palo Alto, CA
Wednesday, July 26 • 1:00 pm - 2:00 pm Track: MEGa Panelists: Scott Baeder - Cadence Design Systems, Inc., Chelmsford, MA
AMD/DreamWorks - Fueling Technology Innovation Randy Ohara - Intel Corp., Santa Clara, CA
Moderator: Rich Friedrich - Hewlett-Packard, Palo Alto, CA Lynn Sweetwood - Macrovision, Schramsburg, IL
Panelists: Randy Allen - Advanced Micro Devices, Inc., Austin, TX It is estimated that 36% of the world's software is pirated. With the continuing globalization of
Ed Leonard - DreamWorks Animation SKG, Glendale, CA EDA software usage, IP design reuse, and technology advances that enables a worldwide virtual
With increasing demand to release multiple high-quality 3D computer-generated films every design network, the potential for piracy of software and IP increases. This panel will illicit and
year, you need serious hardware computing power and faster, inherently more complex chips discuss the challenges facing the EDA, IP and design community as it relates to piracy, and talk
to render in record time. Join us for a special presentation by Ed Leonard, Chief Technology about what can be done to address or mitigate the issues raised. Organized by EDAC.
Officer of DreamWorks Animation SKG, and Randy Allen, AMD Corporate Vice President, and
discover what technology innovations are required to fuel their animation needs to deliver one
fantastic adventure after another, year after year.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

DAC Pavilion Panels – Booth# 2228

Thursday, July 27 • 10:00 am - 10:45 am Track: System Level & Embedded Thursday, July 27 • 12:00 pm - 12:45 pm Track: System Level & Embedded
Developing Consumer SoCs - IP and Automation Troubleshooting the Multi-Processor SoC Design Flow
or Sticks and Duct Tape? Moderator: Jim Turley - Embedded Systems Design, Pacific Grove, CA
Moderator: Ed Sperling - Electronic News, San Jose, CA Panelists: Max Domeika - Intel Corp., Hillsboro, OR
Panelists: Kevin Walsh - Synopsys, Inc., Mountain View, CA Grant Martin - Tensilica, Santa Clara, CA
Sanjay Dave - ATI Research, Santa Clara, CA Serge Leef - Mentor Graphics Corp., Wilsonville, OR
Nir Sever - Zoran Microelectronics, Haifa, Israel To create and verify a multi-processor system, designers must move data between cores,
The competing consumer market requirements of: more features, lower cost and earlier to orchestrate shared and local resource allocation, and often implement multiple operating
market make building SoCs for consumer products a daunting task. EDA automation and IP offer systems. With much functionality now implemented in application software, it has become a
the promise of being able to pull together many pre-designed blocks quickly and easily into the critical component in hardware verification. New methodologies are required, but how should
SoC of your dreams. Are you dreaming? Is the challenge the same for startups and established they work? Are IP providers, especially the embedded processor IP companies, best-placed to
companies? The panelists will discuss their experience, good and bad, in assembling SoCs from offer solutions? How can the hardware and software worlds unite to conquer this complex
third party and in-house IP to create innovative, industry-leading consumer products. design problem?
Thursday, July 27 • 11:00 am - 11:45 am Track: Business
Wireless USB - the Next Ubiquitous Connectivity Standard?
Moderator: Jim Lipman - SoC Central and TechOnline, Livermore, CA
Panelists: Joachim Kunkel - Synopsys, Inc., Mountain View, CA
Jon Rosdahl - Samsung Electronics, Highland, UT
Sean Coffey - Realtek Semiconductor Corp., San Francisco, CA
What are the biggest challenges involved in adding wireless connectivity to SoC designs?
Which building blocks need to be available? How does a strong certification/standards group
help to ensure quality end-products? Panelists discuss the Wireless USB ecosystem and what
combination of IP, SoC technology and certification will be needed to make Wireless USB the
next ubiquitous connectivity standard.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Friday, July 28

TUTORIAL 3 - REAL DFM SOLUTIONS – TOOLS, TUTORIAL 6 - TOOLS FOR HYBRID EMBEDDED SYSTEMS:
METHODOLOGIES, AND SUCCESSES Rm: 304 MODELING, VERIFICATION, AND DESIGN Rm: 302
Organizer: Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA Organizer: Luca Carloni - Columbia Univ., New York, NY
Presenters: Nagaraj NS - Texas Instruments Inc., Dallas, TX Presenters: Hilding Elmqvist - Dynasim AB, Lund, Sweden
Jean-Pierre Schoellkopf - STMicroelectronics, Crolles, France George Pappas - Univ. of Pennsylvania, Philadelphia, PA
Mike Smayling - Applied Materials, Sunnyvale, CA Pieter J. Mosterman - The MathWorks, Inc., Natick, MA
Ban P. Wong - Chartered Semiconductor, Milpitas, CA Alessandro Pinto - Univ. of California, Berkeley, CA
Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA Alberto Sangiovanni-Vincentelli - Univ. of California, Berkeley, CA
TUTORIAL 4 - SURVIVING AND THRIVING IN THE WORLD TUTORIAL 7 - FROM BASIC TO ADVANCED TECHNIQUES FOR
OF CHIP AND PACKAGE CO-DESIGN Rm: 305 SILICON DEBUG AND DIAGNOSIS Rm: 306/308
Organizers: Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA Organizer: Srikanth Venkataraman - Intel Corp., Hillsboro, OR
Howard Chen - IBM Corp., Yorktown Heights, NY Presenters: Srikanth Venkataraman - Intel Corp., Hillsboro, OR
Presenters: Paul Harvey - IBM Corp., Austin, TX Miron Abramovici - DAFCA Inc., Framingham, MA
Howard Chen - IBM Corp., Yorktown Heights, NY Robert Aitken - ARM, Sunnyvale, CA
Lei He - Univ. of California, Los Angeles, CA
Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA
Kaushik Sheth - Rio Design Automation, Inc., Santa Clara, CA
TUTORIAL 5 - SYSTEMVERILOG: LANGUAGE TUTORIAL AND
INDUSTRIAL VERIFICATION EXPERIENCE Rm: 307
Organizer: Johny Srouji - IBM Corp., Austin, TX
Presenters: Johny Srouji - IBM Corp., Austin, TX
Karen Pieper - Synopsys, Inc., Sunnyvale, CA
Tom Fitzpatrick - Mentor Graphics Corp., Groton, MA
John Havlicek - Freescale Semiconductor, Inc., Austin, TX
Matt Maidment - Intel Corp., Portland, OR
Cliff Cummings - Sunburst Design, Inc., Portland, OR 17
43rdDAC-2C 7/3/06 9:16 AM Page 18

The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Topics and Related Sessions

Business Verification and Test

Sessions: 1, 6, 100, 150 Sessions: 7, 19, 20, 25, 42, 46, 48, 60, 61

System Level and Embedded Synthesis and FPGA

Sessions: 2, 4, 9, 16, 21, 22, 31, 39, 49, 52 Sessions: 14, 28, 30, 32, 36, 38, 54

MEGa Physical Design

Sessions: 17, 23, 29, 35 Sessions: 18, 24, 43, 62

Low Power and Power Beyond the Die

Sessions: 8, 11, 13, 27, 33, 34, 37, 55 Sessions: 50, 56

Analog and Circuit New and Emerging Technologies

Sessions: 3, 15, 40, 51, 57 Sessions: 41, 47, 53

Interconnect, Reliability and DFM

Sessions: 5, 10, 12, 26, 44, 45, 58, 59

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

General Session/Keynote Address

Tuesday, July 25 • 8:30 am - 10:15 am Gateway Ballroom
Opening Remarks: Ellen Sentovich - General Chair, 43rd DAC
Awards Presented By: Diana Marculescu Alan Mantooth
ACM/SIGDA Representative IEEE/CASS/CANDE Representative
Awards/Scholarships
• Marie R. Pistilli Women in EDA Achievement Award
• P.O. Pistilli Undergraduate Scholarships (ACSEE)
• DAC/ISSCC Student Design Contest - Best Overall Award
• DAC Graduate Scholarships
• ACM/TODAES Best Paper Award
• ACM Distinguished Service Award
• Phil Kaufman Award
• IEEE/CASS Education Award
• IEEE/CASS Industrial Pioneer Award
• IEEE/CASS Donald O. Pederson Award
• IEEE/CASS CSVT Tranactions Best Paper Award
• IEEE/CASS VLSI Transaction Best Paper Award
• 2006 IEEE Fellows
Keynote Address:
Structuring Process and Design for Future Mobile Communication Devices
Hans Stork - Senior Vice President and Chief Technology Officer, Director of Silicon Technology Department, Texas Instruments Inc.

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Tuesday July 25, 2006 All speakers are denoted in bold

S - denotes short paper
ß - denotes best paper candidate
b - session of special interest to designers
- indicates videoed session

SESSION 1 Rm: 306/308 SESSION 2 b Rm: 307 SESSION 3 Rm: 305

PANEL: HOW WILL THE SPECIAL SESSION: HIERARCHICAL SYNTHESIS FOR

FABLESS MODEL SURVIVE? WHY DOESN’T MY SYSTEM WORK? MIXED-SIGNAL DESIGNS
Chair: Don Clark - Wall Street Journal, San Francisco, CA Chair: Bart Vermeulen - Philips Research, Eindhoven, Chair: Gerd Vandersteen - IMEC/VUB, Heverlee, Belgium
Organizer: Riko Radojcic Netherlands Organizers: Geert Van Der Plas, Koen Lampaert
The fabless model was traditionally enabled through clean interfaces Organizer: Erik Jan Marinissen This session describes the application of hierarchical synthesis and
— both in technical and business terms — between foundries and Industry data shows that over 60% of complex chip design projects do optimization techniques to the design of mixed-signal systems. The
fabless semiconductor companies. However, with advanced geometry require one or more respins, and that silicon debug has become the first two papers use hierarchical optimization techniques to design a
and analog/mixed-signal process nodes, the technical challenges have most time-consuming part of the development cycle of a new SoC. In charge pump phase-locked loop and a delta-sigma A/D converter. The
been greatly magnified, so that successful semiconductor design this special session, industry experts discuss the in-system silicon third paper describes new methods to generate yield-aware pareto
requires intimate co-optimization of design and manufacturing, debug problem and emerging solutions for it. The first speaker talks surfaces that link performance tradeoffs and their yield impacts, for
infringing upon those clean interfaces. The panel presents views to from the perspective of a design/debug engineer, with a host of use in hierarchical circuit design.
these challenges and specifically how companies are planning to experience of debugging actual microprocessor products. The second
address them. speaker discusses on-chip design-for-debug hardware required to ß-3.1 A CPPLL Hierarchical Optimization
Panelists: create access to chip-internal signals. The third speaker describes the Methodology Considering Jitter, Power and
software that helps the debug process by visualization and translation Locking Time
Thomas Hartung - X-Fab Semiconductor Foundries AG, Erfurt, Germany
to higher levels. Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann -
Ana Hunter - Samsung Semiconductor Inc., San Jose, CA
Felicia James - Cadence Design Systems, Inc., San Jose, CA 2.1 The Good, the Bad, and the Ugly of Silicon Technische Universitaet Muenchen, Munich, Germany
Mark T. Bohr - Intel Corp., Hillsboro, OR Debug 3.2 Hierarchical Bottom-up Analog Optimization
Brad Paulsen - TSMC NA, San Jose, CA Doug Josephson - Intel Corp., Fort Collins, CO Methodology Validated by a Delta-Sigma A/D
Nick Yu - Qualcomm Inc., San Diego, CA 2.2 A Reconfigurable Design-for-Debug Converter Design for the 802.11a/b/g Standard
Infrastructure for SoCs Tom Eeckelaert, Raf Schoofs, Georges Gielen, Michiel Steyaert,
Miron Abramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Willy Sansen - Katholieke Univ., Heverlee, Belgium
Gerard Memmi, Dave Miller - DAFCA Inc., Framingham, MA 3.3 Generation of Yield-Aware Pareto Surfaces for
2.3 Visibility Enhancement for Silicon Debug Hierarchical Circuit Design Space Exploration
Yu-Chin Hsu, Furshing Tsai, Wells Jong, Ying-Tsai Chang - Saurabh K. Tiwary - Carnegie Mellon Univ., Pittsburgh, PA
Novas Software, Inc., San Jose, CA Pragati K. Tiwary - BIT Mesra, Ranchi, India
Rob A. Rutenbar - Carnegie Mellon Univ., Pittsburgh, PA

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All speakers are denoted in bold

denotes short paper - S Tuesday July 25, 2006
denotes best paper candidate - ß
session of special interest to designers - b
indicates videoed session -

SESSION 4 Rm: 304 SESSION 5 Rm: 303

PROCESSOR AND COMMUNICATION PRACTICAL APPLICATIONS OF DFM

CENTRIC SOC DESIGN Chair: Nagib Hakim - Intel Corp., Santa Clara, CA
Chair: Johannes Stahl - CoWare, Inc., San Jose, CA Organizer: Michael Orshansky
Organizers: Brian Bailey, Rainer Leupers Design for manufacturing is starting the transition from a purely back-
Multi-processor systems-on-chip (MPSoCs) are becoming a necessary end application of resolution enhancement techniques to a rich set of
way to balance performance, power and reliability while maintaining tools and analysis techniques to improve the yield and manufacturability
the maximum degree of flexibility. The first paper proposes the use of of a variety of different integrated circuit components. This session
bus scenarios for an optimized time budget assignment to system shows three interesting applications: SRAM, where the impact of
tasks. The second paper proposes a new approach to implement manufacturing variability is paramount; systematic yield detractors,
custom processor instruction set extensions. The third paper focuses which are often found to be specific layout constructs, and; path delay
on optimization of scratch-pad memory hierarchies for MPSoC variation, which are a major source of timing yield loss.
architectures, while the last paper deals with handling both transient 5.1 Statistical Analysis of SRAM Cell Stability
and permanent faults in a tiled architecture, targeting single program,
multiple data applications. Kanak B. Agarwal, Sani R. Nassif - IBM Corp., Austin, TX
5.2 Criticality Computation in Parameterized
4.1 A Real Time Budgeting Method for Module-Level-
Statistical Timing
Pipelined Bus Based System Using Bus Scenarios
Jinjun Xiong - Univ. of California, Los Angeles, CA
Tadaaki Tanimoto - Renesas Technology Corp., Kodaira Tokyo, Japan
Vladimir Zolotov - IBM Corp., Yorktown Heights, NY
Seiji Yamaguchi, Akio Nakata, Teruo Higashino - Osaka Univ., Suita
Natesan Venkateswaran - IBM Corp., Hopewell Junction, NY
Osaka, Japan
Chandu Visweswariah - IBM Corp., Yorktown Heights, NY
4.2 Exploiting Forwarding to Improve Data
5.3s Mixture Importance Sampling and Its
Bandwidth of Instruction-Set Extensions
Application to the Analysis of SRAM Designs in
Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra - National Univ. of
the Presence of Rare Failure Events
Singapore, Singapore
Rouwaida N. Kanj - IBM Corp., Austin, TX
4.3s Multiprocessor System-on-Chip Data Reuse Analysis Rajiv V. Joshi - IBM Corp., Yorktown Heights, NY
for Exploring Customized Memory Hierarchies Sani R. Nassif - IBM Corp., Austin, TX
Ilya Issenin - Univ. of California, Irvine, CA
5.4s An Up-stream Design Auto-fix Flow for
Erik Brockmeyer, Bart Durinck - IMEC, Leuven, Belgium, Nikil Dutt -
Manufacturability Enhancement
Univ. of California, Irvine, CA
Jie Yang - Advanced Micro Devices, Inc., Sunnyvale, CA
4.4s Modeling a Fault-Tolerant Multiprocessor SoC Ethan Cohen - Advanced Micro Devices, Inc., Austin, TX
with Run-time Fault Recovery Cyrus Tabery, Norma Rodriguez - Advanced Micro Devices, Inc.,
Xinping Zhu - Northeastern Univ., Boston, MA Sunnyvale, CA
Wei Qin - Boston Univ., Boston, MA Mark Craig - Advanced Micro Devices, Inc., Austin, TX 21
43rdDAC-2C 7/3/06 9:16 AM Page 22

Tuesday July 25, 2006 All speakers are denoted in bold

S - denotes short paper
ß - denotes best paper candidate
b - session of special interest to designers
- indicates videoed session

SESSION 6 b Rm: 306/308 SESSION 7 b Rm: 307 SESSION 8 Rm: 305

PANEL: THE IC NANOMETER RACE: SPECIAL SESSION: BRIDGING THE SYSTEM LEAKAGE, POWER ANALYSIS AND OPTIMIZATION
WHAT WILL IT TAKE TO WIN? TO RTL VERIFICATION GAP Chair: Nam Sung Kim - Intel Corp., Hillsboro, OR
Chair: Walden C. Rhines - Mentor Graphics Corp., Chair: Brian Bailey - Verification Consultant, Oregon City, OR Organizers: Naehyuck Chang, Sanu Mathew
Wilsonville, OR Organizer: Anmol Mathur This session covers topics related to leakage power modeling and
Organizer: Laura Parker System-level models in C/C++ or SystemC are gaining widespread optimization, ranging from leakage power analysis in the presence of
Creating ICs in the nanometer age is a high-stakes race that few acceptance for developing golden functional reference models, as variations and the use of charge recycling for MTCMOS circuits, to using
companies can afford to compete in — and even fewer can win. vehicles for micro-architecture exploration and as platforms for sleep transistors and input vector generation for leakage reduction.
Hear how senior technologists from the world’s top technology software development. Transaction-level models are used to 8.1 Charge Recycling in MTCMOS Circuits:
companies are striving to improve their chances of success. Will provide a communication-accurate view of a design that simulates ß-
leakage constraints force power-sensitive applications to stay with 100 to 1000 times faster than RTL. Since the high-level models can Concept and Analysis
older technologies, or will there be a bifurcation to a new process be simulated with real applications, the design team can often get a Ehsan Pakbaznia - Univ. of Southern California, Los Angeles, CA
technology? Will ballooning capital equipment expenses delay new high level of confidence in the functional correctness of this model. Farzan Fallah - Fujitsu Labs. Ltd., Sunnyvale, CA
capacity or price out design rules for mainstream applications? Will Design teams are often spending 30-50% of their overall design cycle Massoud Pedram - Univ. of Southern California, Los Angeles, CA
silicon-on-insulator and new device structures like FinFETs force in this phase to generate the functional reference model and decide 8.2 Projection-Based Statistical Analysis of Full-Chip
rethinking of design, modeling and simulation methodologies? And on the micro-architecture. Leakage Power with Non-Log-Normal Distributions
which EDA technologies, delivered when, will be critical for victory?
These senior technologists, from some of the biggest companies in 7.1 Use of C/C++ Models for Architecture Xin Li, Jiayong Le, Lawrence T. Pileggi - Carnegie Mellon Univ., Pittsburgh, PA
the high tech industry, will discuss and debate how they think the Exploration and Verification of DSPs 8.3s Physical Design Methodology of Power Gating
overall industry will successfully transition to the nanometer age. David Brier - Texas Instruments Inc., Dallas, TX Circuits for Standard-Cell-Based Design
Specific examples from the technologists’ broad exposure to Raj S. Mitra - Texas Instruments Inc., Bangalore, India Hyung-Ock Kim, Youngsoo Shin - KAIST, Daejeon, South Korea
industry trends and competitors will help illustrate their forecasts 7.2 Maintaining Consistency Between SystemC and Hyuk Kim, Iksoo Eo - ETRI, Daejeon, South Korea
and predictions.
RTL System Designs 8.4s Challenges in Sleep Transistor Design and
Panelists:
Christopher Lennard - ARM, Cambridge, UK Implementation in Low-Power Designs
Dennis Buss - Texas Instruments Inc., Dallas, TX Alistair Bruce - ARM, Sheffield, UK Kaijian Shi - Synopsys, Inc., Dallas, TX
Philippe Magarshack - STMicroelectronics, Crolles Cedex, France Andrew Nightingale, Nizar Romdhane - ARM, Cambridge, UK David Howard - ARM Ltd., Cambridge, UK
Fu-Chieh Hsu - Taiwan Semiconductor Mfg. Co., Hsinchu, Taiwan M M Kamal Hashmi, Steve Beavis - Spiratech Ltd., Manchester, UK
Gadi Singer - Intel Corp., Santa Clara, CA 8.5s A Fast Simultaneous Input Vector Generation and
Ho-Kyu Kang - Samsung Electronics Co., Ltd., Seoul, Korea 7.3 SystemC Transaction Level Models and RTL Gate Replacement Algorithm for Leakage Power
Verification Reduction
Stuart Swan - Cadence Design Systems, Inc., Redwood City, CA Lei Cheng, Liang Deng, Deming Chen, Martin D.F. Wong - Univ. of
7.4 Towards a C++-Based Design Methodology Illinois, Urbana, IL
Facilitating Sequential Equivalence Checking 8.6s Timing Driven Power Gating
Venkat Krishnaswamy - Calypto Design Systems, Inc., Santa Clara, CA De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang - National Tsing-
Phillipe Georgelin - ST Microelectronics, Crolles, France Hua Univ., Hsinchu, Taiwan
22 Chingwei Yeh - National Chung Cheng Univ., Chiayi, Taiwan
43rdDAC-2C 7/3/06 9:16 AM Page 23

All speakers are denoted in bold

denotes short paper - S Tuesday July 25, 2006
denotes best paper candidate - ß
session of special interest to designers - b
indicates videoed session -

SESSION 9 b Rm: 304 SESSION 10 Rm: 303 SESSION 100 Rm: 301

MPSOC DESIGN METHODOLOGIES AND STATISTICAL TIMING ANALYSIS DECISION-MAKING FOR COMPLEX SOCS IN
APPLICATIONS Chair: Chandu Visweswariah - IBM Corp., Yorktown CONSUMER ELECTRONIC PRODUCTS
Chair: Dan Gajski - Univ. of California, Irvine, CA Heights, NY Chair: Ron Wilson - EDN, San Mateo, CA
Organizers: Peter Marwedel, Tajana Simunic Organizers: David Blaauw, Hai Zhou Organizer: Yervant Zorian
Multi-processor systems-on-chip (MPSoC) pose many new challenges to Static timing analysis continues to be a major source of innovation at Consumer electronics chips are the technology drivers today. They
the design of embedded systems. The first two papers highlight design the algorithmic and modeling levels. This session has four excellent require different types of optimizations and thus the need to adopt
methdologies for two application extremes: a high-performance papers in this area that will provide users and practitioners with a emerging solutions to meet such requirements. Optimizing for high
biomedical monitoring and reconfigurable low-power RFID tags. The next first hand view of new developments in academia and in industry. volume production, low power, and shrinking sizes necessitate
two papers discuss design tradeoffs between P2P vs. NoC interconnect, adequate tradeoff analysis and technical/business decision making by
and between circuit-switching and packet-switching schemes. 10.1 Refined Statistical Static Timing Analysis
management. The lead managers in this session will discuss today’s
Through Learning Spatial Delay Correlations emerging solutions and their economic impact.
ß- 9.1 A Multiprocessor System-on-Chip for Real-Time Ben Lee, Li-C Wang - Univ. of California, Santa Barbara, CA
Biomedical Monitoring and Analysis: Architectural 100.1 Qualcomm Lessons Learned at the
Design Space Exploration Magdy S. Abadir - Freescale Semiconductor, Inc., Austin, TX
65nm Node
Iyad Al Khatib - KTH, Kista, Sweden 10.2 Statistical Timing Analysis with Correlated Non-
Charlie Matar, Riko Radojcic - Qualcomm CDMA Technologies,
Francesco Poletti - Univ. of Bologna, Bologna, Italy Gaussian Parameters Using Independent San Diego, CA
Davide Bertozzi - Univ. of Ferrara, Ferrara, Italy Component Analysis
Luca Benini - Univ. of Bologna, Bologna, Italy 100.2 Low Power Challenges in Wireless ICs
Jaskirat Singh - Univ. of Minnesota, St. Paul, MN
Mohamed Bechara, Hasan Khalifeh - American Univ. of Beirut, Beirut, Lebanon Sachin Sapatnekar - Univ. of Minnesota, Minneapolis, MN Rene Delgado - Freescale Semiconductor, Inc., Austin, TX
Axel Jantsch - Royal Institute of Tech., Stockholm, Sweden 100.3 Consumer Electronics Development
Rustam Nabiev - Karolinska, Stockholm, Sweden 10.3 Statistical Timing Based on Incomplete
Probalistic Descriptions of Parameter Tradeoffs in the High-Tech Startup
9.2 An Automated, Reconfigurable, Low-Power RFID Tag Dawn Fitzgerald - Aurora Enterprises, Boston, MA
Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shenchih Uncertainty
Tung, Ralph Sprang, Josh Fazekas, James T. Cain, Marlin H. Mickle - Univ. Wei-Shen Wang - Univ. of Texas, Austin, TX 100.4 Architecture Planning Criteria for a System-
of Pittsburgh, Pittsburgh, PA Vladik Kreinovich - Univ. of Texas, El Paso, TX in-Package Portable Multimedia Platform
9.3 Design Space Exploration and Prototyping for Michael Orshansky - Univ. of Texas, Austin, TX Mario Manninger - austriamicrosystems AG, Unterpremstaetten,
On-Chip Multimedia Applications 10.4 Probabilistic Interval-Valued Computation: Austria
Hyung Gyu Lee - Seoul National Univ., Seoul, South Korea Toward a Practical Surrogate for Statistics
Umit Y. Ogras - Carnegie Mellon Univ., Pittsburgh, PA Inside CAD Tools
Naehyuck Chang - Seoul National Univ., Seoul, South Korea
Amith Singhee, Claire F. Fang, James D. Ma, Rob A. Rutenbar -
Radu Marculescu - Carnegie Mellon Univ., Pittsburgh, PA
Carnegie Mellon Univ., Pittsburgh, PA
9.4 Evaluation and Design Tradeoffs Between
Circuit-Switched and Packet-Switched NoCs
for Application-Specific SoCs
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen - National Chung 23
Cheng Univ., Chia-Yi, Taiwan
43rdDAC-2C 7/3/06 9:16 AM Page 24

Tuesday July 25, 2006 All speakers are denoted in bold

S - denotes short paper
ß - denotes best paper candidate
b - session of special interest to designers
- indicates videoed session

SESSION 11 b Rm: 306/308 SESSION 12 b Rm: 307 SESSION 13 Rm: 305

PANEL: ENTERING THE HOT ZONE — CAN YOU SPECIAL SESSION: RELIABILITY CHALLENGES POWER GRID ANALYSIS AND DESIGN
HANDLE THE HEAT AND BE COOL? FOR 65NM AND BEYOND Chair: Sani R. Nassif - IBM Corp., Austin, TX
Chair: Daya Nadamuni - Gartner Dataquest, San Jose, CA Chair: David Yeh - Texas Instruments/SRC, Organizers: Farid N. Najm, Vikram Jandhyala
Organizer: Michelle Clancy Research Triangle Park, NC Design and verification of the power grid have become critical steps
Electronic gadgets are becoming more pervasive at the office and in Organizers: Joel Phillips, Nagaraj NS for achieving timing success and noise free operation in high-
the home where they can no longer be equipped with large fans or The intent of this special session: 1) Give the EDA community a performance integrated circuits. This session presents a sequence of
vents. One of the biggest challenges is putting more functionality into comprehensive perspective on the problem, explaining what can go excellent papers that cover a spectrum of issues in this area. It starts
a smaller space and managing heat dissipation. Lack of voltage scaling wrong (HCI, NBTI, EM, TDDB, SER, ESD, etc.), what will be the major with a detailed study of power grid design issues covering
for future generations has forced designers to be more innovative to challenges at 65nm and beyond, and how reliability interacts with other inductance and decoupling capacitors in large microprocessor
handle heat dissipation challenges. This panel discusses the design constraints. For example, NBTI not only hurts the reliability of the design. Subsequent papers cover detailed power grid simulation,
breakthroughs required to address the power and thermal concerns circuit, but also reduces yield due to the high-temp burn-in process, and variational analysis of the grid parasitics, and budgeting techniques
for IC package and system designers, and the necessary cooperation higher temperature density due to integration density worsens both EM for the decoupling capacitance.
between these teams and EDA companies. and NBTI issues. 2) Survey design-in-reliability; what can designers do to
build in reliability in products. 3) Present a tools perspective, including ß-13.1 Power Grid Physics and Implications for CAD
Panelists: Eli Chiprout - Intel Corp., Hillsboro, OR
the primary effects (HCI, NBTI, EM) for which EDA tools are available,
Javier De La Cruz - eSilicon Corp., Sunnyvale, CA types of tools (dynamic simulation vs. static rule checking), necessary
Sanjay Pant - Univ. of Michigan, Ann Arbor, MI
Uming Ko - Texas Instruments Inc., Dallas, TX reliability infrastructure and flows that have worked in practice. Finally,
ß-13.2 Fast Analysis of Structured Power Grid by
new and developing areas of interest, missing pieces, and future
Simon Burke - ATI Technologies, Inc., Santa Clara, CA Triangularization Based Structure Preserving
opportunities will be discussed. 4) The topics covered in the special
Rajit Chandra - Gradient Design Automation, Santa Clara, CA session will ensure no rehash of traditional topics and good flow of Model Order Reduction
Andrew Yang - Apache Design Solutions, Inc., Mountain View, CA theory and practice. The session ensures a good balance of key physics
Hao Yu, Yiyu Shi, Lei He - Univ. of California, Los Angeles, CA
phenomena, EDA tools and practical design flows.
Sribalan Santhanam - PA Semi, Santa Clara, CA 13.3 Stochastic Variational Analysis of Large Power
12.1 Reliability Challenges for 45nm and Beyond Grids Considering Intra-die Correlations
Joe McPherson - Texas Instruments Inc., Dallas, TX Praveen Ghanta, Sarma Vrudhula, Sarvesh Bhardwaj - Arizona State
12.2 Design Tools for Reliability Analysis Univ., Tempe, AZ, Rajendran Panda - Freescale Semiconductor, Inc.,
Zhihong Liu, Bruce W. McGaughy, James Z. Ma - Cadence Design Austin, TX
Systems, Inc., San Jose, CA 13.4 A Fast On-Chip Decoupling Capacitance
12.3 Design in Reliability for Communication Designs Budgeting Algorithm Using Macromodeling and
Uday B. Reddy - Intel Corp., Folsom, CA Linear Programming
Murty Dasaka, Pavan Kaipa - Intel Corp., Bangalore, India Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan,
12.4 Practical Aspects of Reliability Yuhong Fu - Freescale Semiconductor, Inc., Austin, TX
Analysis for IC Designs
Thomas Pompl, Christian Schlunder, Martina Hommel, Heiko
24 Nielen, Jens Schneider - Infineon Tech. AG, Germany
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All speakers are denoted in bold

denotes short paper - S Tuesday July 25, 2006
denotes best paper candidate - ß
session of special interest to designers - b
indicates videoed session -

SESSION 14 Rm: 304 SESSION 15 Rm: 303 SESSION 150 Rm: 301

ADVANCES IN FORMAL SOLVERS GATE MODELING AND MODEL ORDER TRADEOFFS AND CHOICES FOR EMERGING
Chair: Jeremey Levitt - Mentor Graphics Corp., San Jose, CA REDUCTION SOCS IN HIGH-END APPLICATIONS
Organizers: Alan Hu, Anmol Mathur Chair: Peter Feldmann - IBM Corp., Yorktown Heights, NY Chair: Nic Mokhoff - EE Times, Manhasset, NY
The session focuses on advances in Boolean and word-level solvers Organizers: Charlie Chung-Ping Chen, Joel Phillips Organizer: Yervant Zorian
at the heart of formal verification tools. The first paper describes a The first half of this session features advances in modeling for timing Design and manufacturing flows and methodologies are directly
distributed approach to dynamic variable ordering for BDDs. The analysis, presenting improved models for multi-input switching and impacted by the demand for emerging SoCs with increasing
next paper describes the use of SAT for redundancy removal using statistical computations for current-based models. The second half performance and parallelism. Moving to new semiconductor
output don’t-cares for simplifying circuit descriptions for simplifying of the session presents advances related to reduced-order technology nodes can significantly affect the choices of suppliers. This
Boolean reasoning. The third paper presents word-level techniques modeling. Two papers discuss detailed technical issues related to session will provide an overview of changing needs and corresponding
for efficient solution of difference logic. The final paper in this passivity preserving modeling, and the final paper features new ideas management decision criteria to make the right choices from a pool
session proposes a novel framework for extracting illegal states of a about handling large numbers of model inputs. of alternate options for flows, methodologies and suppliers.
sequential circuit and using them during SAT-based induction.
15.1 A Multi-port Current Source Model for Multiple 150.1 Assessing Process Nodes and IP for SoC
14.1 Distributed Dynamic BDD Reordering Input Switching Effects in CMOS Library Cells Development
Ziv Nevo - IBM Corp., Haifa, Israel Chirayu S. Amin, Chandramouli Kashyap, Noel Menezes, Kip Ken Wagner - PMC-Sierra, Inc., Burnaby, BC, Canada
Monica C. Farkash - IBM Corp., Austin, TX Killpack, Eli Chiprout - Intel Corp., Hillsboro, OR 150.2 Open-IP: How Your Selection of IP Drives
ß- 14.2 SAT Sweeping with Local Observability 15.2s Statistical Logic Cell Delay Analysis Using a Your ASIC Success
Don’t-Cares Current-Based Model Rajesh Shah - Open-Silicon, Milpitas, CA
Qi Zhu, Nathan B. Kitchen - Univ. of California, Berkeley, CA Hanif Fatemi, Shahin Nazarian, Massoud Pedram - Univ. of Southern 150.3 Yield, Manufacturability and Test: The Criteria
Andreas Kuehlmann - Cadence Berkeley Labs, Berkeley, CA California, Los Angeles, CA
Alberto Sangiovanni-Vincentelli - Univ. of California, Berkeley, CA to Judge the Right Design Investment
15.3s Multi-Shift Quadratic Alternating Direction Rajesh Galivanche - Intel Corp., Santa Clara, CA
14.3 Predicate Learning and Selective Theory Implicit Iteration for High-Speed Positive-Real Kee Sup Kim - Intel Corp., Folsom, CA
Deduction for a Difference Logic Solver Balanced Truncation 150.4 Management Day Cocktail Party
Chao Wang, Aarti Gupta, Malay Ganai - NEC-Labs America, Ngai Wong - Univ. of Hong Kong, Hong Kong
Princeton, NJ Venkataramanan Balakrishnan - Purdue Univ., West Lafayette, IN
14.4 Fast Illegal State Identification for Improving 15.4 A Fast Passivity Test for Descriptor Systems via
SAT-Based Induction Structure-Preserving Transformations of Skew-
Vishnu C. Vimjam, Michael S. Hsiao - Virginia Tech., Blacksburg, VA Hamiltonian/Hamiltonian Matrix Pencils
Ngai Wong, Chung Kwan Chu - Univ. of Hong Kong, Hong Kong
15.5 Model Order Reduction of Linear Networks With
Massive Ports via Frequency-Dependent Port Packing
Peng Li, Weiping Shi - Texas A&M Univ., College Station, TX 25
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ß - denotes best paper candidate
b - session of special interest to designers
- indicates videoed session

SESSION 16 Rm: 306/308 SESSION 17 b Rm: 307 SESSION 18 Rm: 305

SPECIAL SESSION: MPSOC DESIGN TOOLS SPECIAL SESSION: HIGHLIGHTS OF ISSCC: BUFFER INSERTION
Chair: Pierre Paulin - STMicroelctronics, Nepean, ON, Canada MULTIMEDIA Chair: Charles J. Alpert - IBM Corp., Austin, TX
Organizer: Sumit Gupta Chair: Wanda Gass - Texas Instruments Inc., Dallas, TX Organizers: Dirk Stroobandt, Louis Scheffer
This session discusses the problems associated with the design and Organizers: Andrew B. Kahng, Ingrid Verbauwhede Buffer insertion is important for coping with timing constraints but the
verification of SoCs that have instantiations of multiple processors This is the now-traditional best of ISSCC session at DAC. This year, we sheer number of buffers needed poses problems. The first paper deals
and the requirements that this places on software tools. We will selected the best of multimedia-related papers at ISSCC as part of our with the large circuit sizes in an efficient way. The other two papers
discuss issues pertaining to system-level modeling and application theme day session offerings. acknowledge that buffer insertion should also take slew constraints
partitioning and mapping as it pertains to the challenges faced by into account.
MPSoC designers. Specifically, we will present the problems faced by 17.1 Design of a 125uW, Fully Scalable MPEG-2 and
MPSoC designers and why and how these problems are unique to H.264/AVC Video Decoder for Mobile Applications 18.1 Buffer Insertion in Large Circuits with
multi-processor systems. We will discuss issues related to real-time Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee - National Chiao-Tung Constructive Solution Search Techniques
operating system (RTOS) requirements, application partitioning, Univ., Hsinchu, Taiwan Mandar Waghmode, Zhuo Li, Weiping Shi - Texas A&M Univ., College
inter-processor communication, multi-processor design, et cetera. Ting-An Lin, Sheng-Zen Wang - MediaTek, Inc., Hsinchu, Taiwan Station, TX
We will follow this with how software design tools can help alleviate 17.2 Memory in the Multimedia Era 18.2 Low-Power Repeater Insertion with Both Delay
some of these problems, what parts of the design flow can be fully
automated, and what parts can be aided by design tools. We will also Changhyun Kim - Samsung Electronics Co, Ltd., Gyeonggi-do, Korea and Slew Rate Constraints
discuss the state of design tools in the industry and academia today 17.3s A CMOS SoC for 56/18/16 CD/DVD-dual/RAM Yuantao Peng, Xun Liu - North Carolina State Univ., Raleigh, NC
and what pieces of the puzzle are missing. Applications 18.3 Fast Algorithms For Slew Constrained Minimum
16.1 Overview of the MPSoC Design Challenge Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Cost Buffering
Grant E. Martin - Tensilica, Inc., Santa Clara, CA Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Shiyan Hu - Texas A&M Univ., College Station, TX
Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Charles J. Alpert - IBM Corp., Austin, TX
16.2 Programming Models and HW-SW Interfaces Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan
Abstraction for Multi-Processor SoC Jiang Hu - Texas A&M Univ., College Station, TX
Huang, Benjamin Chiu, Alex Ho - MediaTek Inc., Hsinchu, Taiwan Shrirang Karandikar - IBM Corp., Austin, TX
Ahmed A. Jerraya - TIMA/CNRS, Grenoble, France 17.4 Hierarchical Power Distribution and Power Management Zhuo Li, Weiping Shi - Texas A&M Univ., College Station, TX
Frederic Petrot - TIMA/INPG, Grenoble, France Scheme for a Single Chip Mobile Processor C. N. Sze - IBM Corp., Austin, TX
Aimen Bouchhima - TIMA, Grenoble, France Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi
16.3 System-Level Exploration Tools for Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao
MPSoC Designs Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi
Simon Davidmann, Peter Flake, Frank Schirrmeister - Imperas, Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko
Inc., Palo Alto, CA Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose,
Saneaki Tamaki, Shinichi Yoshioka - Renesas Technology Corp., Tokyo, Japan
Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada,
Naohiko Irie - Hitachi, Ltd, Tokyo, Japan
Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno - NTT
26 DoCoMo, Inc, Yokosuka, Japan
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SESSION 19 Rm: 304 SESSION 20 b Rm: 303 SESSION 21 Rm: 301

TESTING AND VALIDATION ADVANCED TOPICS IN PROCESSOR AND SOFTWARE FOR REAL-TIME APPLICATIONS
FOR TIMING DEFECTS SYSTEM VERIFICATION Chair: Mahmut Kandemir - Pennsylvania State Univ.,
Chair: Cecilia Metra - Univ. of Bologna, Bologna, Italy Chair: Jon Michelson - Cisco Systems, Inc., San Jose, CA University Park, PA
Organizers: Erik Jan Marinissen, Gordon Roberts Organizers: Avi Ziv, Harry Foster Organizers: Lothar Thiele, Vincent Mooney
With increasing operation frequencies of ICs, testing and validation of The session presents four papers on dynamic verification and real- Real-time applications stress power and execution time constraints.
timing defects are becoming more important and challenging. time fault detection in processors and systems-on-chip. The first two These papers address approaches for real-time estimation and
papers present various interesting aspects of successful verification of optimization of power, worst-case execution time, and context
19.1 A Flexible and Scalable Methodology complex microprocessor (the Merom processor from Intel) and switch costs. Novel techniques critical for embedded software will
for GHz-Speed Structural Test system-on-a-chip, (the Cell processor from Sony, Toshiba, IBM). The be presented with application scenarios and exciting results.
Vikram Iyengar, Gary Grise, Mark Taylor, Rudy Farmer - IBM third paper describes methods for real-time detection and recovery
from functional bugs, and the last paper deals with stimuli generation 21.1 Rapid and Low-Cost Context-Switch through
Corp., Essex Junction, VT
for a processor-based multimedia system-on-a-chip. Embedded Processor Customization for Real-
ß-19.2 Timing-Based Delay Test for Screening Time and Control Applications
Small Delay Defects 20.1 Practical Methods in Coverage-Oriented
Xiangrong Zhou, Peter D. Petrov - Univ. of Maryland,
Nisar Ahmed, Mohammad Tehranipoor - Univ. of Maryland, Verification of the Merom Microprocessor College Park, MD
Baltimore, MD Alon Gluska - Intel Corp., Haifa, Israel
Vinay Jayaram - Texas Instruments Inc., Dallas, TX 21.2 Efficient Detection and Exploitation of Infeasible
20.2 Verification of the Cell Broadband Paths for Software Timing Analysis
19.3 Hold Time Validation on Silicon and the Engine Processor Ting Chen, Tulika Mitra, Abhik Roychoudhury, Vivy Suhendra, -
Relevance of Hazards in Timing Analysis Kanna Shimizu, Sanjay Gupta - IBM Corp., Austin, TX National Univ. of Singapore, Singapore
Amit Majumdar - Stratosphere Solutions, Inc., Sunnyvale, CA Tatsuya Koyama - Sony Computer Entertainment Inc., Tokyo, Japan
Wei-Yu Chen, Jun Guo - Sun Microsystems, Inc., Sunnyvale, CA Takashi Omizo - Toshiba Corp., Ohme, Japan 21.3 Leakage-Aware Intraprogram Voltage Scaling
Jamee Abdulhafiz - IBM Corp., Austin, TX for Embedded Processors
Yukio Watanabe - Toshiba Corp., Kawasaki, Japan Po-Kuan Huang, Soheil Ghiasi - Univ. of California, Davis, CA
Larry McConville, Todd Swanson - IBM Corp., Austin, TX
20.3s Shielding Against Design Flaws with Field
Repairable Control Logic
Ilya Wagner, Valeria Bertacco, Todd Austin - Univ. of Michigan,
Ann Arbor, MI
20.4s Scheduling-based Test-case Generation for
Verification of Multimedia SoCs
Amir Nahir, Avi Ziv - IBM Corp., Haifa, Israel
Roy Emek - Consultant, Tel Aviv, Israel
Nir Ronen, Tal Keidar - Zoran Corp., Haifa, Israel 27
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ß - denotes best paper candidate
b - session of special interest to designers
- indicates videoed session

SESSION 22 Rm: 306/308 SESSION 23 b Rm: 307 SESSION 24 Rm: 305

PANEL: BUILDING A STANDARD ESL INVITED SESSION: CAD CHALLENGES FOR ROUTING
DESIGN AND VERIFICATION METHODOLOGY: LEADING-EDGE MULTIMEDIA DESIGNS Chair: Dinesh Gaitonde - Xilinx, Inc., Mountain View, CA
IS IT JUST A DREAM? Chair: Andrew B. Kahng - Univ. of California at San Diego, Organizers: Patrick Groeneveld, Phiroze Parakh
Chair: Gary Smith - Gartner DataQuest, San Jose, CA La Jolla, CA The first paper in this session introduces a global router with
Organizer: Francine Bacchini Organizer: Andrew B. Kahng significantly better solution quality. The second paper presents an
Industry cooperation established standards to support electronic Multimedia designs are among the most complex leading-edge efficient delay-update technique for network topologies. The
system level (ESL) design and verification. But where is the common, integrated circuits that are made today. In this session, CAD third paper presents an innovative method for steiner tree
standard ESL methodology itself? Leading ESL adopters devise their architects for three industry-leading multimedia products will construction via RC network-analysis. Finally, the fourth paper
own custom methodologies, but is a standard ESL methodology — discuss new challenges that arise across the CAD flow – from pesents a fast timing-driven steiner tree algorithm.
open to all — possible? ESL users and suppliers will look at what is system and architecture level through physical implementation – as ß-24.1 BoxRouter: A New Global Router Based on Box
being done today and debate the issues around what is needed. we approach billion-transistor devices. The first talk will focus on Expansion and Progressive ILP
Panelists: system-level specification and codesign of embedded software for a Minsik Cho, David Z. Pan - Univ. of Texas, Austin, TX
multimedia processor. The second talk will discuss new time and
Anoosh Hosseini - Cisco Systems, Inc., Milpitas, CA space challenges for verification methodologies, which must be met 24.2 Steiner Network Construction for
Ashish Parikh - PixelWorks, Inc., Campbell, CA to address the requirements of graphics processor time-to-market Timing Critical Nets
Pascal Urard - STMicroelectronics, Crolles Cedex, France pressures. The third talk will discuss CAD challenges unique to a Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li - Texas A&M Univ.,
Emil Girczyc - Summit Design, Inc., Los Altos, CA pioneering high-speed, multi-core processing engine for gaming and College Station, TX
Simon Bloch - Mentor Graphics Corp., San Jose, CA entertainment platforms.
H. Tony Chin - HD Lab Inc., Yokohama, Japan 24.3s Circuit Simulation Based Obstacle-Aware
23.1 Addressing the Challenge of Low Power, High Steiner Routing
Performance and Scalable Multimedia Yiyu Shi, Paul Mesa, Hao Yu, Lei He - Univ. of California, Los Angeles, CA
Acceleration in the Nomadik Processor
24.4s Timing-Driven Steiner Trees are
Patrick Blouet - STMicroelectronics, Crolles, France
(Practically) Free
23.2 Next-Generation Multimedia Designs: Charles J. Alpert - IBM Corp., Austin, TX
Verification Needs Andrew B. Kahng - Blaze DFM, Inc., Sunnyvale, CA
Ira Chayut - NVIDIA, Santa Clara, CA C. N. Sze - IBM Corp., Austin, TX
23.3 CAD Challenges for Designing a High Frequency Qinke Wang - Univ. of California at San Diego, La Jolla, CA
Multi-Core SoC Implementation of a First-
Generation CELL Processor
Dac Pham - IBM Corp., Austin, TX

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session of special interest to designers - b
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SESSION 25 Rm: 304 SESSION 26 b Rm: 303 SESSION 27 Rm: 301

THE TEST BIN PANEL: VARIATION-AWARE ANALYSIS: SAVIOR LOW POWER AND ULTRA-LOW
Chair: Roni Khazaka - McGill Univ., Montreal, Canada OF THE NANOMETER ERA? VOLTAGE DESIGN
Organizers: Cecilia Metra, Erik Jan Marinissen Chair: William H. Joyner, Jr. - IBM Corp./SRC, Research Chair: Chris Kim - Univ. of Minnesota, Minneapolis, MN
The first paper is on software-based test for microprocessors. The Triangle Park, NC Organizers: Diana Marculescu, Trevor Mudge
second paper is on re-ordering test patterns to improve diagnostic Organizer: Shishpal Rawat This session covers topics related to physical leakage models,
resolution. The third paper proposes on-chip DFT for impedance VLSI engineers have traditionally used a variety of CAD analysis subthreshold circuit design, and low power voltage assignment.
matching of I/Os. tools (e.g. SPICE) to deal with variability. As we go into deep sub
27.1 A Fully Physical Model for Leakage
25.1 Systematic Software-Based Self-Test for micron issues, the analysis is becoming harder due to many
secondary effects becoming primary. Panelists will debate the Distribution under Process Variations in
Pipelined Processors variability trend and present the order of importance of many Nanoscale Double-Gate CMOS
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail - Univ. variability trends (Vdd, Vt, Interconnect, Leff, Gate Width) and their Hari Ananthan, Kaushik Roy - Purdue Univ., West Lafayette, IN
of Piraeus, Piraeus, Greece, impact on design tools and methodologies.
27.2 A PLA Based Asynchronous Micropipelining
Antonis Paschalis - Univ. of Athens, Athens, Greece Panelists:
Anand Raghunathan, Srivaths Ravi - NEC Labs. America, Princeton, NJ Approach for Subthreshold Circuit Design
Vijay Pitchumani - Intel Corp., Santa Clara, CA Nikhil Jayakumar, Rajesh Garg - Texas A&M Univ., College Station, TX
25.2 A Test Pattern Ordering Algorithm for Clive D. Bittlestone - Texas Instruments Inc., Dallas, TX
Sani R. Nassif - IBM Corp., Austin, TX Bruce Gamache - Univ. of Colorado, Boulder, CO
Diagnosis with Truncated Fail Data Sunil Khatri - Texas A&M Univ., College Station, TX
Gang Chen, Sudhakar M. Reddy - Univ. of Iowa, Iowa City, IA Norma Rodriquez - Advanced Micro Devices, Inc., Sunnyvale, CA
Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI 27.3s Subthreshold Logical Effort: A Systematic
Irith Pomeranz - Purdue Univ., West Lafayette, IN Riko Radojcic - Qualcomm CDMA Technologies, San Diego, CA
Janusz Rajski - Mentor Graphics Corp., Wilsonville, OR Framework for Optimal Subthreshold
Device Sizing
25.3 DFT for Controlled-Impedance I/O Buffers
John Keane, Tae-Hyoung Kim, Hanyong Eom, Sachin Sapatnekar,
Ahmad Alyamani - King Fahd Univ. of Petroleum and Minerals,
Chris Kim - Univ. of Minnesota, Minneapolis, MN
Dhahran, Saudi Arabia
27.4s Timing-Constrained and Voltage-Island-Aware
Voltage Assignment
Huaizhi Wu - Cadence Design Systems, Inc., San Jose, CA
Martin D.F. Wong - Univ. of Illinois, Urbana-Champaign, Urbana , IL
I-Min Liu - Atoptech, Inc., Santa Clara, CA

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ß - denotes best paper candidate
b - session of special interest to designers
- indicates videoed session

SESSION 28 Rm: 306/308 SESSION 29 b Rm: 307 SESSION 30 Rm: 305

HIGH-LEVEL EXPLORATION AND PANEL: DESIGN CHALLENGES FOR NEXT- CAD FOR FPGAS
OPTIMIZATION GENERATION MULTIMEDIA, GAME AND Chair: William N.N. Hung - Synplicity, Inc., Sunnyvale, CA
Chair: Rishiyur S. Nikhil - Bluespec, Inc., Waltham, MA ENTERTAINMENT PLATFORMS Organizers: Bill Halpin, Steven Teig
Organizers: Reinaldo Bergamaschi, Rishiyur S. Nikhil Chair: Bryan Lewis - Gartner Dataquest, San Jose, CA FPGAs have relied on computer-aided design techniques for logic
This session presents five papers which advance the state-of-the-art in Organizer: Andrew B. Kahng synthesis and physical design since their inception. This session
high-level synthesis optimization and design space exploration. The Multimedia, game, and entertainment devices have pushed the leading provides novel design tools and methods for solving these
first paper presents a new scheduling formulation based on a system edge of performance, complexity, power, form-factor, design cycle “traditional” problem areas, including retiming, clustering, technology
of difference constraints. The second paper presents a novel approach time, and other key aspects of ASIC design for the past several mapping and placement.
for considering clock skew during high-level synthesis. The third and technology nodes. This panel brings together experts who are defining
fourth paper present efficient design exploration approaches for high- ß-30.1 Architecture-Aware FPGA Placement Using
the next generation of gaming, mobile TV, digital home, display, and
level design, and the fifth paper presents a method for fast estimation multimedia processing platforms, to answer such questions as: Metric Embedding
of controller delay from high-level specifications. Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi - Carnegie
• What are the underlying chip architectures and roadmaps for key
multimedia/entertainment platforms? Mellon Univ., Pittsburgh, PA
28.1 An Efficient and Versatile Scheduling Algorithm
Based On SDC Formulation • What are the key design and technology challenges (or "brick 30.2 Efficient SAT-based Boolean Matching for FPGA
Jason Cong, Zhiru Zhang - Univ. of California, Los Angeles, CA walls") for next-generation products, and how will these Technology Mapping
challenges be addressed? Sean A. Safarpour - Univ. of Toronto, Toronto, ON, Canada
ß- 28.2 Register Binding for Clock Period Minimization Gregg Baeckler, Richard Yuan - Altera Corp., San Jose, CA
Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, • What other challenges arise from complex supplier/competitor
relationships, standards, and other aspects of a globalized market? Andreas Veneris - Univ. of Toronto, Toronto, ON, Canada
Wei-Chieh Yu - Chung Yuan Christian Univ., Chung Li, Taiwan
• Where will we see the next "convergence" in devices and 30.3 Optimal Simultaneous Mapping and Clustering
28.3 Towards Automatic Exploration of Arithmetic platforms? for FPGA Delay Optimization
Circuit Architectures The panelists will also present insights into other aspects of Joey Y. Lin - Magma Design Automation, Inc., Los Angeles, CA
Ajay K. Verma, Paolo Ienne - EPFL, Lausanne, Switzerland today’s multimedia/entertainment platforms: CAD and design Deming Chen - Univ. of Illinois, Urbana, IL
28.4s Design Space Exploration Using Time and methodologies, design enablement (compilers, programming Jason Cong - Univ. of California, Los Angeles, CA
Resource Duality with the Ant Colony models, etc.), design for IP reuse (configurability, derivatives), and IP
management in a world of "co-opetition". 30.4 Simultaneous Time Slack Budgeting and
Optimization Retiming for Dual-Vdd FPGA Power Reduction
Panelists:
Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner - Univ. of Yu Hu, Yan Lin, Lei He - Univ. of California, Los Angeles, CA
California, Santa Barbara, CA John Cohn - IBM Corp., Essex Junction, VT
Chris Malachowsky - NVIDIA Corp., Santa Clara, CA Tim Tuan - Xilinx Corp., San Jose, CA
28.5s Rapid Estimation of Control Delay from High-
Richard Tobias - Pixelworks, Inc., Campbell, CA
Level Specifications Jeong-Taek Kong, Sr. - Samsung Electronics Co., Ltd., Giheung, Korea
Gagan R. Gupta - Univ. of Wisconsin, Madison, WI Brendan Traw - Intel Corp., Hillsboro, OR
Madhur Gupta - Purdue Univ., West Lafayette, IN
Preeti R. Panda- Indian Institute of Tech., New Delhi, India
30
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SESSION 31 b Rm: 304 SESSION 32 Rm: 303 SESSION 33 b Rm: 301

SECURE SYSTEMS LOGIC SYNTHESIS 1 LOW-POWER, THERMAL-AWARE ARCHITECTURES

Chair: Catherine Gebotys - Univ. of Waterloo, Waterloo, Canada Chair: Davide Pandini - STMicroelectronics, Milano, Italy Chair: Kevin Skadron - Univ. of Virginia, Charlottsville, VA
Organizers: Pai Chou, Peter Marwedel Organizers: James Hoe, Rajeev Murgai Organizers: Diana Marculescu, Naehyuck Chang
The papers in this session address a critical area in system design: security. This session presents new ideas in combinational logic synthesis. It This session covers topics related to energy aware architectures for
VIRTUS enables security through processor virtualization. Network offers a fresh look at classical topics such as symmetry detection, OFDM transmitter design and control, and low power hearing aid
security processor design gives flexibility and scalability for cryptographic boolean matching, and rewriting-based logic optimization. It also design, as well as thermal management and energy estimation at
functions. A methodology for exploring the security processing software visits emerging areas such as gate sizing for finFETs and technology architecture level.
architecture on SoCs is the topic of the third paper. IMPRES presents a mapping for leakage current.
HW/SW technique for improving processor security and reliability. 33.1 Energy-Scalable OFDM Transmitter Design and
Ciphering and integrity checking of data exchanged between a SoC and its 32.1 Symmetry Detection for Large Boolean Control
external memory is the addressed in the last paper. Functions Using Circuit Representation, Björn Debaillie, Bruno Bougard, Gregory Lenoir, Gerd
ß- 31.1 VIRTUS: A New Processor Virtualization Architecture Simulation and Satisfiability Vandersteen, Francky Catthoor - IMEC, Leuven, Belgium
for Security-Oriented Next-Generation Mobile Terminals Jin S. Zhang - Portland State Univ., Portland, OR 33.2 Systematic Temperature Sensor Allocation and
Hiroaki Inoue - NEC Corp., Sagamihara, Japan Alan Mishchenco, Robert Brayton - Univ. of California, Berkeley, CA, Placement for Microprocessors
Akihisa Ikeno, Masaki Kondo - NEC Informatec Systems, Ltd., Kawasaki, Japan Malgorzata Chrzanowska-Jeske - Portland State Univ., Portland, OR Rajarshi Mukherjee, Seda Ogrenci Memik - Northwestern Univ.,
Junji Sakai, Masato Edahiro - NEC Corp., Sagamihara, Japan
32.2 Exploiting K-Distance Signature for Boolean Evanston, IL
31.2 A Network Security Processor Design Based on an
Integrated SoC Design and Test Platform Matching and G-Symmetry Detection 33.3 HybDTM: A Coordinated Hardware-Software
Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng lee, Jen-Chieh Yeh, Chih- Kuo-Hua Wang - Fu Jen Catholic Univ., Taipei, Taiwan Approach for Dynamic Thermal Management
Tsun Huang, Cheng-Wen Wu - National Tsing-Hua Univ., Hsinchu, Taiwan 32.3 Gain-Based Technology Mapping for Minimum Amit Kumar - Princeton Univ., Princeton, NJ
31.3 Software Architecture Exploration for High-Performance Runtime Leakage under Input Vector Li Shang - Queen’s Univ., Kingston, ON, Canada
Security Processing on a Multiprocessor Mobile SoC Li-Shiuan Peh, Niraj K. Jha - Princeton Univ., Princeton, NJ
Uncertainty
Divya Arora - Princeton Univ., Princeton, NJ Ashish K. Singh, Murari Mani - Univ. of Texas, Austin, TX 33.4s A Systematic Method For Functional Unit
Srivaths Ravi, Anand Raghunathan, Murugan Sankaradass - NEC-Labs Power Estimation in Microprocessors
America, Princeton, NJ Ruchir Puri - IBM Corp., Yorktown Heights, NY
Michael Orshansky - Univ. of Texas, Austin, TX Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan - Univ. of
Niraj Jha - Princeton Univ., Princeton, NJ
Srimat T. Chakradhar - NEC-Labs America, Princeton, NJ California, Riverside, CA
32.4s Gate Sizing for FinFETs vs 32nm Bulk
31.4s IMPRES: Integrated Monitoring for Processor MOSFETS 33.5s Low-Power Architectural Tradeoffs in a VLSI
REliability and Security Brian G. Swahn, Soha Hassoun - Tufts Univ., Medford, MA Implementation of an Adaptive Hearing Aid
Roshan G. Ragel - Univ. of New South Wales, Sydney, Australia Algorithm
Sridevan Parameswaran - Univ. of New South Wales, Kensington, Australia 32.5s DAG-Aware AIG Rewriting: A Fresh Look at
Felix Buergin, Flavio Carbognani, Martin Hediger, Hektor Meier,
31.5s A Parallelized Way to Provide Data Encryption and Combinational Logic Synthesis Robert Meyer-Piening, Rafael Santschi, Norbert Felber, Hubert
Integrity Checking on a Processor-Memory Bus Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton - Univ. Kaeslin, Wolfgang Fichtner - ETH Zurich, Zurich, Switzerland
Reouven Elbaz - LIRMM/STMicroelectronics, Montpellier, France of California, Berkeley, CA
Lionel Torres, Gilles Sassatelli - LIRMM, Montpellier, France
Pierre Guillemin, Michel Bardouillet, Albert Martinez - STMicroelectronics,
Rousset, France 31
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ß - denotes best paper candidate
b - session of special interest to designers
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SESSION 34 Rm: 306/308 SESSION 35 b Rm: 307 SESSION 36 b Rm: 305

LOW POWER SYSTEM LEVEL DESIGN POWER-CONSTRAINED DESIGN FOR ELECTRICAL AND THERMAL ISSUES IN FPGAS
Chair: Massoud Pedram - Univ. of Southern California, MULTIMEDIA Chair: Rajeev Jayaraman - Xilinx, Inc., San Jose, CA
Los Angeles, CA Chair: Richard Tobias - PixelWorks, Campbell, CA Organizers: Patrick Lysaght, Ryan Kastner
Organizers: Diana Marculescu, Sanu Mathew Organizers: Andrew B. Kahng, John Cohn This session will explore a variety of electrical and thermal issues in
This session addresses topics related to low power system level This session presents a variety of design objectives and design solutions deep nanometer FPGAs. The papers present new algorithms and
design, ranging from extending the lifetime of fuel cell-based systems related to power constraints for multimedia applications. The first architectures to reduce leakage power in embedded memories,
and power management, to network-on-chip based architectures paper addresses energy-efficient messaging. The next paper offers new reduce thermal emulation runtimes, reduce leakage due to process
and multi-Vdd systems. approaches to dynamic voltage and frequency scaling-based energy variation, and analyze the degradation of FPGAs caused by hot
saving for multimedia systems: the second paper uses signature-based carrier effects.
34.1 Extending the Lifetime of Fuel Cell Based workload estimation, and the third paper applies DVFS in the context
Hybrid Systems 36.1 Leakage Power Reduction of Embedded
of gaming systems. The session closes with two short papers on design
Jianli Zhuo, Chaitali Chakrabarti - Arizona State Univ., Tempe, AZ techniques for power minimization in mobile displays. Memories on FPGAs Through Location
Naehyuck Chang - Seoul National Univ., Seoul, South Korea Assignment
35.1 SMERT: Energy-Efficient Design of a Multimedia Yan Meng, Timothy Sherwood, Ryan Kastner - Univ. of California,
Sarma Vrudhula - Arizona State Univ., Tempe, AZ
Messaging System for Mobile Devices Santa Barbara, CA
34.2 High-Level Power Management of Embedded Lin Zhong - Rice Univ., Houston, TX
Systems with Application-Specific Energy 36.2 A Fast HW/SW FPGA-Based Thermal
Bin Wei - AT&T Labs, Florham Park, NJ
Cost Functions Mike Sinclair - Microsoft Research, Redmond, WA Emulation Framework for Multi-Processor
Youngjin Cho, Naehyuck Chang - Seoul National Univ., System-on-Chip
35.2 Signature-Based Workload Estimation for
Seoul, South Korea David Atienza, Pablo G. Del Valle - DACYA/UCM, Madrid, Spain
Mobile 3D Graphics Giacomo Paci, Francesco Poletti, Luca Benini - DEIS/Univ. of Bologna,
Chaitali Chakrabarti, Sarma Vrudhula - Arizona State Univ., Tempe, AZ
Bren C. Mochocki - Univ. of Notre Dame, Notre Dame, NJ Bologna, Italy
34.3 Communication Latency Aware Low Power Srihari Cadambi, Kanishka Lahiri - NEC-Labs America, Princeton, NJ,
NoC Synthesis Giovanni De Micheli - LSI/EPFL, Lausanne, Switzerland
Xiaobo S. Hu - Univ. of Notre Dame, Notre Dame, IN Jose M. Mendias - DACYA/UCM, Madrid, Spain
Yuanfang Hu, Yi Zhu - Univ. of California at San Diego, La Jolla, CA 35.3 Games are Up for DVFS
Hongyu Chen - Synopsys, Inc., Mountain View, CA 36.3 An Adaptive FPGA Architecture with Process
Yan Gu, Samarjit Chakraborty, Wei Tsang Ooi - National Univ. of Variation Compensation and Reduced Leakage
Ronald Graham, Chung-Kuan Cheng - Univ. of California at San Diego,
Singapore, Singapore Georges Nabaa - Actel Corp., Mountain View, CA
La Jolla, CA
35.4s Power Aware Mobile Display Navid Azizi, Farid N. Najm - Univ. of Toronto, Toronto, ON, Canada
34.4 Optimal Study of Resource Binding
Ali Iranli, Wonbok Lee, Massoud Pedram - Univ. of Southern 36.4 FLAW: FPGA Lifetime AWareness
with Multi-Vdds
California, Los Angeles, CA Suresh Srinivasan, Prasanth Mangalagiri, Karthik Sarpatwari, Yuan
Deming Chen - Univ. of Illinois, Urbana, IL
Jason Cong, Yiping Fan - Univ. of California, Los Angeles, CA 35.5s Power Minimization for LED-backlit TFT-LCDs Xie, Vijaykrishnan Narayanan - Pennsylvania State Univ., University Park, PA
Junjuan Xu - Peking Univ., Beijing, China Wei-Chung Cheng - National Chiao Tung Univ., Hsinchu, Taiwan
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denotes short paper - S Wednesday July 26, 2006
denotes best paper candidate - ß
session of special interest to designers - b
indicates videoed session -

SESSION 37 b Rm: 304 SESSION 38 Rm: 303 SESSION 39 Rm: 301

SPECIAL SESSION: BEYOND LOW-POWER DESIGN: COMMUNICATION-DRIVEN SYNTHESIS PARALLELISM AND MEMORY OPTIMIZATIONS
ENVIRONMENTAL ENERGY HARVESTING Chair: Luca Carloni - Columbia Univ., New York, NY Chair: Steven Tjiang - Google, Mountain View, CA
Chair: Kaushik Roy - Purdue Univ., West Lafayette, IN Organizer: Stephen Edwards Organizers: Steven Tjiang, Vincent Mooney
Organizers: Pai Chou, Vijay Raghunathan On-chip communication is ubiquituous and more challenging With the emergence of chip multiprocessors, parallelism and memory
This session will feature renowned experts in the field of energy as chips get larger. The papers in this session address the optimizations become critical for efficient deployment of embedded
harvesting who will provide a comprehensive treatment of the area, problem of synthesizing more efficient, delay-tolerant software. Broadly speaking, memory issues cross the
drawing from state-of-the-art practice and emerging research directions communication structures. software/hardware boundary, and so several papers in this session
at all levels of design abstraction including materials/devices, circuits, address memory optimization from the software and hardware
38.1 Synthesis of Synchronous Elastic Architectures perspectives. Novel and interesting techniques will pique the attendees’
systems, and architecture/design. Environmental energy harvesting has
emerged as a promising technique to enable near-perpetual system Jordi Cortadella - Universitat Politécnica de Catalunya, interests in this session.
operation in several emerging applications (e.g., human bio-implants, Barcelona, Spain
Michael Kishinevsky, Bill Grundmann - Intel Corp., Hillsboro, OR
ß-39.1 A Constraint Network Based Solution to Code
ambient intelligence, wireless sensor networks). Further, it mitigates Parallelization
the cost and environmental impact of battery replacement and disposal. 38.2 Statistical On-Chip Communication Bus
The session will cover all aspects of designing and optimizing an Ozcan Ozturk, Guilin Chen, Mahmut Kandemir- Pennsylvania State
Synthesis and Voltage Scaling Under Timing Univ., University Park, PA
environmental energy harvesting system in a bottom-up manner,
starting from devices/materials, circuits, systems/architecture, and Yield Constraint 39.2 Buffer Memory Optimization for Video Codec
finally harvesting aware system-level power management policies. Sujan Pandey, Manfred Glesner - Darmstadt Univ. of Tech., Application Modeled in Simulink
Darmstadt, Germany Sang-Il Han - Seoul National Univ., Seoul, South Korea
37.1 Solution Processed Infrared Photovoltaic Devices Xavier Guerin - TIMA Lab, Grenoble, France
Edward H. Sargent, Dean D. MacNeil - Univ. of Toronto, Toronto, 38.3 Optimization of Area under a Delay
Soo-Ik Chae - Seoul National Univ., Seoul, South Korea
ON, Canada Constraint in Digital Filter Synthesis Using Ahmed A. Jerraya - TIMA Lab, Grenoble, France
SAT-Based Integer Linear Programming 39.3 Configurable Cache Subsetting for Fast Cache Tuning
37.2 Circuits for Energy Harvesting Sensor Signal Processing
Rajeevan Amirtharajah - Univ.of California, Davis, CA Levent Aksoy - Istanbul Tech. Univ., Istanbul, Turkey Pablo Viana - UFPE, Recife, Brazil
Eduardo C. Costa - Univ. Católica de Pelotas, Pelotas, Brazil Ann Gordon-Ross, Eamonn Keogh, Frank Vahid - Univ. of California,
Jamie Collier - Boston Scientific, Arden Hills, MN
Paulo Flores, Jose Monteiro - INESC - ID / IST, Lisbon, Portugal Riverside, CA
Jeff Siebert - Intel Corp., Folsom, CA,
Justin Wenck - Univ. of California, Davis, CA 38.4s Behavior and Communication Co- Edna Barros - UFPE, Recife, Brazil
Bicky Zhou - Intel Corp., Santa Clara, CA Optimization for Systems with Sequential 39.4s High-Performance Operating System Controlled
Communication Media Memory Compression
37.3 Systems for Human Powered Mobile Computing Lei Yang - Northwestern Univ., Evanston, IL
Joseph Paradiso - Massachusetts Institute of Tech., Cambridge, MA Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang -
Haris Lekatsas - NEC-Labs America, Princeton, NJ
Univ. of California, Los Angeles, CA Robert P. Dick - Northwestern Univ., Evanston, IL
37.4 Harvesting Aware Power Management
for Sensor Networks 38.5s Synthesis of High-Performance Packet 39.5s A Cost-Effective Implementation of an ECC-Protected
Aman Kansal, Jason Hsu, Mani Srivastava- Univ. of California, Los Processing Pipelines Instruction Queue for Out-of-Order Microprocessors
Angeles, CA Cristian Soviani - Columbia Univ., New York, NY Vladimir Stojanovic, Iris Bahar, Jennifer L. Dworak - Brown Univ.,
Vijay Raghunathan - NEC-Labs America, Princeton, NJ Ilija Hadzic - Lucent Technologies, Murray Hill, NJ Providence, RI,
Richard Weiss - Evergreen State College, Olympia, WA 33
Stephen A. Edwards - Columbia Univ., New York, NY
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S - denotes short paper
ß - denotes best paper candidate
b - session of special interest to designers
- indicates videoed session

SESSION 40 Rm: 306/308 SESSION 41 Rm: 307 SESSION 42 Rm: 305

PANEL: TOMORROW’S ANALOG: NANOTUBES AND NANOWIRES SIMULATION ASSISTED FORMAL VERIFICATION
JUST DEAD OR JUST DIFFERENT? Chair: Sankar Basu - NSF, Arlington, VA Chair: Andrew Piziali - Cadence Design Systems, Inc., Parker, TX
Chair: Georges Gielen - Katholieke Univ., Leuven, Belgium Organizers: Igor L. Markov, Krishnendu Chakrabarty Organizers: Harry Foster, Richard Ho
Organizer: Rob A. Rutenbar Nanotechnology holds promise for higher device densities and The papers in this session utilize simulation to improve the results
With the ongoing trend towards more and more digitization in lower fabrication costs. This session covers analysis of ballistic of formal verification, both for model checking and for equivalence
applications ranging from multimedia to telecommunications, there CNFETs, design of reconfigurable nano-CMOS, as well as crossbar- checking. One paper explores the verification of a serial protocol
is a big debate about whether there will remain a need for analog based nano-FPGAs. and bridge, one paper describes a technique for finding very long
circuits in scaled technologies. Analog circuits do not seem to take counter-examples (bugs) and our final paper utilizes simulation and
41.1 NATURE: A Hybrid Nanotube/CMOS data mining techniques to discover global constraints that can be
advantage of nanometer CMOS; rather they suffer from it. So if the
question is asked, “Will analog scale?”, you get conflicting opinions. Dynamically Reconfigurable Architecture used in a number of applications.
One camp argues for an almost-all-digital future. Analog/RF content Wei Zhang, Niraj K. Jha - Princeton Univ., Princeton, NJ
42.1 Directed-Simulation Assisted Formal
should be limited, because it’s difficult, expensive, risky, and can be Li Shang - Queen’s Univ., Kingston, ON, Canada
done with DSP. The opposing camp counters that some critical Verification of Serial Protocol and Bridge
41.2 Modeling and Analysis of Circuit Saurav Gorai - Mentor Graphics Corp., Noida, India
circuits simply do not want (or need) to scale, and analog is only
“risky” when you let digital designers do it. So, what is the future Performance of Ballistic CNFET Saptarshi Biswas, Lovleen Bhatia, Praveen Tiwari, Raj S. Mitra -
role of analog circuits in scaled CMOS, and can analog EDA tools Bipul C. Paul - Stanford Univ., Stanford, CA Texas Instruments Inc., Bangalore, India
help in this? Shinobu Fujita, Masaki Okajima - Toshiba Corp., San Jose, CA
42.2 Guiding Simulation with Increasingly
Panelists: Thomas Lee - Stanford Univ., Stanford, CA
Refined Abstract Traces
Shekhar Y. Borkar - Intel Corp., Hillsboro, OR 41.3s Topology Aware Mapping of Logic Functions Kuntal V. Nanshi, Fabio Somenzi - Univ. of Colorado, Boulder, CO
Charles G. Sodini - Massachusetts Institute of Tech., Cambridge, MA onto Nanowire-based Crossbar Architectures
Daniel Saias - STMicroelectronics, Crolles Cedex, France 42.3 Mining Global Constraints for Improving
Wenjing Rao, Alex Orailoglu - Univ. of California at San Diego,
Eric Naviasky - Cadence Design Systems, Inc., San Jose, CA La Jolla, CA Bounded Sequential Equivalence Checking
Robert W. Brodersen - Univ. of California, Berkeley, CA Weixin Wu, Michael Hsiao - Virginia Tech., Blacksburg, VA
Jue-Hsien Chern - Mentor Graphics Corp., Wilsonville, OR Ramesh Karri - Polytechnic Univ., Brooklyn, NY
41.4s A New Hybrid FPGA With Nanoscale
Clusters and CMOS Routing
Reza M. Rad, Mohammad Tehranipoor - Univ. of Maryland,
Baltimore, MD

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denotes short paper - S Thursday July 27, 2006
denotes best paper candidate - ß
session of special interest to designers - b
indicates videoed session -

SESSION 43 Rm: 304 SESSION 44 b Rm: 303 SESSION 45 b Rm: 301

YIELD ANALYSIS AND IMPROVEMENT APPROACHES TO SOFT ERROR MITIGATION DESIGN/TECHNOLOGY INTERACTION
Chair: Evanthia Papadopoulou - IBM Corp., Yorktown Chair: Subashish Mitra - Stanford Univ., Stanford, CA Chair: Jerry D. Hayes - IBM Corp., Essex Junction, VT
Heights, NY Organizers: Dennis Sylvester, Haihua Su Organizer: Sani R. Nassif
Organizers: Fook-Luen Heng, Patrick Groeneveld This session describes new approaches to reducing soft error rates Technology scaling has drastically exacerbated the complexity and
Yield analysis and improvement have gained more attention due to in modern ICs, particularly in combinational logic, but also in amount of data required to achieve productive design/technology
new defect mechanisms in the nano-technology era. The first paper is memory structures. The first paper details a symbolic framework to interaction. This session shows examples of the excellent work
an early attempt to derive a mathematical model to predict yield analyze error susceptibility that then drives selective gate sizing to going on in the DFM community on ensuring the best possible
based on process information. The second paper addresses double via harden the circuit with limited overheads. The second paper coupling between the design and fabrication phases.
insertion during the routing phase. The third paper solves the antenna incorporates shadow gates on highly critical gates to achieve
avoidance problem by considering the actual antenna ratio constraint. radiation hardening with acceptable area and delay penalties. The 45.1 Process Variation Aware OPC with Variational
final paper proposes new content-addressable memory structures Lithography Modeling
43.1 An IC Manufacturing Yield Model Considering to achieve soft error rate improvements. Peng Yu, Sean X. Shi, David Z. Pan - Univ. of Texas, Austin, TX
Intra-Die Variations
44.1 MARS-C: Modeling and Reduction of Soft Errors 45.2 Modeling of Intra-die Process Variations for
Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles Chiang -
in Combinational Circuits Accurate Analysis and Optimization of Nano-
Synopsys, Inc., Mountain View, CA
Natasa Miskov-Zivanov, Diana Marculescu - Carnegie Mellon Univ., scale Circuits
43.2 Novel Full-Chip Gridless Routing Considering Sarvesh Bhardwaj, Sarma Vrudhula, Praveen Ghanta, Yu Cao -
Pittsburgh, PA
Double-Via Insertion Arizona State Univ., Tempe, AZ
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang - National 44.2 A Design Approach for Radiation-Hard Digital
Electronics 45.3s Computation of Accurate Interconnect Process
Taiwan Univ., Taipei, Taiwan, Lumdo Chen, Brian Han - UMC, Hsinchu
Science Park, Taiwan Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi - Texas Parameter Values for Performance Corners
A&M Univ., College Station, TX under Process Variations
43.3 Optimal Jumper Insertion for Antenna
44.3 A Family of Cells to Reduce the Soft-Error-Rate Frank Huebbers - Northwestern Univ., Evanston, IL
Avoidance under Ratio Upper-Bound Ali Dasdan - Yahoo, Sunnyvale, CA
Jia Wang, Hai Zhou - Northwestern Univ., Evanston, IL in Ternary-CAM
Navid Azizi, Farid N. Najm - Univ. of Toronto, Toronto, ON, Canada Yehea Ismail - Northwestern Univ., Evanston, IL
45.4s Standard Cell Characterization Considering
Lithography Induced Variations
Ke Cao, Sorin Dobre - Qualcomm Inc., San Diego, CA
Jiang Hu - Texas A&M Univ., College Station, TX

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S - denotes short paper
ß - denotes best paper candidate
b - session of special interest to designers
- indicates videoed session

SESSION 46 Rm: 306/308 SESSION 47 b Rm: 307 SESSION 48 Rm: 305

PANEL: BUILDING A VERIFICATION TEST PLAN: SPECIAL SESSION: MORE MOORE’S LAW AND FORMAL SPECIFICATION AND VERIFICATION
TRADING BRUTE FORCE FOR FINESSE MORE THAN MOORE’S LAW TESTBENCH GENERATION
Chair: Sharad Malik - Princeton Univ., Princeton, NJ Chair: Igor L. Markov - Univ. of Michigan, Ann Arbor, MI Chair: Michael Theobald - D.E. Shaw Research, New York, NY
Organizer: Francine Bacchini Organizers: Krishnendu Chakrabarty, Niraj Jha Organizers: Alan Hu, Erich Marschner
The pain of functional verification is intensifying. Building the right This session presents a roadmap for nanoscale CMOS (more Moore’s Formal verification today typically involves verification of a design with
verification test plan can reduce this pain – trading brute force for Law) as well as emerging nanoelectronics technologies that offer respect to its specification. This session presents formal methods
finesse – while enabling greater predictability, more aggressive alternatives to CMOS (more than Moore’s Law). The session starts applied to earlier stages of the verification process, including formal
innovation and late stage spec changes made with confidence. Users with an industry perspective on mainstream and near-term CMOS methods for investigating the quality of a specification, and for
and suppliers debate the optimal mix of formal, simulation, hardware technologies. This is followed by an academic perspective on carbon generating testbenches from a specification.
acceleration and emulation, examining ways to ensure new features nanotube interconnects. The last talk in this session will present new
aren’t dropped pre-tapeout from “inadequate verification”. developments in the design of nonvolatile memories. 48.1 Formal Analysis of Hardware Requirements
Panelists: Ingo Pill - Graz Univ. of Tech., Graz, Austria
47.1 Electronics Beyond Nano-scale CMOS Simone Semprini, Roberto Cavada, Marco Roveri, - ITC Irst, Povo, Italy
Doron Stein - Cisco Systems, Inc., Netanya, Israel Shekhar Y. Borkar - Intel Corp., Hillsboro, OR Roderick Bloem - Graz Univ. of Tech., Graz, Austria
Raj S. Mitra - Texas Instruments Inc., Bangalore, India 47.2 Are Carbon Nanotubes the Future of VLSI Alessandro Cimatti - ITC Irst, Povo, Italy
Janick Bergeron - Synopsys, Inc., Ottawa, ON, Canada
Interconnections? 48.2 Cancelled
Harry D. Foster - Mentor Graphics Corp., Addison, TX
Andrew Piziali - Cadence Design Systems, Inc., Parker, TX Kaustav Banerjee, Navin Srivastava - Univ. of California,
Catherine Ahlschlager - Sun Microsystems, Inc., Sunnyvale, CA Santa Barbara, CA 48.3 Test Generation Games from Formal
47.3 The Zen of Nonvolatile Memories Specifications (start time: 11:00 am)
Erwin Prinz - Freescale Semiconductor, Inc., Austin, TX Ansuman Banerjee, Bhaskar Pal, Sayantan Das, Abhijeet Kumar,
Pallab Dasgupta - Indian Institute of Tech., Kharagpur, India

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denotes short paper - S Thursday July 27, 2006
denotes best paper candidate - ß
session of special interest to designers - b
indicates videoed session -

SESSION 49 Rm: 304 SESSION 50 b Rm: 303 SESSION 51 b Rm: 301

SPECIAL SESSION: KEY TECHNOLOGIES FOR
ANALYSIS AND OPTIMIZATION ISSUES IN NoC DESIGN BEYOND THE DIE ANALOG DESIGN AND DESIGN ASSISTANCE
Chair: Petru Eles - Linkoping Univ., Linkoping, Sweden Chair: Peng Li - Texas A&M Univ, College Station, TX
Organizers: Joerg Henkel, Radu Marculescu Chair: Mike Heimlich - Applied Wave Research, Pelham, NH Organizers: Helmut Graeb, Rob A. Rutenbar
Networks-on-Chip (NoCs) is one of the promising solutions for future Organizer: Lei He This session presents a mix of design case studies, design automation and
multi-billion MPSoCs. To design such systems, the optimization of the SIP (system-in-package) may reduce costs compared to SoC for design assistance techniques for several difficult mixed-signal circuits and
communication infrastructure plays a crucial role. The papers selected heterogeneous integration. The first two papers discuss package- systems. The first paper presents a new low-power ADC that is the winner
for this session cover a broad range of techniques and optimization aware SoC design and system integration using silicon as carrier. of the 2006 DAC-ISSCC student design contest. The second paper deals
metrics which can support various communication scenarios. The first The next two papers present high-speed links between chips in with application of optimization in LNA design, while the third paper presents
two papers improve the on-chip network performance by keeping the CMOS and optical technologies, respectively. a non-optimization design migration aid applied to a bias cell and a crystal
resource utilization low. More precisely, link scheduling and flow-control oscillator. The fourth paper presents how to maintain model consistency
are exploited as means to optimize the overall network behavior. The 50.1 The Importance of Adopting a Package-Aware during the design of a multi-mode multi-band transceiver front-end.
last two papers present novel on-chip routing techniques which are Chip Design Flow
51.1 A 10.6mW/0.8pJ Power-Scalable 1GS/s 4b ADC in
meant to improve the resource utilization and provide support for fault- Kaushik Sheth, Egino Sarto, Joel McGrath - Rio Design
tolerant operation in presence of transient and permanent faults. By 0.18um CMOS with 5.8GHz ERBW
Automation, Inc., Santa Clara, CA
attending this session, the audience will get a deep insight into the most Pierluigi Nuzzo - Univ. of Pisa, Pisa, Italy
stringent issues in communication-centric design that system designers 50.2 Silicon Carrier for Computer Systems Geert Van der Plas - IMEC, Leuven, Belgium
have to deal with in tomorrow’s complex MPSoCs. Chirag Patel - IBM Corp., Yorktown Heights, NY Fernando De Bernardinis - Univ. of Pisa, Pisa, Italy
50.3s 4.25 GB/S Laser Driver: Design Challenges Liesbet Van der Perre, Bert Gyselinckx - IMEC, Leuven, Belgium
49.1 Optimal Link Scheduling on Improving Best-Effort Pierangelo Terreni - Univ. of Pisa, Pisa, Italy
and Guaranteed Services Performance in Network- and EDA Tool Limitations
51.2 SoC-LNA: Synthesis and Optimization for Fully
on-Chip System Benjamin J. Sheahan - Stanford Univ., Stanford, CA
Integrated Narrow-Band CMOS Low Noise Amplifiers
Lap Fai Leung, Chi Ying Tsui - Hong Kong Univ. of Science & Tech., Hong John W. Fattaruso, Jennifer Wong, Karlheinz Muth - Texas Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud - Rice Univ., Houston, TX
Kong, Hong Kong Instruments Inc., Dallas, TX
49.2 Prediction-based Flow Control for Networks-on- Boris Murmann - Stanford Univ., Stanford, CA 51.3s Chameleon ART: A Non-Optimization Based
Chip Traffic Analog Design Migration Framework
50.4 Power-Centric Design of High-Speed I/O Sherif Hammouda - Mentor Graphics Corp., Cairo, Egypt
Umit Y. Ogras, Radu Marculescu - Carnegie Mellon Univ., Pittsburgh, PA Hamid Hatamkhani - Univ. of California, Los Angeles, CA Hazem Said - Ain Shams Univ., Cairo, Egypt
49.3s A Multi-Path Routing Strategy with Guaranteed In- Frank Lambrecht - Rambus, Inc., Mountain View, CA Mohamed Dessouky, Mohamed Tawfik - Mentor Graphics Corp., Cairo, Egypt
Order Packet Delivery and Fault-Tolerance for Vladimir Stojanovic - Massachusetts Institute of Tech., Cambridge, MA Quang Nguyen - ON Semiconductor France SAS, Toulouse, France
Networks on Chip Chih-Kong Ken Yang- Univ. of California, Los Angeles, CA Wael Badawy - Univ. of Calgary, Calgary, AB
Srinivasan Murali - Stanford Univ., Stanford, CA Hazem Abbas - Mentor Graphics Corp., Cairo, Egypt
David Atienza Alonso - LSI-EPFL, Lausanne, Switzerland Hussein Shahein - Ain Shams Univ., Cairo, Egypt
Luca Benini - Univ. of Bologna, Bologna, Italy 51.4s Ensuring Consistency During Front-End Design Using
Giovanni De Micheli - EPFL, Lausanne, Switzerland an Object-Oriented Interfacing Tool Called NETLISP
49.4s DyXY - A Proximity Congestion-Aware Deadlock- Michael Goffioul - IMEC, Leuven, Belgium
Free Dynamic Routing Method for Network-on-Chip Gerd Vandersteen - Vrije Universiteit Brussels, Brussels, Belgium
Ming Li, Qing-An Zeng, Wen-Ben Jone- Univ. of Cincinnati, Cincinnati, OH Joris Van Driessche, Björn Debaillie, Boris Come - IMEC, Leuven, Belgium
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S - denotes short paper
ß - denotes best paper candidate
b - session of special interest to designers
- indicates videoed session

SESSION 52 Rm: 306/308 SESSION 53 Rm: 307 SESSION 54 Rm: 305

HIGH-PERFORMANCE SIMULATION OF NANO- AND BIO-CHIP DESIGN LOGIC AND SEQUENTIAL SYNTHESIS
TRANSACTION LEVEL AND DATAFLOW MODELS Chair: Ion Mandoiu - Univ. of Connecticut, Storrs, CT Chair: Maciej Ciesielski - Univ. of Massachusetts, Amherst, MA
Chair: Felice Balarin - Cadence Berkeley Labs, Berkeley, CA Organizers: Igor L. Markov, Niraj Jha Organizers: Adam Donlin, Jean Christophe Madre,
Organizers: Adam Donlin, Andres R. Takach, Luciano This session presents chip design techniques for nano- and bio- Malgorzata Marek-Sadowska
Lavagno, Sandeep Shukla technologies. The first paper leverages thermodynamics to select Papers in this section address a broad spectrum of topics in logic
High-performance simulation is a crucial requirement for ESL. The first two appropriate base pairs in DNA-driven self-assembly. The next two synthesis. The first paper incorporates logic synthesis into the design
papers in this session address rapid simulation and throughput-driven papers offer new design techniques for microfluidic biochips. The flow of large asynchronous control circuits obtained from high-level
optimization of buffer sizes in dataflow models. The remaining papers discuss final paper in this session describes a 3D carbon nanotube specifications. The next three papers address various aspects of
three advanced SystemC ESL topics. The first is a generic approach to capacitor. clock period optimization. The last paper proposes an approach to
Transaction Level Modeling. The second layers multiple models of gate sizing for binning yield optimization.
53.1 Design Automation for DNA Self-Assembled
computation over the native SystemC kernel. Finally, a UML-SystemC 54.1 State Encoding of Large Asynchronous
modeling tool with full roundtrip capability is presented. Nanostructures
Constantin Pistol, Alvin Lebeck, Chris L. Dwyer - Duke Univ., Controllers
52.1 Efficient Simulation of Critical Synchronous Dataflow Graphs Durham, NC Josep Carmona, Jordi Cortadella - Univ. Politécnica de Catalunya,
Chia-Jui Hsu - Univ. of Maryland, College Park, MD Barcelona, Spain
Suren Ramasubbu - Agilent Technologies, Inc., Palo Alto, CA 53.2 Automated Design of Pin-Constrained Digital
Ming-Yung Ko - Univ. of Maryland, College Park, MD Microfluidic Arrays for Lab-on-a-Chip 54.2 An Efficient Retiming Algorithm under Setup
Jose Luis Pino - Agilent Technologies, Inc., Palo Alto, CA Applications and Hold Constraints
Shuvra S. Bhattacharyya - Univ. of Maryland, College Park, MD William L. Hwang, Fei Su, Krishnendu Chakrabarty - Duke Univ., Chuan Lin, Hai Zhou - Northwestern Univ., Evanston, IL
52.2 Exploring Tradeoffs in Buffer Requirements and Durham, NC 54.3s Extensive Slack Balance: An Approach
Throughput Constraints for Synchronous Dataflow Graphs to Make Front-end Tools Aware of
53.3s Placement of Digital Microfluidic Biochips
Sander Stuijk, Marc Geilen, Twan Basten - TU Eindhoven, Eindhoven, Netherlands
Using the T-tree Formulation Clock Skew Scheduling
52.3 GreenBus - A Generic Interconnect Fabric for
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang - National Kui Wang, Lian Duan, Xu Cheng - Peking Univ., Beijing, China
Transaction Level Modeling
Taiwan Univ., Taipei, Taiwan 54.4s Budgeting-Free Hierarchical Design Method
Wolfgang Klingauf, Robert Guenzel - TU Braunschweig, Braunschweig, Germany
Oliver Bringmann, Pavel Parfuntseu - FZI Forschungszentrum Informatik, 53.4s A High Density, Carbon Nanotube Capacitor for Large Scale and High-Performance LSIs
Karlsruhe, Germany for Decoupling Applications Yuichi Nakamura - NEC Corp., Kawasaki, Japan
Mark Burton - GreenSocs, Cambridge, UK Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Mitsuru Tagata - NEC Corp., Hakusan, Japan
52.4s A Framework for Embedded System Specification Roy - Purdue Univ., West Lafayette, IN Takumi Okamoto - NEC Corp., Kawasaki, Japan
under Different Models of Computation in SystemC Shigeyoshi Tawada, Ko Yoshikawa - NEC Corp., Fuchu, Japan
Fernando Herrera, Eugenio Villar - Univ. of Cantabria, Santander, Spain 54.5 Variability Driven Gate Sizing for
52.5s A Model Driven Design Environment for Embedded Systems Binning Yield Optimization
Elvinia Riccobene - Univ. of Milan, Crema, Italy Azadeh Davoodi, Ankur Srivastava - Univ. of Maryland, College
Patrizia Scandurra - Univ. of Catania, Catania, Italy
Sara Bocchio, Alberto Rosti - STMicroelectronics, Agrate Brianza, Italy Park, MD
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denotes short paper - S Thursday July 27, 2006
denotes best paper candidate - ß
session of special interest to designers - b
indicates videoed session -

SESSION 55 b Rm: 304 SESSION 56 b Rm: 303 SESSION 57 Rm: 301

LOW-POWER CIRCUIT DESIGN BEYOND-THE-DIE CIRCUIT AND SYSTEM NEW IDEAS IN ANALOG/RF MODELING AND
Chair: Ali Keshavarzi - Intel Corp., Hillsboro, OR INTEGRATION SIMULATION
Organizers: Naehyuck Chang, Trevor Mudge Chair: Shauki Elassaad - Emergent Design Solutions, Chair: Luca Daniel - Massachusetts Institute of Tech.,
This session addresses various techniques related to low-power Santa Clara, CA Cambridge, MA
circuit design ranging from Elmore models for energy estimation, Organizers: John Berrie, Mike Heimlich Organizers: Koen Lampaert, Rob A. Rutenbar
variation-aware SRAM cell or dynamic gates design, to standard The first two papers cover performance, power and temperature Accurate macromodeling and fast simulation remain two of the
cell leakage power optimization and low-power bus encoding. tradeoffs in 3D integrated circuit design, from architecture and circuit highest priorities for all working analog designers. This session
55.1 Elmore Model for Energy Estimation in RC points of view. The third paper addresses efficient high-density escape presents new ideas in both modeling and simulation, targeting a
routing. The final two papers are concerned with system-level high- range of difficult and important circuits. The first paper presents a
Trees speed signal and power integrity, including pre-emphasis and novel decomposition strategy for building nonlinear cell-level analog
Quming Zhou, Kartik Mohanram - Rice Univ., Houston, TX equalisation analysis. macromodels. The second paper develops a new technique for
55.2 Self-Calibration Technique for Reduction of efficient extraction of phase macromodels for digitally controlled
56.1 A Thermally-Aware Performance Analysis of Vertically oscillator circuits. The third paper describes new, robust envelope-
Hold Failures in Low-Power Nano-scaled Integrated (3D) Processor-Memory Hierarchy following methods for RF circuits. The final paper describes new
SRAM Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy table-lookup methods for very fast simulation and statistical
Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Sherwood, Kaustav Banerjee - Univ. of California, Santa Barbara, CA modeling of sigma-delta designs.
Kaushik Roy - Purdue Univ., West Lafayette, IN
56.2 Exploring Compromises Among Timing, Power 57.1 A Multilevel Technique for Robust and Efficient
55.3 A Novel Variation-Aware Low-Power Keeper and Temperature in Three-Dimensional Extraction of Phase Macromodels of Digitally
Architecture for Wide Fan-in Dynamic Gates Integrated Circuits Controlled Oscillators
Hamed F. Dadgour - Univ. of California, Santa Barbara, CA Hao Hua, Chris Mineo, Kory Schoenfliess, Ambarish Sule, Samson Xiaolue Lai, Jaijeet Roychowdhury - Univ. of Minnesota, Minneapolis, MN
Rajiv Joshi - IBM Corp., Yorktown Heights, NY Melamed, Ravi Jenkal, Rhett Davis, - North Carolina State Univ., Raleigh, NC
Kaustav Banerjee - Univ. of California, Santa Barbara, CA 57.2 Systematic Development of Nonlinear Analog
56.3 Efficient Escape Routing for Hexagonal Array Circuit Macromodels through Successive
55.4s Standard Cell Library Optimization for of High Density I/Os Operator Composition and Nonlinear
Leakage Reduction Rui Shi, Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA Model Decoupling
Saumil S. Shah - Univ. of Michigan, Ann Arbor, MI
Puneet Gupta, Andrew B. Kahng - Blaze DFM, Inc., Sunnyvale, CA 56.4s System Level Signal and Power Integrity Analysis Ying Wei, Alex Doboli - State Univ. of New York, Stony Brook, NY
Methodology for System-In-Package Applications 57.3 A Robust Envelope Following Method Applicable
55.5s Low-Power Bus Encoding Using An Adaptive
Rohan Mandrekar, Krishna Bharath, Krishna Srinivasan, Ege Engin, to Both Non-Autonomous and Oscillatory Circuits
Hybrid Algorithm Madhavan Swaminathan - Georgia Institute of Tech., Atlanta, GA
Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu, Qinru Qiu - Ting Mei, Jaijeet Roychowdhury - Univ. of Minnesota, Minneapolis, MN
Binghamton Univ., Binghamton, NY 56.5s PELE: Pre-Emphasis and Equalization Link Estimator 57.4 Lookup Table Based Simulation and Statistical
to Address the Effects of Signal Integrity Limitations Modeling of Sigma-Delta ADCs
William Bereza, Yuming Tao, Shoujun Wang, Rakesh Patel, Tad Guo Yu, Peng Li - Texas A&M Univ., College Station, TX
Kwasniewski - Altera Corp., Kanata, ON, Canada 39
43rdDAC-2C 7/3/06 9:16 AM Page 40

Thursday July 27, 2006 All speakers are denoted in bold

S - denotes short paper
ß - denotes best paper candidate
b - session of special interest to designers
- indicates videoed session

SESSION 58 Rm: 306/308 SESSION 59 Rm: 307 SESSION 60 Rm: 305

ADVANCED METHODS FOR INTERCONNECT PANEL: DFM WHERE’S THE PROOF OF VALUE? BOUNDED MODEL CHECKING AND
EXTRACTION, CLOCKS AND RELIABILITY Chair: Joe Brandenburg - Consultant, Portland, OR EQUIVALENCE VERIFICATION
Chair: Arvind NV - Texas Instruments Inc., Bangalore, India Organizers: Linda Marchant, Shishpal Rawat Chair: Gagan Hasteer - Calypto Design Systems, Inc.,
Organizers: Farid N. Najm, Nagaraj NS How can design teams employ new techniques and still stay within Santa Clara, CA
This session covers clock skew minimization, parallel matrix compression design budgets? How much effort does it require to be an early Organizers: Anmol Mathur, Avi Ziv
for parasitic extraction and reliability design methods for NBTI and gate adopter? How does a design engineer get measurable results to This session groups two papers on equivalence checking with two
oxide reliability. The first paper covers a new formulation of clock skew compensate for his effort? The discussion uses the example of a fixed papers on bounded property checking. One equivalence paper
minimization that uses a quadratic programming approach and considers design budget and timeline, and panelists discuss how their tools fit compares very high-level descriptions to RTL, and the other extracts
subcritical skews in addition to the most critical skews. The next paper into that budget and what the ROI (monetary, quality, reduced time- RTL from transistor models of FPGAs. The bounded property
describes a parallel implmentation of the low-rank compression with to-market, comprehensive yield enhancement) would be. checking papers propose automatic heuristics for guiding BDD-based
linear cost reduction capacity with respect to the number of processors. Panelists: state-space exploration and deriving invariants to improve model
Static and dynamic NBTI modeling and design methods to mitigate the Joseph Sawicki - Mentor Graphics Corp., Wilsonville, OR checking efficiency.
NBTI effects are presented. In the final paper, a new dynamic reliability
management scheme is described to balance the increasing throughput Andrew B. Kahng - Blaze DFM, Inc., Sunnyvale, CA 60.1 Early Cutpoint Insertion for High-Level Software
during periods of peak computational demand while ensuring the Atul Sharan - Clear Shape Technologies., Inc., Sunnyvale, CA vs. RTL Formal Combinational Equivalence
required reliability lifetime. Naeem Zafar - Pyxis Technology, Inc., Santa Clara, CA Verification
Mike Gianfagna - Aprio Technologies, Inc., Santa Clara, CA Xiushan Feng, Alan J. Hu - Univ. of British Columbia, Vancouver,
58.1 Clock Buffer and Wire Sizing Using Sequential
Raul Camposano - Synopsys, Inc., Santa Clara, CA BC, Canada
Programming
Matthew R. Guthaus, Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI 60.2s Transistor Abstraction for the Functional
Richard B. Brown - Univ. of Utah, Salt Lake City, UT Verification of FPGAs
58.2 Modeling and Minimization of PMOS NBTI Effect Guy Dupenloup, Thierry Lemeunier, Roland Mayr - Altera Corp.,
for Robust Nanometer Design San Jose, CA
Rakesh Vattikonda, Yu Kevin Cao, Wenping Wang - Arizona State
Univ., Tempe, AZ 60.3s Automatic Invariant Strengthening to Prove
Properties in Bounded Model Checking
58.3s A Parallel Low-Rank Multilevel Matrix
Compression Algorithm for Parasitic Extraction of Mohammad H. Awedh, Fabio Somenzi - Univ. of Colorado,
Electrically Large Structures Boulder, CO
Chuanyi Yang, Swagato Chakraborty, Dipanjan Gope, Vikram 60.4 Fast Falsification Based on Symbolic Bounded
Jandhyala - Univ. of Washington, Seattle, WA Property Checking
58.4s Reliability Modeling and Management in Dynamic Prakash M. Peranandam, Pradeep K. Nalla, Juergen Ruf, Roland J.
Microprocessor-Based Systems Weiss, Thomas Kropf, Wolfgang Rosenstiel - Univ. of Tuebingen,
Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge - Univ. of Tuebingen, Germany
Michigan, Ann Arbor, MI
40
43rdDAC-2C 7/3/06 9:16 AM Page 41

All speakers are denoted in bold

denotes short paper - S Thursday July 27, 2006
denotes best paper candidate - ß
session of special interest to designers - b
indicates videoed session -

SESSION 61 Rm: 304 SESSION 62 Rm: 303

TEST RESPONSE COMPACTION AND ATPG PLACEMENT

Chair: Anuja Sehgal - Advanced Micro Devices, Inc., Chair: Bill Halpin - Synplicity, Inc., San Jose, CA
Sunnyvale, CA Organizers: Jiang Hu, Louis Scheffer
Organizers: Kazumi Hatayama, Patrick Girard This session focuses on new placement techniques for integrated
Increasing circuit complexity and new test methods for deep- circuits. Included are a new method for floorplan repair after changes,
submicron defects make the test data volume grow to an intractable improved approaches to cell flipping, and a new technique for timing
size. After compressing the test stimuli, the current research wave driven incremental placement.
addresses compaction of test responses. The last paper is an example
of a new test method addressing deep-submicron defects. 62.1 Constraint-Driven Floorplan Repair
Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack
61.1 Unknown-Tolerance Analysis and Test-Quality - Univ. of Michigan, Ann Arbor, MI
Control for Test Response Compaction Using 62.2 Optimal Cell Flipping in Placement and
Space Compactors Floorplanning
Mango Chia-Tso Chao, Tim Cheng - Univ. of California, Santa Chiu-Wing Sham, Evangeline Young - Univ. of Hong Kong, Hong
Barbara, CA Kong, China
Seongmoon Wang, Srimat T. Chakradhar, Wen-long Wei - NEC-Labs Chong-Nuen Chu - Iowa State Univ., Ames, IA
America, Princeton, NJ
62.3 A New LP Based Incremental Timing Driven
61.2 Test Response Compactor with
Placement for High Performance Designs
Programmable Selector
Tao Luo - Univ. of Texas, Austin, TX
Grzegorz Mrugalski, Janusz Rajski - Mentor Graphics Corp., David Newmark - Advanced Micro Devices, Inc., Austin, TX
Wilsonville, OR David Z. Pan - Univ. of Texas, Austin, TX
Jerzy Tyszer - Poznan Univ. of Tech., Poznan, Poland
61.3s Fault Detection and Diagnosis with Parity Trees
for Space Compaction of Test Responses
Harald Vranken, Sandeep K. Goel - Philips Research Labs, Eindhoven,
Netherlands
Andreas Glowatz, Juergen Schloeffel, Friedrich Hapke - Philips
Semiconductors, Hamburg, Germany
61.4s Multiple-Detect ATPG Based on Physical
Neighborhoods
Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, Ronald D.
Blanton - Carnegie Mellon Univ., Pittsburgh, PA
41
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Tutorials - Monday, July 24

TUTORIAL 1 - ESL DESIGN METHODOLOGY USING SYSTEMC TUTORIAL 2 - PRACTICAL ASPECTS OF COPING WITH
VARIABILITY: AN ELECTRICAL VIEW
Rm: 305
Rm: 304
Organizer: Francine Bacchini - ThinkBold Corporate Communications, San Jose, CA
Presenters: Wolfgang Rosenstiel - Univ. of Tuebingen, Tubingen, Germany Organizer: Chandu Visweswariah - IBM Corp., Yorktown Heights, NY
Jack Donovan - ESLX, Inc., Austin, TX Presenters: Xi-Wei Lin - Synopsys, Inc., Mountain View, CA
Maurizio Vitale - Philips Semiconductors, Pittsburgh, PA Bora Nikolic - Univ. of California, Berkeley, CA
Laurent Maillet-Contoz - STMicroelectronics, Crolles, France Peter A. Habitz - IBM Corp., Burlington, NC
Mike Meredith - Forte Design Systems, San Jose, CA Riko Radojcic - Qualcomm CDMA Technologies, San Diego, CA
Vincent Viteau - Summit Design, Inc., Cedex, France This comprehensive tutorial on the electrical aspects of variability will be presented by leading
This tutorial is ideally suited to System Architects, Software Architects and Developers, and industry practitioners and academic researchers. Emphasis will be placed on practical
Hardware Design and Verification engineers. The aim of this electronic system-level (ESL) techniques and methodologies for analyzing and dealing with variability. The tutorial will consist
design methodology tutorial is to communicate to adopters and prospective adopters of ESL of four main sections:
design the primary considerations involved in the establishment of an architecture-to- 1) The tutorial begins with understanding exactly where the variability is coming from and
implementation design, verification, optimization and debug methodology, including embedded classifying the sources of variability into systematic and random effects.
software development.
2) The second section focuses on test and characterization structures for both logic and array
The use and re-use of transaction-level models (TLM) formulated in the SystemC language will applications, and how to reflect variability in timing and power models, including speculation
be described and assessed in the context of their application to (1) architectural development on emerging statistical timing model standards.
and optimization, (2) early software development, (3) hardware and hardware/software
verification, and (4) hardware implementation. 3) The next section is a practical introduction to statistical timing and optimization techniques,
with a focus on timing methodology considerations to cope with variability while reducing
This tutorial will begin with an overview of the use models, followed by a "how to" exposition timing pessimism.
on the development of the virtual system platform (VSP) for early embedded software
development. Two designers with ESL design methodology expertise – from 4) The final section will concentrate on deployment of both physical and electrical DFM
STMicroelectronics and Philips – will then recount their experience in its use, offering practical solutions and present a taxonomy of available DFM tools and the corresponding
development and deployment tips. The tutorial will then discuss implementation methodologies into which they fit.
methodologies. The tutorial will conclude with an example of an ESL design, verification and This is a unique opportunity to learn about the latest developments from the experts!
debug flow from architecture to RTL, followed by Q&A.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Tutorials - Friday, July 28

TUTORIAL 3 - REAL DFM SOLUTIONS, TOOLS, TUTORIAL 4 - SURVIVING AND THRIVING IN THE WORLD
METHODOLOGIES, AND SUCCESSES OF CHIP AND PACKAGE CO-DESIGN
Rm: 304 Rm: 305
Organizer: Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA Organizers: Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA
Presenters: Nagaraj NS - Texas Instruments Inc., Dallas, TX Howard Chen - IBM Corp., Yorktown Heights, NY
Jean-Pierre Schoellkopf - STMicroelectronics, Crolles, France Presenters: Paul Harvey - IBM Corp., Austin, TX
Mike Smayling - Applied Materials, Sunnyvale, CA Howard Chen - IBM Corp., Yorktown Heights, NY
Ban P. Wong - Chartered Semiconductor, Milpitas, CA Lei He - Univ. of California, Los Angeles, CA
Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA
Topics include: (i) Today's stress on "geometric DFM" over "electrical DFM", which misses out Kaushik Sheth - Rio Design Automation, Inc., Santa Clara, CA
on value propositions such as performance robustness and more rapid power/timing closure. Beyond the die, it takes a holistic approach to tackle the design problems at the package, board,
(ii) Benefits from statistical design (which requires new infrastructure for modeling, IP, signoff and system levels. This tutorial will begin with an overview of the emerging packaging technologies
and tool infrastructure) versus benefits from "variation-aware design" (which exploits a link to and their impact on chip performance. Then we will provide a comprehensive list of simple, but
the fab but is otherwise compatible with today's design and signoff flows). (iii) Opportunities often overlooked, design methods to help tutorial attendees get the most out of today's new
for new "design synergy" – uniformity, structure, compensation, etc. – that can dramatically packaging technologies. We will explain how statistical techniques can be employed to ensure that
improve yield and manufacturability. the design will work over the entire tolerance range without resorting to conservative and very
Entering the 65nm node, today's DFM tools attempt to satisfy several basic objectives. To expensive over-design practices. We will also discuss competing design objectives such as
address the failure of "WYSIWYG" in sub-100nm process nodes, "shape" (x-y dimension) and electrical, thermal, mechanical, reliability, and manufacturability requirements and illustrate co-
"thickness" (z dimension) simulation technologies are being deployed. To address design methods with numerous examples. The co-modeling of chip/package power distribution
"uncontrollable variation", statistical analysis technologies (SSTA, statistical extraction, etc.) are design will be presented to analyze and minimize transient power supply noise due to clock gating,
being investigated. And, well-established internal technologies for defect-oriented yield analysis power gating, frequency scaling, and other power management activities. We will describe the key
(critical area, pattern hotspot finding) and optimization (via/contact doubling, wire spreading, components in a chip and package co-design flow with emphasis on package-aware chip I/O
etc.) are being commoditized. The order of tool deployment has been as one would expect: planning, structure-preserved model order reduction for large number of ports, and power
(1) geometric criteria (through process window hot-spots, etc.) before electrical criteria integrity optimization with power domain partitioning and decoupling capacitor insertion. In
(leakage, timing variation, etc.); (2) library and IP development use models before full-chip use addition, we will explore the scalability of the technologies and present advanced design
models; and (3) analyses before optimizations. techniques such as active and passive compensation for low-power and high-speed interconnect.
Finally, this tutorial will highlight the short-term and long-term implications of ignoring the
relationship between the chip, package and PCB. We will describe an effective means of bridging
the gap between the designs of high-performance chips and packages, and a chip's integration with
the rest of the electronic system. By adopting such a package-aware chip design flow, we can
ensure design convergence and eliminate the ad-hoc iteration between chip and package designs.
43
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Tutorials - Friday, July 28

TUTORIAL 5 - SYSTEMVERILOG: LANGUAGE TUTORIAL AND TUTORIAL 6 - TOOLS FOR HYBRID EMBEDDED SYSTEMS:
INDUSTRIAL VERIFICATION EXPERIENCE MODELING, VERIFICATION, AND DESIGN
Rm: 307 Rm: 302
Organizer: Johny Srouji - IBM Corp., Austin, TX Organizer: Luca Carloni - Columbia Univ., New York, NY
Presenters: Johny Srouji - IBM Corp., Austin, TX Presenters: Hilding Elmqvist - Dynasim AB, Lund, Sweden
Karen Pieper - Synopsys, Inc., Sunnyvale, CA George Pappas - Univ. of Pennsylvania, Philadelphia, PA
Tom Fitzpatrick - Mentor Graphics Corp., Groton, MA Pieter J. Mosterman - The MathWorks, Inc., Natick, MA
John Havlicek - Freescale Semiconductor, Inc., Austin, TX Alessandro Pinto - Univ. of California, Berkeley, CA
Matt Maidment - Intel Corp., Portland, OR Alberto Sangiovanni-Vincentelli - Univ. of California, Berkeley, CA
Cliff Cummings - Sunburst Design Inc., Portland, OR This tutorial gives a detailed overview of the current landscape of tools for the specification,
With the ever-increasing complexity of electronic systems and processors in the industry as design, and validation of hybrid embedded systems.The basic principles of hybrid systems
driven by performance and functionality, design and verification are becoming more complex. (systems that feature both continuous and discrete time components) modeling will be
As designs become packed with greater functionality and verification takes up more of the presented as the common theoretical underpinning for all the tools. The core of the tutorial
overall schedule, there is a need for a standard language to support all aspects of the design and will be live demonstrations of about a dozen tools that have been developed in the industry and
verification process. SystemVerilog was developed to extend the Verilog HDL, the predominant academia.
language used for chip design for many years, specifically to address these needs. For each tool, a brief presentation of its syntactic and semantic characteristics will be followed by
This tutorial will provide a detailed overview of the IEEE 1800 SystemVerilog Hardware Design a practical exposition of how to use it to model and design some simple, but challenging "running
and Verification Language (HDVL), including practical examples of industrial experience using examples", thereby showing its advantages and limitations. This will provide a sound mechanism
the language to develop complex designs. The tutorial will include a thorough description of the to compare the tools by illustrating their differences in terms of expressiveness, usability, power,
SystemVerilog definition, intent and potential while covering the design modeling, testbench and performance. Some industrial examples will be modeled, presented, and discussed.
automation, verification, assertions aspects of the language, and the programming interfaces.
The practical sessions will include discussions of what has worked well, the impact on design
and verification productivity and transition experiences from Verilog to SystemVerilog, as well
as suggestions of possible future directions for the language.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Tutorials - Friday, July 28

TUTORIAL 7 - FROM BASIC TO ADVANCED TECHNIQUES
FOR SILICON DEBUG AND DIAGNOSIS
Rm: 306/308
Organizer: Srikanth Venkataraman - Intel Corp., Hillsboro, OR
Presenters: Srikanth Venkataraman - Intel Corp., Hillsboro, OR
Miron Abramovici - DAFCA Inc., Framingham, MA
Robert Aitken - ARM, Sunnyvale, CA
• Design error diagnosis, silicon debug and defect diagnosis ranging from the basic concepts
to advanced applications and new DFD techniques.
• Established diagnosis procedures including fault dictionaries, post-test fault simulation, and
back tracing.
• Methods for locating defects such as opens, shorts, and leakage in transistor-level circuits,
approximation techniques for identifying unmodeled faults, Iddq-based diagnosis, diagnosis
for delay-faults, scan-chain diagnosis, test compression-based diagnosis BIST-based diagnosis,
and design-for-diagnosability techniques.
• Silicon debug techniques, design-for-debug techniques, and error location procedures.
• Diagnosis for yield learning application and feedback for DFM techniques.
• Successful debug and diagnosis methods used in real industrial products, industrial
experiences, and case studies.

45
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

UML for SoC Design Workshop

Sunday, July 23 • 9:00 am - 6:00 pm Rm: 302
REGISTRATION The program of the third workshop on the Unified Modeling Language™ (UML) Sreeranga Rajan, Chair of the UML-SoC profile Standardization Committee at
INSTRUCTIONS for System-on-a-Chip (SoC) design includes papers from design teams and the Object Management Group™ (OMG), will open the workshop and provide
Workshop registration researchers around the globe. UML is attracting growing interest as a system the latest information about this standard extension to UML for SoC
is required. level visual language to support the tasks of specifying, analyzing, designing, and development. Other presentations will explore embedded system analysis,
$100 ACM/IEEE Members verifying SoCs. The UML for SoC Design Workshop is meant to coordinate design, modeling, synthesis, and design flows supported by UML. The workshop
$150 Non-Members efforts, to initiate discussions, and to exchange experiences/information related is open to anyone interested in learning more about UML for SoC Design.
to UML applied to SoC design and hardware aspects. A keynote by Dr.
9:00 Welcome and Introduction by the Workshop Organizers 12:30 Lunch - Rm: 304
Y. Vanderperren - Katholieke Univ., Leuven, Belgium Session 3: UML and SoC Languages
J. Wolfe - Mentor Graphics Corp., Mobile, AL
2:00 Automatic Generation of Verification Properties for SoC Design from
9:15 Keynote - UML for SoC: Where, When, and How?
SysML-Diagrams
Sreeranga P. Rajan - Fujitsu Labs, Sunnyvale, CA
Stefan Laemmermann, Roland Weiss, Juergen Ruf, Thomas Kropf,
Session 1: Systems Modeling with UML
9:45 UML Modeling and Configuration of Tile Based Networks-on-Chip Wolfgang Rosenstiel - Univ. of Tuebingen, Germany
Subhek Garg, Marcello Lajolo - NEC, Princeton, NJ 2:30 SoC, UML and MDA - An Investigation
10:15 UML-Based Modeling of Time-triggered Applications Maha Ramanan - Philips Semiconductors, Southampton, UK
Kathy Dang Nguyen, Geoffrey Koh, P.S. Thiagarajan, Weng-Fai 3:00 A SoC Design Flow Based on UML 2.0 and SystemC
Wong - Univ. of Singapore, Singapore Alberto Rosti, Sara Bocchio - STMicroelectronics, Milano, Italy
10:45 Coffee Break Elvinia Riccobene - Univ. of Milano, Milano, Italy
Session 2: UML-based SoC Design Space Exploration Patrizia Scandurra - Univ. of Catania, Catania, Italy
11:00 Multi-objective Design Space Exploration Based on UML 3:30 Coffee break and tool demos
Marcio F. da S. Oliveira, Eduardo Brião, Francisco Nascimento, Session 4: Models of Computations and UML for SoC
Lisane Brisolara, Luigi Carro, Flávio Wagner - Federal Univ. of Rio Grande 4:00 Stereotyping for Register-level SoC Custom Logic Kernel Design:
do Sul, Porto Alegre, Brazil Integrating Algorithmic State Machines into UML
11:30 A UML-Based Design Flow and Partitioning Methodology for James P. Davis, Achraf El Allali, Bryan D. Young, Salman Ali - Univ. of
Dynamically Reconfigurable Systems South Carolina, Columbia, SC
Chih-Hao Tseng, Pao-Ann Hsiung - National Chung-Cheng Univ., Taiwan, 4:30 Towards a Unified Behavioral Language
Republic of China Wolfgang Mueller, Henning Zabel - C-LAB, Paderborn, Germany
12:00 Design Space Exploration Through Interactive Model Mappings Session 5: Workshop Discussion
for UML-based Specifications 5:00 Challenges with UML-Based SoC Design and State-of-the-Art Solution
Tim Schattkowsky - C-LAB, Paderborn, Germany Y. Vanderperren - Katholieke Univ., Leuven, Belgium
Achim Rettberg - Paderborn Univ., Paderborn, Germany J. Wolfe - Mentor Graphics Corp., Mobile, AL
Rainer Doemer - Univ. of California, Irvine, CA 6:00 Workshop Wrap-up
46
43rdDAC-2C 7/3/06 9:16 AM Page 47

The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Second Integrated Design System Workshop

Monday, July 24 • 12:00 pm - 5:00 pm Rm: 303
Organizers: John Darringer - IBM Corp. Rahul Goyal - Intel Corp. Alva Barney - Hewlett-Packard Co. Scott Peterson - LSI Logic Corp. Bill Bayer - Si2

Objective - The era of "point tools" linked by files is long over. Streamlined This workshop brings together design system managers and design system providers
integrated design systems are essential to meet today's business demands. Custom from the industry’s leading companies to assess the state of integrated design systems
chip designers require them to integrate growing numbers of macros while insuring today, identify the top challenges remaining, discuss the potential solutions in the
manufacturability. ASIC and SoC designers must have them to optimize multiple pipeline as well as those that are likely, just over the horizon. What new directions
factors simultaneously to achieve "design closure". Product designers need them to will integrated design systems move into next? What gains in productivity can be
exploit 3DIC and SiP package synergy and remain competitive. expected?
What does it take to develop these effective integrated design systems? Vendors Each session will include a panel to probe deeper into the topics presented and allow
provide solutions for parts of a methodology, but most users want to exploit the best your questions to be addressed and your comments be heard.
tools from multiple vendors and add proprietary applications to gain a competitive
advantage. Progress has been made on standard APIs for sharing data, but much more REGISTRATION INSTRUCTIONS
Workshop registration is required.
is needed to enable design systems to keep pace with the industry. $50.00 - ACM/IEEE Members • $75.00 - Non-Members

12:00 pm Lunch 3:00 pm Part 2: Tomorrow’s Opportunities

1:00 pm Part 1: Today’s Challenges and Solutions Moderator: Richard Goering - EE Times, Ben Lomond, CA
Moderator: Scott Peterson - LSI Logic Corp., Bloomington, MN 3:30 pm What are the Next Critical Areas to Address?
1:20 pm What are the Most Important Challenges for Integrating Evolution of an Integrated Design System
Design Systems Today? • Yoshi Inoue - Renesas Tech. Corp., Tokyo, Japan
• Thomas Harms - Infineon Technologies AG, Munich, Germany System-Level Design
• Philippe Magarshack - STMicroelectronics, Crolles Cedex, France • Pat Sheridan - CoWare, Inc., San Jose, CA
• Rahul Goyal - Intel Corp., Santa Clara, CA Design for Manufacturability
1:50 pm What is Coming to Address These Challenges? • Juan-Antonio Carballo - IBM Corp., Austin, TX
• Antun Domic - Synopsys, Inc., San Jose, CA System in Package and 3D ICs
• Ted Vucurevich - Cadence Design Systems, Inc., San Jose, CA • Bill Price - Philips Semiconductor, San Jose, CA
• George Janac - Silicon Navigator, Inc., Cupertino, CA IP Modeling
2:20 pm PANEL – What are the Top Priorities and • John Goodenough - ARM, Sunnyvale, CA
When Will They Be Fixed? 4:20 pm PANEL: What Major Advances are Likely to Happen in the
Panel members selected from previous speakers. Next 4 Years?
3:00 pm Break Panel members selected from previous speakers.
5:00 pm Adjourn 47
43rdDAC-2C 7/3/06 9:16 AM Page 48

The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Workshop for Women in Design Automation

REGISTRATION INSTRUCTIONS
Working the 80/20 Rule for Success - Focusing in on What Matters Workshop registration is required.
$50.00 ACM/IEEE Members
Monday, July 24 • 9:00 am - 12:45 pm Rm: 302
$75.00 Non-Members

The workshop's accomplished keynote speaker and panelists will provide insights these talented women "cracked the code" and learned how to focus on the 20%
into how to work the 80/20 rule for success. Showcasing their own real life that mattered and enabled them to achieve the 80% results for career success and
examples and providing practical suggestions, workshop attendees will learn how work/life balance.
Workshop Chair: Daya Nadamuni - Chief Analyst and Research VP, Gartner Dataquest (pictured) SCHEDULE
Workshop Vice Chair: Sabina Burns - Sr. Director, Corp Marketing and Communications, Virage Logic Corp. 9:00 am -10:00 am Continental Breakfast and Registration
Steering Committee: 10:00 am -12:15 pm Keynote Speaker and Panel Discussion
Nanette Collins - Publicity Chair, 43rd DAC 12:15 pm -12:45 pm Award Ceremony
Marie R. Pistilli - Co-Chair, Board of Directors, MP Associates, Inc. 12:45 pm - 1:45 pm Lunch Reception
Telle Whitney - President, Anita Borg Institute for Women & Technology
Keynote Reynette Au - Vice President Business Licensing, NVIDIA Corp.
Reynette Au joined NVIDIA as Vice President of Business Licensing in November 2005. was president and Chief Executive Officer for Triscend Corp., which was sold to
With more than 20 years of management experience in the semiconductor industry, she Xilinx Inc. in 2004; and Vice President, Marketing for ARM, where under her direction,
is responsible for building the company's IP licensing business and positioning it as a the company significantly expanded the brand awareness of its popular microprocessor
complementary and strategic partnership-building model across all NVIDIA businesses. solutions and firmly established its market position as 'The Architecture for the Digital
Before joining NVIDIA, Reynette was Vice President, Marketing for Stretch Inc., World'. She also held operational and program management positions at AMD and
the industry's first company to embed programmable logic within processor AT&T Microelectronics. Reynette earned a Bachelor of Science in Computer Science
architecture to create a unique, software-configurable solution. Prior to this, she (BSCS) degree from the University of Denver.

Panel Discussion Moderator: Sabina Burns - Virage Logic Corp.

Don't miss the opportunity to learn how prominent professionals in the Panelists: Denise Brouillette - The Innovative Edge
industry have made career choices to achieve a rewarding personal and Eillen Sullivan - Cadence Design Systems, Inc.
professional life experience. Each of us has the chance to influence our Kathy Papermaster - IBM Corp.
organization in fundamental ways if we have the tools. Building on the Soha Hassoun - Tufts Univ.
work described in the keynote the panelists will describe their own Sofie Maxwell - City and County of San Francisco
experience about the impact they have made on their organizations. Board of Supervisors - District 10
We are pleased to have panelists from companies and organizations of
Supported by:
very different sizes, product lines and focus. You can expect to walk
away with concrete examples of changes that work.
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Introduction to Chips and EDA

for a Non-Technical Audience
Monday, July 24 • 10:00 am - 12:00 pm Rm: 301

How do they cram all those functions into that little cell phone? Will the next portable music Organizer
player be so small that you can't see it? Squeezing more features into the electronic products Pamela McDaniel - Synopsys, Inc.
we use every day means the electronics inside are getting more complex. Electronic Design
Automation (EDA) makes this happen! Speaker
If you are new to the EDA or chip industry or have been in the industry for a while and want Karen Bartleson - Synopsys, Inc., Mountain View, CA
to get a little closer to technology, this workshop is for you. It will give you, the non-technical
professional, a basic understanding of chip design and the amazing world of Electronic Design REGISTRATION INSTRUCTIONS
Automation. Workshop registration is required. • $10.00 - Registration fee.

This workshop provides: Workshop objectives:

• A simplified explanation of how chips are designed and manufactured • Provide a basic understanding of EDA and semiconductors to non-technical people
• An understanding of how essential EDA is to chip design • Present information in simple, easy-to-understand terms
• An opportunity to see and touch the parts that make up chips and electronic products • Use hands-on parts (wafers, chips, masks…) for enhanced experience
• A non-threatening, fun event with working knowledge to take away • Encourage people to join and invest in the EDA industry
• Address ongoing requests to help non-technical people understand the EDA industry
This workshop is for:
• Non-engineering staff from technology companies Please note:
• Analysts and media people unfamiliar with EDA and semiconductor industries This workshop is similar to the one presented at DAC 2005.
• Educators and students who are curious about chip technology and design automation The workshop is for non-technical attendees.
• Friends and relatives of technical people Maximum class size: 50

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Hands-on Tutorials
General Information Analysis and Optimization of Low Power Designs
Hands-on Tutorials are three-hour tutorials presented by exhibitors to demonstrate their Presented By: Apache Design Solutions, Inc.
solutions to a particular issue. This year DAC is offering seven hands-on tutorials on Low Monday, July 24 9:00 am - 12:00 pm Rm: 309
Power Design. Demonstrations are done with the attendees working from workstations while As designs move to deep-sub-micron technologies, lowered supply voltage, reduced noise
the presenters lead the discussion. The tutorials are limited to the first 30 attendees with a margins, and increasing leakage power necessitates extensive verification and analyses prior to
student to workstation ratio of 2:1. Due to the proprietary nature of the discussions, tape-out. This tutorial provides hands-on experience in analysis and optimization of designs
presenting companies have the right to refuse access to employees or contractors of
utilizing power-gating (MTCMOS) technology, a common low-power design technique for leakage
competitors. The cost per tutorial is $75 and attendees are encouraged to enroll in more than
one tutorial. Attendees must register for a minimum of an exhibits only registration in order control. The tutorial will use RedHawk-LP, Apache's full-chip dynamic power sign-off solution for
to be eligible to enroll in a Hands-on Tutorial. low-power designs, to accurately analyze the behavior of their power-gated designs, including full-
chip power-up and mixed-mode analysis. You will explore and determine the ideal timing intervals
for ramp-up, as well as add or remove power-gating switches for optimal design performance. The
tutorial will discuss the different operating modes of a power-gated design, and how a block
transitioning from one state to another impacts the performance of other blocks in the design. In
this tutorial, you will gain the hands-on experience needed to better understand and manage your
low-power designs.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Hands-on Tutorials
Using Virtual System Prototypes to Optimize Architectures for Low Power Design Using Predictive Development - Atrenta
Low Power and Other Key Attributes Solution in Action on a Next-Generation 3G Cell Phone Chip
Presented By: VaST Systems Technology, StarCore LLC Presented By: Atrenta Inc., Freescale Semiconductor, Inc.
Monday, July 24 2:00 pm - 5:00 pm Rm: 310 Tuesday, July 25 2:00 pm - 5:00 pm Rm: 309
Learning Objectives: With the rapid growth of mobile and wireless applications, power management on chips has
become a critical design factor. In an effort to minimize power consumption on a chip,
1. Review the challenges of software dominated, multi processor, embedded systems engineers use power management techniques during design implementation in order to
development and the need to embrace innovative ways to optimize the architecture reduce dynamic and leakage power consumption. The power dimension to design closure
for key constraints such as low power adds significant design challenges besides the usual concerns over functionality, performance
2. Learn how Virtual System Prototype (VSP) driven development makes it easier to and die size.
optimize complex SoC designs while also improving time to market and quality This hands-on tutorial focuses on predictive development techniques to create designs that
3. Explore how to construct a VSP with general purpose and/or digital signal processor + are low-power-aware from early design stages. Predictive development is Atrenta's new class
interconnect fabric and then learn how this is used to: of design automation solutions that turn the costly and error-prone activity of electronic
• Experiment with candidate architectures with respect to architectural constraints development into a more predictable, manageable and reliable process.
• Understand how to automatically create empirical data to be used to optimize Atrenta's SpyGlass LP™ provides a comprehensive set of low-power design techniques in
SoC designs order to address gated clock domains, multiple voltage domains, and power-down regions
that may be present in a typical low power design. For example, the use of multiple voltage
• Experience how the VSP can go on to be used as a golden reference model for the
domains requires that signals crossing the voltage domain boundaries are level-shifted
concurrent development of software and hardware
appropriately. The use of power-domains in power-sensitive designs requires that certain
signals are isolated correctly under the power-down condition. The presence of multiple
voltage and power domains leads to complex power and ground connectivity issues on the
chip that needs to be checked.
This tutorial walks the user through the application of these techniques using SpyGlass LP on
a representative design. The tutorial also covers a "real-life" customer experience using the
Atrenta solution of a next generation cell phone chip at Freescale Semicondutor, Inc.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Hands-on Tutorials
Low Power by Using a Clockless Design Style Reduce Leakage Power and Increase Battery Life by
Presented By: Handshake Solutions Implementing an Ideal Vt Selection Strategy
Wednesday, July 26 9:00 am - 12:00 pm Rm: 309 Presented By: Prolific Inc., ARM
Handshake Technology is a clockless circuit style without the traditional centralized Wednesday, July 26 2:00 pm - 5:00 pm Rm: 309
synchronous clock signal. Handshake Solutions offers access to this unique and proven Do you run place-and-route? Do you use a multi-V_t library? Do you care about leakage
technology through design tools, standard IP blocks and design services. We recently power? Two leakage power reduction methods make sense for every design: proper library
announced the clockless ARM996HS with nearly a factor three power reduction compared to selection during place-and-route; and final-pass optimization to refine threshold voltage (V_t )
its clock-gated counterpart. Also, a production proven ultra low-power 80C51 cell selection from a multi-V_t library.
microcontroller subsystem is available for licensing. This tutorial provides an overview of how cell design and block design contribute various
Advantages of Handshake Technology based circuits are ultra low-power, low EMI and low components of power, and describes importance of cell selection on final quality of results.
peak currents. Our technology relies on an extremely disciplined design style, which allows The tutorial also examines the advantages and tradeoffs of running place-and-route tools using
safe design of self-timed (asynchronous) circuits. This unique silicon compilation approach puts all low-V_t cells, all high-V_t cells, or mixed-V_t cells.
the advantages of self-timed circuits in the hands of any designer. During this hands-on tutorial, Participants will run Prolific’s ProPower product, using ARM Physical IP Libraries and
the participants will be able to work with our design tools and experience how our high-level Synopsys’ PrimeTime, to minimize leakage power. This method takes a fully placed-and-routed
design entry language allows them to easily tryout different design alternatives. It also shows design, previously optimized by other leakage power reduction tools, and guarantees 25% to
how high-level decisions influence important design aspects, like area, speed and power. 70% improvement without impacting area, TNS, WNS, or active power of the design.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Hands-on Tutorials
Low Power and Power Management Design Using Multi-Voltage Low Power Design - Designer's Perspective
Design and Verification Tools Presented By: Virage Logic, Cadence Design Systems, Inc.,
Presented By: ArchPro Design Automation, Inc. Sandbridge Technologies
Thursday, July 27 9:00 am - 12:00 pm Rm: 309 Thursday, July 27 2:00 pm - 5:00 pm Rm: 309
Power management is no longer a clock gating play. Complex SoCs need multiple voltage Power reduction is becoming a mainstream requirement that is affecting most designs at
frequency points and multiple sleep states to deliver the best power-performance metrics. 90nm and below. Typical low power design techniques such as clock gating and mixed-Vt
Voltage represents the most fundamental and effective control on power and peformance of optimization are not adequate enough, calling for more aggressive power reduction methods.
CMOS. However, there is a small problem: existing EDA tools and design languages do not deal In addition to impacting design implementation and library development, aggressive power
with variable voltage. The IC industry is rapidly adopting multi-voltage designs of various styles, saving techniques also affects testability and functional verification. This tutorial will
but the EDA tools are just emerging. Further, many IC designers themselves don't comprehend demonstrate how an actual low power design requirement can be met by taking a design
that they are adopting multi-voltage and end up missing the complexity of their IC. through implementation.
Attendees will take an example dual-tone multi-frequency design through physical
This tutorial explores the following topics (with live examples). implementation using the Cadence® Encounter® digital IC design platform low power design
1. What are the various styles of multi-voltage designs and their implications? flow and Virage Logic Ultra-Low-Power Semiconductor IP. Advanced power reduction
a. How are power/performance tradeoffs made. techniques such as multiple supply voltages to reduce power consumption in lower
2. How does multi-voltage change the design flow? performance blocks and power gating to shut off idle blocks for dramatic power reduction
will also be highlighted.
3. How to verify a multi-voltage design? How do you measure coverage?
a. Common multi-voltage errors and how to debug them
4. How to automate the implementation of a multi-voltage design?
5. Voltage rules and their application all through the design flow
6. Impact on DFT, libraries and IP.

ArchPro tools along with industry standard tools will be used in the live exercises.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Sponsors
The 43rd Design Automation Conference is sponsored by IEEE/CASS /CANDE/CEDA (Institute • Opportunity to read and review papers, write articles and participate in the Society's
of Electrical and Electronics Engineers/Circuits and Systems Society), the ACM/SIGDA government
(Association for Computing Machinery/Special Interest Group on Design Automation), and the • And all the personal and professional benefits of IEEE/CASS /CANDE membership
EDA Consortium (Electronic Design Automation Consortium). Membership information is
Computer Aided Network Design (CANDE)
available on the sponsors web site or at the conference at the ACM and IEEE booths.
is a joint technical committee of the IEEE Circuits and Systems Society and the Council on
IEEE Circuits and Systems Society Electronic Design Automation. CANDE is dedicated to bringing design automation
The IEEE Circuits and Systems Society (CASS) is one of the largest societies within IEEE and professionals together to further their education, to assist in building relationships, and to
in the world devoted to the analysis, design, and applications of circuits, networks, and sponsor initiatives which grow the CAD/EDA industry. CANDE sponsors a workshop in the
systems. It offers its members an extensive program of publications, meetings and technical Fall to address emerging technologies and to provide an opportunity for the generation of new
and educational activities, encouraging an active exchange of information and ideas. The ideas. CANDE is the sponsoring technical committee from CASS for both DAC and ICCAD.
Society's peer reviewed publication activities include: Trans. on CAD; Trans. on CAS-Part I
For more information, please contact the IEEE/CASS/CANDE.
(Regular Papers); Trans. on CAS-Part II (Express Briefs); Trans. on VLSI; Trans. on CAS for
Video Technology; Trans. on Multimedia; and the new Transactions on Mobile Computing Mail: IEEE/CASS
which is co-sponsored with IEEE sister societies. CASS also sponsors or co-sponsors a 445 Hoes Ln.
number of international conferences, which include the Design Automation Conference Piscataway, NJ 08854
(DAC), the Int'l Conference on Computer-Aided Design (ICCAD) and the Int'l Symposium on Phone: 732-465-5853
Circuits and Systems (ISCAS). A worldwide comprehensive program of advanced workshops Email: [email protected]
including a new series on "Emerging Technologies in Circuits and Systems", as well as our Web: www.ieee-cas.org
continuing education short courses bring to our worldwide membership the latest The Council on Electronic Design Automation (CEDA)
developments in cutting-edge technologies of interest to industry and academia alike. The The Council on Electronic Design Automation (CEDA) is an IEEE Council recently formed by the
IEEE/CASS has been serving its membership for over 50 years with such member benefits as: IEEE Technical Activities Board. CEDA aims to bring together the EDA-related activities that run
• Discounts on all Society publications, conferences and workshops (including co- through many of the IEEE's societies, conferences and workshops. CEDA's responsibilities include
sponsored and sister society publications and conferences) sponsorship of several conferences and publications, such as ICCAD, DAC, and the Transactions
• The Society Magazine which includes articles on emerging technologies, society news and on CAD and the sponsorship of a Distinguished Speaker Series. Members of CEDA include the
current events IEEE Antennas and Propagation, Computer, Circuits and Systems, Electron Devices, Microwave
• Opportunities to network with peers and experts within our 17 focused committee Theory and Techniques, and Solid State Circuits Societies. For more information on CEDA or to
meetings, the local events of over 60 chapters and more than 20 annual sign up for CEDA newsletters, go to www.ieee-ceda.org.
conferences/workshops
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Sponsors
ACM/SIGDA -The Resource for EDA Professionals The Association for Computing Machinery (ACM)
ACM/SIGDA (Special Interest Group on Design Automation) has a long history of supporting ACM is an educational and scientific society uniting the world's computing educators,
conferences and the EDA profession. In addition to sponsoring DAC, SIGDA sponsors researchers and professionals to inspire dialogue, share resources and address the field's
ICCAD, DATE, and ASP-DAC, plus approximately 15 smaller symposia and workshops. challenges. ACM strengthens the profession's collective voice through strong leadership,
SIGDA provides a broad array of additional resources to our members, to students and promotion of the highest standards, and recognition of technical excellence. ACM supports
professors, and to the EDA profession in general. SIGDA organizes the University Booth and the professional growth of its members by providing opportunities for life-long learning,
Ph.D. Forum at DAC and the CADathlon at ICCAD, and funds various scholarships and career development, and professional networking. For more information, please visit
awards (including the IEEE/ACM William J. McCalla ICCAD Best Paper Award). Other http://www.acm.org
benefits provided to SIGDA members include the SIGDA's E-Newsletter (containing
information on upcoming conferences and funding opportunities), emailed to SIGDA The ACM Digital Library and Guide to Computing Literature are the definitive online
members twice each month. The SIGDA E-Newsletter also includes SIGDA News which resources for computing professionals. Richly interlinked, they provide access to ACM's
highlights most relevant events in EDA and semiconductor industry and the NEW "What collection of publications and bibliographic citations from the universe of published computing
is...?" column that brings to the attention of EDA professionals the most recent topics of literature. http://www.acm.org/dl
interest in design automation. Additionally, ACM has 34 Special Interest Groups (SIGs) that focus on different computing
SIGDA has pioneered electronic publishing of EDA literature, beginning with the DA Library disciplines. More than half of all ACM members join one or more of these Special Interest
in 1989, which captured 25 years of EDA literature onto an archival series of CDROMs. In Groups. The SIGs publish newsletters and sponsor important conferences such as
the early 1990s, SIGDA published the first EDA conference proceedings on CDROMs, and SIGGRAPH, OOPSLA, DAC, SC and CHI, giving members opportunities to meet experts in
now produces CDROM proceedings for most of the major EDA conferences and symposia their fields of interest and network with other knowledgeable members.
each year. SIGDA also produces an annual DVD Compendium of those proceedings, and http://www.acm.org/sigs
more recently, Multimedia Monographs based on talks at DAC and ICCAD. Finally, SIGDA
provides strong support for the ACM journal TODAES (Transactions on Design Automation Become an ACM member today and join thousands of other leading professionals,
of Electronic Systems). researchers and academics who benefit from all ACM has to offer. Join ACM online at
http://www.acm.org, or contact ACM directly by phone: 800-342-6626 (US and Canada) or
For further information on SIGDA's programs and resources, see http://www.sigda.org. In
212-626-0500 (Global), by fax: 212-944-1318, or by e-mail: [email protected].
addition, SIGDA members may also want to consider joining our parent organization, ACM. ACM
membership provides access to a variety of ACM products and resources, including discounts on Hours of operation are from 8:30 am - 4:30 pm Eastern Time.
conferences, subscriptions to ACM journals and magazines, and the ACM Digital Library, an
invaluable IT resource. For further details, see ACM's home page at http://www.acm.org.
As an EDA professional, isn't it time YOU joined SIGDA? 55
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Sponsors/Univ. Booth/Proceedings
SIGDA/DAC University Booth 43rd DAC Proceedings
Each year SIGDA organizes the University Booth. The booth is an opportunity for university The 43rd DAC proceedings will contain nearly 200 papers, panels, and special sessions. DAC
researchers to display their results and to interact with visitors from industry. Priority is given is offering each conference and student registrant 43 years of DAC proceedings on DVD. One
to presentations that complement the conference technical program. Demos that highlight hardbound copy of this year's proceedings will be available to registrants for $50 at the time
benchmark results are also encouraged. The Design Contest winners, DAC speakers, and PhD of registration. If you wish to purchase additional copies, you may do so at the ACM kiosk
Forum participants are invited to give demonstrations presenting their work at the University located in the North Hall on the exhibit floor level via self-help on-line computer orders. After
Booth. The schedule of presentations will be published at the conference and will also be the conference, mail orders should be sent to ACM or IEEE. The addresses for mail orders
available on the SIGDA web site. We thank the Design Automation Conference for its are:
continued support of this project. ACM Order Department IEEE Service Center
EDA Consortium PO Box 11414 445 Hoes Ln.
New York, NY 10286-1414 Piscataway, NJ 08854
The EDA Consortium is the international association of companies that provide tools and services Phone: (800) 342-6626 Phone: 800-678-IEEE (US and Canada)
that enable engineers to create the world's electronic products. (US and Canada) or 732-981-1393 (Global)
or 212-626-0500 (Global) Fax: 732-981-1721
EDA Consortium addresses issues that are common to its members and the community they Fax: 212-944-1318 www.ieee.org
serve. Recent accomplishments include simplification of international EDA export regulation and e-mail: [email protected]
publication of an industry Operating Systems Roadmap.
Companies that become EDA Consortium members are eligible for a 10% discount on DAC
Exhibit Space. Visit www.edac.org or call 408-287-3322 today to learn more about EDA
Consortium membership opportunities. Send an email to [email protected] to be added to the
Consortium’s executive event invitation list.

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Awards
Marie R. Pistilli Women in EDA Achievement Award Design Automation Conference Graduate Scholarships
• Ellen J. Yoffa - Director of Next Generation Web, IBM T.J. Watson Research Center, Each year the Design Automation Conference sponsors several $24,000 scholarships to support
Yorktown Heights, NY graduate research and study in Design Automation (DA), with emphasis in "design and test
For her significant contributions in helping women advance in the field of EDA technology. automation of electronic and computer systems". Each scholarship is awarded directly to a
The P.O. Pistilli Undergraduate Scholarships for Advancement in university for the Faculty Investigator to expend in direct support of one or more DA graduate
Computer Science and Electrical Engineering students.
The objective of the P.O. Pistilli Scholarship program is to increase the pool of professionals in The criteria for granting such a scholarship expanded in 1996 to include financial need. The
Electrical Engineering, Computer Engineering, and Computer Science from under-represented criteria are: the academic credentials of the student(s); the quality and applicability of the
groups (women, African American, Hispanic, Native American, and physically challenged). In 1989, proposed research; the impact of the award on the DA program at the institution; and financial
ACM Special Interest Group on Design Automation (SIGDA) began providing the program. need. Preference is given to institutions that are trying to establish new DA research programs.
Beginning in 1993, the Design Automation Conference provided the funds for the scholarship and Prof. Jennifer L. Dworak - Division of Engineering–Electrical Sciences and Computer Engineering,
SIGDA continues to administer the program for DAC. DAC normally funds two or more $4000 Brown University, Providence, RI
scholarships, renewable up to five years, to graduating high school seniors. Student: Elif Alpaslan
The 2006 winners are:
A Statistical Coverage Metric and Stimulus Generation Approach for Design
Katlyn DeLuca - attending University of Massachusetts, Lowell, MA Verification Based upon Structural Analysis of the Design and Stimulus
Eletha Flores - attending Massachusetts Institute of Technology, Cambridge, MA
For more information about the P.O. Pistilli scholarship, contact Dr. Cherrice Traver, ECE
Dept., Union College, Schenectady, NY 12308. email: [email protected] Prof. Daniel Kroening - Computer Systems Institute, Swiss Institute of Technology,
Zurich, Switzerland
DAC/ISSCC Student Design Contest Winners
Student: Vijay D'silva
Operational Chip Design Category: 1st Place (Best Overall)
A 10.6mW/0.8pJ Power-Scalable 1 GS/s 4b ADC in 0.18um CMOS with 5.8GHz ERBW Automatic Detection of Multi-Cycle Paths in Large Circuits
Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni - University of Pisa
Bert Gyselinckx, Liesbet Van der Perre, Geert Van der Plas - IMEC
Information on next year's DAC scholarship award program will be available on the DAC web
site: http://www.dac.com.

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Awards
The ACM Transactions on Design Automation of Electronic Systems IEEE Circuits and Systems Society 2006 Donald O. Pederson Award
(TODAES) 2006 Best Paper Award Embedded Deterministic Test • IEEE Transactions on Computer-Aided Design of
Zero Cost Indexing for Improved Processor Cache Performance • Volume 11, Issue Integrated Circuits and Systems, vol. 23, no. 5, pp. 776-792, May 2004
1, January 2006, Pages 3-25 Janusz Rajski – Mentor Graphics Corp., Wilsonville, OR
Tony Givargis - University of California, Irvine, CA Jerzy Tyszer – Poznan University of Technology, Poznan, Poland
Mark Kassab – Mentor Graphics Corp., Wilsonville, OR
The Association for Computing Machinery/Special Interest Group on
Nilanjan Mukherjee – Mentor Graphics Corp., Wilsonville, OR
Design Automation (ACM/SIGDA) Distinguished Service Award
• Robert A. Walker - Kent State University, Kent, OH IEEE Circuits and Systems Society
For dedicated service as SIGDA Chair (2001 - 2005), and over a decade of service to SIGDA, 2006 CSVT Transactions Best Paper Award
DAC, and the EDA profession Complexity Scalable Motion Compensated Wavelet Video Encoding • IEEE
2005 Phil Kaufman Award for Distinguished Contributions to EDA Transactions on Circuits and Systems for Video Technology, vol. 15, no. 8, pp.
982-993, August 2005
• Phil Moorby - Chief Scientist, Synopsys, Inc. Deepak Srinivas Turaga – Philips Research USA, Briarcliff Manor, NY
Phil Moorby is the recipient of the prestigious EDA Consortium 2005 Phil Kaufman Award for Mihaela van der Schaar-Mitrea – Philips Research USA, Briarcliff Manor, NY
industry contributions as the inventor of the Verilog hardware design language (HDL) which has Beatrice Pesquet-Popescu – Telecom Paris, Paris Cedex 13, France
become, and today remains, one of the world's most popular electronic design languages.
IEEE Circuits and Systems Society
IEEE Circuits and Systems Society 2006 Education Award 2006 VLSI Transactions Best Paper Award
• Wayne Wolf - Princeton University, Princeton, NJ A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies
For outstanding education and leadership in VLSI systems and embedded computing • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13,
IEEE Circuits and Systems Society 2006 Industrial Pioneer Award no. 1, pp. 27-38, January 2005
Amit Agarwal – Intel Corp., Hillsboro, OR
• John A Darringer - IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Bipul C. Paul – Purdue University, West Lafayette, IN
For the development of practical techniques and algorithms for automated logic synthesis, for
Hamid Mahmoodi – San Francisco State University, San Francisco, CA
their realization as usable tools, and for their successful application to high performance
Animesh Datta – Purdue University, West Lafayette, IN
computing products
Kaushik Roy – Purdue University, West Lafayette, IN

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Awards
2006 IEEE Fellows Best Paper Candidates
• Charles Alpert - IBM Corp., Austin, TX Twelve papers were nominated by the Technical Program Committee as a DAC Best Paper
For contributions to physical design automation of very large scale integrated (VLSI) circuits Candidate; six in front-end design and six in back-end design. Final decisions will be made after
• Wolfgang Kunz - University of Kaiserlautern, Kaiserlautern, Germany the papers are presented at the conference. The awards for the best papers, one in front-end
For contributions to hardware verification, very large scale integrated (VLSI) circuit testing design and one in back-end design, will be presented at 12:45 on Thursday, July 27 in the
and logic synthesis Gateway Ballroom, just before the Keynote Address.
• Resve Saleh - University of British Columbia, Vancouver, BC, Canada Session 3.1 A CPPLL Hierarchical Optimization Methodology Considering Jitter,
For contributions to mixed-signal integrated circuit simulation and design verification Power and Locking Time
• Chuan-Jin Richard Shi - University of Washington, Seattle, WA Session 8.1 Charge Recycling in MTCMOS Circuits: Concept and Analysis
For contributions to computer-aided design of mixed-signal integrated circuits
Session 9.1 A Multiprocessor System-on-Chip for Real-Time Biomedical Monitoringand
• Martin Wong - University of Illinois at Urbana-Champaign, Urbana, IL Analysis: Architectural Design Space Exploration
For contributions to algorithmic aspects of computer-aided design (CAD) of very large scale
integrated (VLSI) circuits and systems Session 13.1 Power Grid Physics and Implications for CAD
Session 13.2 Fast Analysis of Structured Power Grid by Triangularization BasedStructure
Preserving Model Order Reduction
Session 14.2 SAT Sweeping Using Local Observability Don't-Cares
Session 19.2 Timing-Based Delay Test for Screening Small Delay Defects
Session 24.1 BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP
Session 28.2 Register Binding for Clock Period Minimization
Session 30.1 Architecture-Aware FPGA Placement using Metric Embedding
Session 31.1 VIRTUS: A New Processor Virtualization Architecture forSecurity-Oriented
Next-generation Mobile Terminals
Session 39.1 A Constraint Network Based Solution to Code Parallelization

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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Student Design Contest

DAC/ISSCC Student Design Contest
The Student Design Contest promotes excellence in the design of electronic systems by fabricated and tested but must have been thoroughly simulated. Students compete for cash
providing a competition for graduate and undergraduate students at universities and colleges. prizes donated by industrial supporters, as well as the DAC conference. winners have been
It is co-organized by ISSCC and DAC. This year we received over 50 submissions in three invited to show their work at the University Booth on the show floor. Awards will be given
categories: Conceptual, Operational Chip, and Operational Systems. Operational designs are at the DAC Pavilion on Wednesday, July 26, 2006 from 10:00 am - 10:45 am. The ceremony
those which have been implemented and tested. Conceptual designs have not yet been will include brief overview presentations from each winning project team.

DAC/ISSCC 2006 Student Design Contest Winners

Operational Chip Design Category: Operational System Design Category:
1st Place A 10.6mW/0.8pJ Power-Scalable 1 GS/s 4b ADC in 0.18um CMOS 1st Place Demonstration of Uncoordinated Multiple Access in Optical Communications
with 5.8GHz ERBW (Best Overall) Herwin Chan, Andres I. Vila Cadaso, Juthika Basak, Miguel Griot, Wen-Yen Weng, Richard Wesel, B.
Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni - University of Pisa Jalali, Eli Yablonovitch- University of California, Los Angeles
Bert Gyselinckx, Liesbet Van der Perre, Geert Van der Plas - I M E C Ingrid Verbauwhede - U n i v e r s i t y of California, Los Angeles and K.U. Leuven, Belgium
(tie) 2nd Place Increasing the Time Dynamic Range of Pulse 2nd Place Illumimote: A High Performance Light Sensor Module
Measurement Techniques in Digital CMOS for Wireless Sensor Networks
Mona Safi-Harb, Gordon W. Roberts - McGill University Heemin Park, Jonathan Friedman, Mani B. Srivastava, Pablo Gutierrez, Vidyut Samanta, Jeff Burke -
University of California, Los Angeles
(tie) 2nd Place A DSP Enabled Microsystem for Cochlear Implants with Hybrid LC Clocking
3rd Place An Ultra Low Power Wireless Micro-Sensor Node
Eric D. Marsman, Robert M. Senger - University of Michigan
Richard B. Brown-U n i v e r s i t y of Utah Denis Daly, Daniel Finchelstein, Nathan Ickes, Naveen Verma, Anantha Chandrakasan - Massachusetts
Institute of Technology
3rd Place A 160K Gates/4.5KB SRAM H.264 Video Decoder for HDTV Applications Honorable Phase Delay Based Collision Avoidance RADAR for Smart Automobiles
Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Chao-Ching Wang, Yi-Huan Ou-Yang, Ming-Chih Mention
Babu L. Saincha - Indian Institute of Information Technology
Tsai, Yao-Chang Yang, Jiun-In Guo, Jinn-Shyan Wang - National Chung ChengUniversity
Award Contributors:
Conceptual Category:
1st Place ASIC Implementation of LDPC Decoder Accelerating
Message-Passing Schedule
Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto - Waseda University

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Additional Meetings
SystemC Technology Symposium CEDA Distinguished Speaker Reception
Monday, July 24 • 12:00 pm - 1:30 pm Rm: 200-212 Monday, July 24 • 5:30 pm - 7:30 pm Rm: 124
The Open SystemC Initiative (OSCI) invites you to learn how recent advancements in CEDA Distinguished Speaker Series, beer/wine/cheese, followed by the TCAD Donald
SystemC apply to you today and moving forward: O. Pederson Best Paper Award winner entitled, Embedded Deterministic Test by
J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee
Hear from industry experts on recent SystemC advancements and using SystemC for
doing real world system-level design. Status updates on the technology roadmap, IEEE Si2 Members Meeting
1666 and TLM will be presented. (complimentary lunch provided) Monday, July 24 • 6:00 pm - 7:30 pm Rm: 111
ACM/SIGDA Symposia/Workshop Leaders Luncheon The annual Silicon Integration Initiative (Si2) Members Meeting will provide an overview and
Monday, July 24 • 12:00 pm - 2:00 pm Rm: 124 status report on Si2 projects, such as the OpenAccess Coalition, the Open Modeling
Coalition, the Design-to-Manufacturing Coalition, the Design Technology Council, the
Organizers of symposia and workshops sponsored by ACM/SIGDA, as well as Liberty TAB, and the LEF/DEF Governing Board. The newly-elected Si2 Board of Directors
ACM/SIGDA volunteers are invited to a lunch get-together. ACM staff and SIGDA Board
will be introduced, and industry trends are explored. Companies considering joining Si2 are
Members will be available for detailing and explaining the steps of starting or organizing
welcome to attend. Refreshments and snacks will be served before and after the meeting.
an event. A brief overview of other new ACM/SIGDA activities will be presented. Please contact Bill Bayer ([email protected]) if you would like to attend.
How Many Engineers Does It Take? The Real Issues in IP
The SPIRIT Consortium General Meeting
Integration
Monday, July 24 • 6:00 pm - 8:00 pm Rm: San Francisco Marriott Hotel
Monday, July 24 • 12:30 pm - 2:00 pm Rm: 111
At DAC 2006, The SPIRIT Consortium will provide a major opportunity to hear about The
Free lunch panel. IP integration and verification is only getting more complex, expensive,
Consortium's specifications and see them applied in practice by multiple users and vendors.
and risky. IP suppliers, integrators, EDA vendors, and foundries must work together in
Please join us to hear presentations on the released specifications, The Consortium roadmap
a streamlined fashion to ensure IP success. But are they? Varying degrees of IP quality and proposed IEEE 1685 standard, and see in-use demonstrations of the specifications. Enjoy
coupled with a host of business and technical issues makes IP integration the key
a brief repast and cocktail hour on behalf of The SPIRIT Consortium! You may register your
challenge in modern SoCs. Don't be left holding the cards with your next chip design.
interest to attend this general meeting by emailing [email protected].
This panel will expose the interrelated and often opposing technical and business issues
surrounding IP integration and explore how this fragmented industry can work together. Synopsys/Sun University Reception
Monday, July 24 • 6:30 pm - 8:30 pm Rm: 228/230
NASCUG Meeting
Monday, July 24 • 2:00 pm - 6:00 pm Rm: 200-212 University professors and students are invited to join Synopsys and Sun Microsystems for an
evening reception including drinks and hors d'oeuvres. Prize drawings will be held throughout
You are invited to the 5th North American SystemC Users Meeting (NASCUG):
the evening and the following keynote presentations will be featured.
Open to DAC attendees, the focus of the NASCUG meeting is on SystemC real-world
The Future is BDA, Dr. Richard Newton, Dean of Engineering, Univ. of California, Berkeley
design methodologies and user experiences. Topics include techniques for integrating
SystemC into the design flow and SystemC tool flows and methodologies. (reception Design For Testability: The Path to Deep Submicron, Tom W. Williams, Synopsys Fellow
starts at 5:00 pm)
Not sure what BDA is? Join us to find out.
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Additional Meetings
Industry Standard IP Protection System for EDA Tool Flows Brion Technology Lunch Seminar
Tuesday, July 25 • 7:30 am - 9:15 am Rm: 302 Tuesday, July 25 • 11:30 am - 2:00 pm Rm: 111
IP Vendors require security; Chip Designers require interoperability across many tools. Two levers that are improving the resolution and manufacturability of ultra sub
Can one methodology satisfy both? This panel will discuss a methodology and its wavelength patterns: one is immersion, the other is improving patterning by
underlying technology that achieves these goals. Panelists from IC vendors, EDA computational lithography. Computational lithography is used to apply and verify pattern
companies, and IP providers will discuss their unique requirements and concerns and proximity corrections and sub-resolution assist features to full-chip layouts - processes
will highlight the flexibility and security necessary for an industry standard methodology such as SRAF placement, model-based RET/OPC and model-based RET/OPC
to emerge. Key panel topics: verification. Re-mapping the problem into an image-based approach allows the
- The underlying technology application of repetitive grid-based calculations to be hard coded in dedicated computing
- IP provider control for the level to which their IP is visible to EDA tools and users boards. The combination of the image-based approach and high speed dedicated
- Advantages of using a non-proprietary encryption mechanism computing hardware is revolutionizing all aspects of model-based RET/OPC.
- EDA vendor requirements
SIGDA Ph. D. Forum/Member Meeting
SPICE and FastSPICE: The Next 25 Years Tuesday, July 25 • 6:30 pm - 8:00 pm Rm: 310
Synopsys Analog Mixed Signal Breakfast Event
Tuesday, July 25 • 7:30 am - 10:00 am Rm: Marriott: Golden Gate Hall Salon B1 SIGDA invites you to attend our annual PhD Forum and Member Meeting. SIGDA
members are invited, as we are all members of the EDA Community. We will begin with
Synopsys invites you to attend Synopsys' Analog Mixed Signal breakfast program on the a presentation of SIGDA's programs and this year’s SIGDA Technical Leadership
future of SPICE and FastSPICE. HSPICE is celebrating it's 25 year anniversary. Come and Awards, but the main focus of the meeting will be the Ph.D. Forum. Aimed at
hear what the industry experts predict the next 25 years have in store for SPICE and strengthening ties between academia and industry, students will present posters and
FastSPICE challenges. For more information and to register visit: discuss their Ph.D. dissertation research with interested attendees. The Ph.D. Forum
http://www.synopsys.com/ams_breakfast gives students feedback on their research, and gives the EDA community a preview of
work in process. Also, light refreshments will be served at 7:30 pm. For more
information, see http://www.sigda.org/daforum.

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Additional Meetings
Escape from Analog Alcatraz through OpenAccess Fourth Annual Hacks and Flacks Roundtable Discussion at DAC
Synopsys Interoperability Breakfast Event Wednesday, July 26 • 3:00 pm - 4:30 pm Rm: 302
Wednesday, July 26 • 7:30 am - 9:30 am Rm: 302 Hours, days and weeks are spent strategizing and agonizing over public relations and
marketing plans. Once plans are finalized, a large amount of money is invested on
Chi-Foon Chan, President/COO of Synopsys, invites you to attend Synopsys' interoperability
implementation. Time, effort and company dollars are spent with the goal of reaching
breakfast. Speakers including Philippe Magarshack, Front-End Technology and Manufacturing “key” customers and gaining the attention of various audiences. BUT…do we? Does our
Group VP and GM of Central CAD and Design Solutions at STMicroelectronics, and Jim
message reach the audience who ultimately makes or breaks the sales decisions? Where
Hogan, Industry Veteran, discuss the benefits and challenges of enabling interoperability for
do your customers get their information? What makes a positive impression on customers
analog and custom design through OpenAccess. Find out who wins the annual Tenzing for EDA and IP products? What direct effect does public relations have on sales and other
Norgay Interoperability Achievement Award. For more information and to register, visit
corporate departments? Please join us for a lively discussion among EDA customers such
www.synopsys.com/interop/breakfast
as Texas Instruments, STMicroelectronics and Atheros Communications along with public
Lessons from the Trenches Real-World ESL Project Experiences relation and marketing professionals to discuss these questions and find out what they
- Are the Advantages Worth the Cost and Effort? read and what media they believe most influences their purchase and investment decisions.
Wednesday, July 26 • 12:00 pm - 2:00 pm Rm: 228 & 230
CANDE Meeting
A panel of users and tools vendors will discuss real world examples of how electronic system Wednesday, July 26 • 6:00 pm - 7:30 pm Rm: 112
level design tools and methodologies are being used today to improve quality, reduce risk
CANDE is a joint Technical Committee on Design Automation for the IEEE Circuits
and improve time-to-market. Issues to be addressed:
and Systems Society (CASS) and the Council on Electronic Design Automation
• The usability of the current generation of ELS tools • The amount of training/support (CEDA). It is the sponsoring committee from CASS and CEDA for both ICCAD and
required to achieve productivity with ESL point tools • What it takes to put together and
DAC. CANDE brings design automation professionals together to build relationships,
support a cost effective • ESL flow • What are the quantifiable benefits of the ESL flow
and to sponsor a workshop and initiatives that improve the CAD/EDA industry. Please
• What has worked/what has not • Next steps in ESL for each panel member's company visit the CANDE website: (http://www.cande.net/) for more information.
For more information or to register contact [email protected]
Birds-of-a-Feather (BOF) Meetings
ACM TODAES Editorial Board Meeting
Wednesday, July 26 • 6:30 pm - 8:00 pm
Wednesday, July 26 • 12:00 pm - 2:00 pm Rm: 112
DAC will provide conference rooms for informal groups to discuss items of common
Annual Editorial Board meeting of the ACM Transactions on Design Automation of
technical interest. These very informal non-commercial meetings, held after hours, are
Electronic Systems (ACM TODAES).
referred to as "Birds-of-a-Feather". All BOF meetings are held at The Moscone Center,
Wednesday, July 26, 6:30 pm - 8:00 pm. DAC will facilitate common interest group meetings
to discuss DA related topics. To arrange a BOF meeting sign up at the Information Desk
located in the lower North Lobby. A room will only be assigned if ten or more people sign
up. An LCD projector and screen will be provided. Check DACnet and the Birds-of-a-
Feather board at the Information Desk.
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

44th Call For Papers

DAC is the premier conference devoted to Design Automation (DA) and the application of DA tools rules, or those previously published or simultaneously under review by another conference, will be
in designing electronic systems. Four types of submissions are invited: regular papers, special topic rejected. DAC will work cooperatively with other conferences and symposia in the field to check for
sessions, panels, and tutorials. Submissions must be made electronically at www.dac.com. R e g u l a r double submissions. Additional submission guidelines are available on the DAC website (after
Papers are due NO later than 5:00 pm MST, November 20, 2006. September 1, 2006). All regular papers will be reviewed as finished papers. Preliminary submissions will
DAC 2007 is seeking papers that deal with design tools, design methods, design techniques, and be at a disadvantage. Authors of accepted papers must sign a copyright release form for their paper.
embedded design in a number of categories described below. Notice of acceptance will be sent via email by March 9, 2007.
Design Tools papers describe contributions to the research and development of design tools and Special session submissions must include descriptions of suggested papers and speakers, and the
their supporting algorithms. importance of the special session to the DAC audience. DAC reserves the right to restructure all
special sessions. Special session submissions are due NO later than 5:00 pm MST,
Design Methods and case studies papers describe innovative methodologies for the design of November 1, 2006
electronic circuits and systems, as well as creative experiences with design automation in state-of-the-
art design projects. Panel and tutorial suggestions should not exceed two pages, should describe the topic and intended
audience, and should include a list of suggested participants. Tutorial suggestions must include a bulleted
Design Papers describe the use of design tools and methods from the perspective of a specific design outline of covered topics. DAC reserves the right to restructure all panel and tutorial proposals.Panel
project. They include a brief description of the design and discussion of: methodology, flow, innovative
and tutorial suggestions are due NO later than 5:00 pm MST, November 1, 2006
use of tools, the limits of current tools, and what new tool capabilities are required for future designs.
Students are invited to submit descriptions of original electronic designs, either circuit level or system level.
Embedded Systems are characterized by mixed hardware and software components with limited Student Design Contest paper submissions must (1) be in PDF format only, (2) contain the title of
resources. Increases in software content introduce new system design issues. Embedded design papers the project, (3) contain an abstract of approximately 60 words, (4) a complete description of the project,
describe tools, methods, and case studies for applications with specific embedded system content. and (5) be no more than 6 pages (including the abstract, maximum of 10 figures/tables and references),
The theme topic for DAC 2007 is automotive electronics, and papers that specifically refer to the double columned, 9pt or 10pt font. The submission should clarify the originality, distinguishing features, and
theme will be highlighted at the conference. measured performance of the design. Three categories of designs - operational, system and conceptual -
Requirements for Submission are eligible for awards. For operational designs, proof-of-implementation is required, while for conceptual
designs, complete simulation and test plan is necessary. Designs must have taken place as part of the
Regular paper submissions MUST (1) be in PDF format only, (2) contain an abstract of
students' work at the university and must have been completed after June 2005. Submitted designs should
approximately 60 words clearly stating the significant contribution, impact, and results of the
not have received awards in other contests. Selected designs will be presented at the conference (and at
submission, (3) be no more than 6 pages (including the abstract, figures, tables, and references), double
ISSCC in February 2007). Additional contest rules are available on the DAC web site. Student Design
columned, 9pt or 10pt font, and (4) MUST NOT include name(s) or affiliation(s) of the author(s)
Contest submissions are due NO later than 5:00 pm MST, December 6, 2006
anywhere on the manuscript or abstract, and any references to the author(s)’s own previous work or
affiliations in the bibliographic citations must be in the third person. Format templates are available on ALL SUBMISSIONS MUST BE MADE ELECTRONICALLY AT THE
64 the DAC web site for your convenience, but are not required. Submissions not adhering to these DAC WEB SITE: WWW.DAC.COM
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

44th Call For Papers

Submitters are required to specify a category from the 18 7. High-Level Synthesis 14. Analog/Mixed-Signal and RF
listed below. 7.1 High-level, behavioral, algorithmic, and architectural synthesis, “C” 14.1 Analog, mixed-signal, and RF design methodologies
to gates tools and methods 14.2 Automated synthesis and macromodeling
1. System-Level Design and Co-Design 7.2 HW-SW interface synthesis, communication and network synthesis 14.3 Analog, mixed-signal and RF simulation and optimization
1.1 System specification, modeling, simulation, and performance analysis 7.3 Synthesis of digital circuits above the RTL level
1.2 Scheduling, HW-SW partitioning 15. FPGA Design Tools and Applications
7.4 Resource scheduling, allocation, and synthesis 15.1 Rapid prototyping
1.3 IP and platform-based design, IP protection 8. Beyond Die-Integration and Package/Hybrid/Board Design
1.4 System-on-Chip (SoC) and Multi-processor SoC (MPSoC) 15.2 Logical synthesis and physical design techniques for FPGAs
8.1 Chip-package-board codesign 15.3 Configurable and reconfigurable computing
1.5 Application-specific processor design tools 8.2 System-in-Package, 3D design, stacked devices
2. System-Level Communication and Networks on Chip 16. Testing
8.3 Beyond-the-die communication, high-speed I/O, optical communication 16.1 Test quality and reliability, nanometer technology test, current-
2.1 Modeling and performance analysis 8.4 Analysis and optimization (signal integrity, physical layout, simulation)
2.2 Communications-based design based test
beyond the die 16.2 Digital fault modeling, automatic test pattern generation
2.3 Architectural synthesis, mapping, routing, scheduling 9. Logic Synthesis and Circuit Optimization
2.4 Optimization for energy, fault-tolerance, reliability 16.3 Digital design-for-test, test data compression, built-in self test
2.5 Interfacing and software issues 9.1 Combinational, sequential, and asynchronous logic synthesis 16.4 Memory test and repair, FPGA testing
2.6 NoC Design methodologies and CAD flows, case studies and prototyping 9.2 Library mapping, cell-based design and optimization 16.5 Fault tolerance and on-line testing
3. Embedded HW Design and Applications 9.3 Transistor and gate sizing and resynthesis 16.6 Analog/mixed-signal/RF testing
3.1 Case studies of embedded system design 9.4 Interactions between logic design and layout or physical synthesis 16.7 Board- and system-level test
3.2 Flows and methods for specific applications and design domains 10. Circuit Simulation and Interconnect Analysis 16.8 Silicon debug, post-silicon design validation
4. Embedded SW Tools and Design 10.1 Electrical-level circuit simulation 17. New, Emerging, or Specialized Design Technologies,
4.1 Retargetable compilation 10.2 Model-order reduction methods for linear systems including but not restricted to
4.2 Memory/cache optimization 10.3 Interconnect and substrate modeling and extraction
10.4 High-frequency and electromagnetic simulation of circuits 17.1 MEMS, sensors, actuators, imaging devices
4.3 Real-time single- and multi-processor scheduling, linking, loading 17.2 Nano-technologies, nano-wires, nano-tubes
4.4 Real-time operating system 10.5 Thermal and electrothermal simulation
11. Timing Analysis and Design for Manufacturability 17.3 Quantum computing
5. Power Analysis and Low-Power Design 17.4 Biologically based or biologically inspired systems
5.1 System level power design and thermal management 11.1 Design for yield, defect tolerance, cost issues, and impacts of DFM 17.5 New transistor structures and devices, new or radical process
5.2 Embedded low-power approaches: partitioning, scheduling, and resource 11.2 Process technology development, characterization, and modeling technologies
management 11.3 Deterministic static timing analysis and verification 18. Special Theme Topic: Automotive Electronics
5.3 High-level power estimation and optimization 11.4 Statistical performance analysis and optimization 18.1 Safety critical systems design: engine control, brake systems,
5.4 Gate-level power analysis and optimization 11.5 Design for resilience under manufacturing variations automated highways, security systems, low tire pressure monitors,
5.5 Device, circuit techniques for low-power design 12. Physical Design and Manufacturability traction control, and auto distance cruise control
6. Verification 12.1 Physical floorplanning, partitioning, placement 18.2 Bus selection and verification challenges for LIN, CAN and FlexRay
6.1 Functional, transaction-level, RTL, and gate-level modeling and 12.2 Buffer insertion, routing, interconnect planning 18.3 Automotive convenience factors: control systems, entertainment,
verification of hardware design 12.3 Physical verification and design rule checking communication, navigation, climate control, rain sensing, active
6.2 Dynamic simulation, equivalence checking, formal (and semi-formal) 12.4 Automated synthesis of clock networks noise cancellation, and vehicle stability
12.5 Reticle enhancement, lithography-related design optimizations 18.4 Analog mixed-signal design challenges
verification model and property checking 18.5 Automotive as an EDA driver: will automotive define ESL for EDA?
6.3 Emulation and hardware simulators or accelerator engines 13. Signal Integrity and Design Reliability
13.1 Signal integrity, capacitive and inductive crosstalk 18.6 Issues with FPGA, ASIC and ASSP based design
6.4 Modeling languages and related formalisms, verification plan 13.2 Reliability modeling and analysis
development and implementation 13.3 Novel clocking and power delivery schemes
6.5 Assertion-based verification, coverage-analysis, constrained-random 13.4 Power grid robustness analysis and optimization
testbench generation 13.5 Soft-errors and single-event upsets (SEUs)
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Technical Program Committee

Co-Chair, Design Methods Pai Chou Patrick Groeneveld James Hoe Koen Lampaert
Grant E. Martin Univ. of California Eindhoven Univ. of Tech. Carnegie Mellon Univ. Mindspeed Technologies, Inc.
Tensilica, Inc. Irvine, CA Eindhoven, Netherlands Pittsburgh, PA Newport Beach, CA
Santa Clara, CA
Vivek De Bill Halpin Jiang Hu Luciano Lavagno
Co-Chair, Design Tools Intel Corp. Synplicity, Inc. Texas A&M Univ. Politecnico di Torino
Sachin Sapatnekar Hillsboro, OR Sunnyvale, CA College Station, TX Torino, Italy
Univ. of Minnesota
Sujit Dey Kazumi Hatayama Alan Hu Rainer Leupers
Minneapolis, MN
Univ. of California at San Diego Renesas Technology Corp. Univ. of British Columbia RWTH Aachen
Brian Bailey La Jolla, CA Tokyo, Japan Vancouver, BC, Canada Aachen, Germany
Consultant
Adam Donlin Lei He Yehea Ismail Patrick Lysaght
Oregon City, OR
Xilinx, Inc. Univ. of California Northwestern Univ. Xilinx, Inc.
Reinaldo Bergamaschi San Jose, CA Los Angeles, CA Evanston, IL San Jose, CA
IBM Corp., TJ Watson Research Cntr.
Stephen Edwards Christoph Heer Vikram Jandhyala Jean Christophe Madre
Yorktown Heights, NY
Columbia Univ. Infineon Technologies AG Univ. of Washington Synopsys, Inc.
John Berrie New York, NY Munich, Germany Seattle, WA Montbonnot, France
Zuken
Shauki Elassaad Michael Heimlich Niraj Jha Rabi Mahapatra
Almondsbury, United Kingdom
Rio Design Automation, Inc. Applied Wave Research, Inc. Princeton Univ. Texas A&M Univ.
David Blaauw Santa Clara, CA Pelham, NH Princeton, NJ College Station, TX
Univ. of Michigan
Harry Foster Fook-Luen Heng Andrew B. Kahng Chris Malachowsky
Ann Arbor, MI
Mentor Graphics Corp. IBM Corp. Univ. of California at San Diego NVIDIA Corp.
Krishnendu Chakrabarty Addison, TX Yorktown Heights, NY La Jolla, CA Santa Clara, CA
Duke Univ.
Patrick Girard Joerg Henkel Mahmut Kandemir Diana Marculescu
Durham, NC
LIRMM Univ. Univ. of Karlsruhe Penn State Univ. Carnegie Mellon Univ.
Naehyuck Chang Montpellier, France Karlsruhe, Germany University Park, PA Pittsburgh, PA
Seoul National Univ.
Helmut Graeb Richard Ho Ryan Kastner Radu Marculescu
Seoul, Korea
Technical Univ. of Munich D.E. Shaw Research & Development Univ. of California Carnegie Mellon Univ.
Charlie Chung-Ping Chen Munich, Germany Cupertino, CA Santa Barbara, CA Pittsburgh, PA
Univ. of Wisconsin
66
Madison, Wisconsin
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Technical Program Committee

Malgorzata Marek-Sadowska Trevor Mudge Dusan Petranovic Tajana Simunic Chi-Ying Tsui Joe Gianelli
Univ. of California Univ. of Michigan Mentor Graphics Corp. Univ. of California at San Diego Hong Kong Univ. of Science & Tech. Synplicity, Inc.
Santa Barbara, CA Ann Arbor, MI San Jose, CA La Jolla, CA Clear Water Bay, Hong Kong Sunnyvale, CA
Erik Jan Marinissen Rajeev Murgai Joel Phillips Dirk Stroobandt Geert Van Der Plas Rich Goldman
Philips Research Labs Fujitsu Labs of America, Inc. Cadence Berkeley Labs Ghent Univ. IMEC vzw Synopsys, Inc.
Eindhoven, Netherlands Sunnyvale, CA Berkeley, CA Ghent, Belgium Leuven, Belgium Mountain View, CA
Igor L. Markov Farid Najm Victor Prasanna Haihua Su Christophe Wolinski Andrew B. Kahng
Univ. of Michigan Univ. of Toronto Univ. of Southern California IBM Corp. IFSIC / IRISA Univ. of California at San Diego
Ann Arbor, MI Toronto, ON, Canada Los Angeles, CA Austin, TX Rennes Cedex, France La Jolla, CA
Erich Marschner Sani Nassif Gordon Roberts Dennis Sylvester Avi Ziv Georgia Marszalek
Cadence Design Systems, Inc. IBM Research McGill Univ. Univ. of Michigan IBM Corp. ValleyPR
Ellicott City, MD Austin, TX Montreal, QC Ann Arbor, MI Haifa, Israel Foster City, CA
Peter Marwedel Rishiyur Nikhil Jaijeet Roychowdhury Andres Takach Hai Zhou Shishpal Rawat
Univ. of Dortmund Bluespec, Inc. Univ. of Minnesota Mentor Graphics Corp. Northwestern Univ. Intel Corp.
Dortmund, Germany Waltham, MA Minneapolis, MN Wilsonville, OR Evanston, IL Folsom, CA
Sanu Mathew Nagaraj NS Rob Rutenbar Steven Teig PANEL SUBCOMMITTEE Rob Rutenbar
Intel Corp. Texas Instruments, Inc. Carnegie Mellon Univ. Tabula, Inc. Dennis Brophy Carnegie Mellon Univ.
Hillsboro, OR Dallas, TX Pittsburgh, PA Santa Clara, CA Mentor Graphics Corp. Pittsburgh, PA
Wilsonville, OR
Anmol Mathur Michael Orshansky Louis Scheffer Michael Sanie
Lothar Thiele
Calypto Design Systems, Inc. Univ. of Texas Cadence Design Systems, Inc. Francine Bacchini Consultant
ETH Zuerich
Santa Clara, CA Austin, TX San Jose, CA Thinkbold Corporate Communications Menlo Park, CA
Zuerich, Switzerland
San Jose, CA
Cecilia Metra Jens Palsberg Eike Schmidt Lori Kate Smith
Steven Tjiang
Univ. of Bologna Univ. of California ChipVision Design Systems AG Jayaram Bhasker Cadence Design Systems, Inc.
Google, Inc.
Bologna, Italy Los Angeles, CA Oldenburg, Germany eSilicon Corp. San Jose, CA
Mountain View, CA
Allentown, PA
Vincent Mooney Phiroze Parakh Sandeep Shukla Richard Tobias
Richard Tobias
Georgia Institute of Tech. Sierra Design Automation, Inc. Virginia Tech. John Cohn Pixelworks
Pixelworks
Atlanta, GA Santa Clara, CA Blacksburg, VA IBM Corp. Campbell, CA
Campbell, CA
Essex Jct., VT
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The 43rd Design Automation Conference • July 24 - 28, 2006 • San Francisco, CA

Exhibitor Liaison Committee/SDC Judges

EXHIBITOR LIAISON COMMITTEE DAC/ISSCC STUDENT DESIGN CONTEST JUDGES
Jana Burke Gabe Moretti Alan Mantooth William J. Bowhill
Mentor Graphics Corp. Gabe on EDA DAC/ISSCC SDC Co-Chair DAC/ISSCC SDC Co-Chair
Tucson, AZ Venice, FL Univ. of Arkansas Intel Massachusetts Inc.
Fayetteville, AR Hudson, MA
Donna Castillo Steve Pollock
Cadence Design Systems, Inc. JEDA Technologies Bud Taddiken John Edmondson
San Jose, CA Los Altos, CA Microtune, Inc. NVIDIA Corp.
Plano, TX Bedford, MA
Anne Cirkel Mindy Palmer
Mentor Graphics Corp. CoWare, Inc. Chidamber Kulkarni John W. Lockwood
Wilsonville, OR San Jose, CA Xilinx Inc. Washington Univ.
Michelle Clancy Dave Reed San Jose, CA St. Louis, MO
Cayenne Communication Blaze DFM, Inc. Claude Gauthier Liam Madden
Washington, NC Sunnyvale, CA Univ. of Michigan Advanced Micro Devices, Inc.
Craig Cochran Ellen M. Sentovich Cupertino, CA Sunnyvale, CA
Jasper Design Automation, Inc. Cadence Berkeley Labs Daniel Leibholz Peter R. Wilson
Mountain View, CA Berkeley, CA Advanced Micro Devices, Inc. Univ. of Southampton
Nanette V. Collins Lee Wood Boxborough, MA Southampton, United Kingdom
Public Relations Consultant MP Associates, Inc. Francis Jeung Saraju P. Mohanty
Boston, MA Boulder, CO ASTRI-WMT University of North Texas
Limor Fix Shatin NT, Hong Kong Denton, TX
Intel Research Pittsburgh Hoi-Jun Yoo Werner Weber
Pittsburgh, PA KAIST Infineon Technologies AG
Daejeon, South Korea Munich, Germany
Tom Minot
Portland, OR James Goodman William B. Kuhn
ATI Technologies Inc. Kansas State Univ.
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Ottawa, Canada Manhattan, KS