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820-01598 Prometheus Power Sequence Diagram LO2

The document outlines the power up sequence for various components in a system. It begins with powering the main power rails from an external power source over 4V. It then details powering up the real time clock circuits, main processor power rails, storage device power rails like SSD in a specific order with timing delays between each step to ensure safe and stable power up of the entire system.

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Patricio Velez
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150 views1 page

820-01598 Prometheus Power Sequence Diagram LO2

The document outlines the power up sequence for various components in a system. It begins with powering the main power rails from an external power source over 4V. It then details powering up the real time clock circuits, main processor power rails, storage device power rails like SSD in a specific order with timing delays between each step to ensure safe and stable power up of the entire system.

Uploaded by

Patricio Velez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VALID EXTERNAL POWER SOURCE, BATTERY OR CHARGER >4.

0V

5.4V
PBUS
100ms

PP3V3_G3H_RTC
24ms

PP3V3_G3H

VIN_RTC>VIN_RTC_UPPER_TRESHOLD
1s

PP1V8_SLPS2R
1ms

PMU_CLK32K_SOC
0.5ms

PP1V8_AWAKE

PP1V8_SLPS2R_PMUGPIO

PP1V1_SLPS2R

PP0V8_SLPS2R
0.5ms

0.5ms
Vinafix.com
0.5ms

PP0V82_SLPDDR
0.5ms

PP3V3_AWAKE
0.5ms

PPVDDCPUSRAM_AWAKE
0.5ms

PP0V9_SLPDDR
0.5ms

P1V1_SLPDDR_SOCFET_EN

PP1V1_SLPDDR

H9M 24MHz CLK


2.5ms

PP1V2_AWAKE
1ms

PPVDDCPU_AWAKE
1ms

PMU_SYS_ALIVE

PMU_ACTIVE_READY

PMU_COLD_RESET_L

H9M LOAD SECURE ROM, SMC BATTERY TRAP

PMU_PVDDMAIN_EN
6-20ms

P3V3MAIN_PGOOD

PP3V_G3H_RTC

PMU_CLK32K_PCH
20ms

PCH_RTC_RESET_L
0.1ms

P5VG3S_EN

PP5V_G3S
0.1ms

P3V3G3S_EN

PP3V3_G3S
0.1ms

P1V8G3S_EN

PP1V8_G3S
0-20ms

P5VG3S_PGOOD
0ms

PMU_CLK32K_WLANBT

SSD 4LANDING: OCARINA I2C WRITE POWER_STATE_TARGET={ACTIVE} TO ENABLE SSD POWER

SSD_PMU_RESET_L

PPVCCQ_ANI_SSD0
SSD 4 LANDING (VR=OCARINA) *

1ms

PP0V9_SSD0
1ms

SSD0_VR_2V5_EN

PP2V5_NAND_SSD0
1.5ms

SSD0_OCARINA_WP_L
0ms

SSD0_OCARINA_PFN
ANS2 DRIVER WILL DETERMINE WHEN TO REQUEST SMC TO DE-ASSERT SSD_RESET_L

SSD0_OCARINA_RESET_L

SSD 2LANDING: CALPE, CONFIGURE RAILS AND GPIOS TO ENABLE SSD POWER:

PPVCCQ_ANI_SSD0
1ms
SSD 2 LANDING (VR=CALPE) *

PP0V9_SSD0
0.1ms

SSD0_PMIC_DISCHARGE_EN
1ms

SSD0_VR_2V5_EN

PP2V5_NAND_SSD0

SSD0_VR_P2V5_PGOOD

SSD0_PMIC_RESET_L

SMC BEGINS PWRBTN MONITORING

PMU_ONOFF_L

PP3V3_S5
2ms

PP1V8_S5
1ms

PPVPCORE_S5
1ms

PP1V_PRIM
10-20ms

[SMC/PM]_RSMRST_L

SMC WAITS FOR eSPI_RESET# PIN TO INITIATE eSPI LINK TRAINING. PCH DE-ASSERTS SLP_S5# AND SLP_S4# OVER eSPI
> 16ms

PCH_PWRBTN_L
0ms

PP1V8_S3
1ms

PVDDQ_EN

PP1V2_S3
< 20ms

PVDDQ_PGOOD
0ms

PP1V_S3

PCH DE-ASSERTS SLP_S3#, SLP_A#, SLP_LAN# AND SLP_WLAN# OVER eSPI

PVCCPLLOC_EN

PP1V2_S0SW
0.2ms

PP1V_S0SW
0.2ms

PVCCIO_EN

PPVCCIO
< 20ms

PVCCIO_PGOOD
1ms

ALL_SYS_PWRGD

IMVP, including: PPVCC_S0_CPU,


PPVCCSA_S0_CPU, PPVCCGT_S0_CPU
< 20ms

CPU_VR_READY
0ms

PM_SYSRST_L
2.5ms

PM_PCH_PWROK
100ms

PM_PCH_SYS_PWROK

* Power up sequence different between SSD 2 vs. 4 landing.


Power rails: BLACK
Signal outputs: BLUE
Signal inputs: ORANGE

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