Chapter 2: Op-Amp Basic Stages

2.1 Introduction

An integrated circuit IC is a circuit where an entire circuit is constructed on a single piece of

semiconductor material. One of the commonly used types of IC is the operational amplifier.
The schematic diagram of the 741-type OP-Amp and its symbol is shown below.

Vee

Inverting Input -
Output
Non Inverting +
Input

Vcc

Operational Amplifier is a high gain dc differential amplifier capable of performing a wide

range of functions by using external feedback. It is the most flexible linear device. By
controlling the feedback network properties, we can manipulate the overall forward transfer
function of the device and its application.

The majority of commercially available operational amplifiers employ the structure shown
below.
 V1
Buffer & Level
Diff-Amp Additional Gain Output Deriver VO
V2 Shifter

The differential amplifier is used as the input stage to provide the inverting and the non
inverting inputs and the high input resistance as well as voltage gain. The low output
resistance of the op-amp is achieved by the emitter follower output stage. The level shifter
adjusts the dc voltages so that the output voltage signal is referenced to ground. The
adjustment of dc level is required because the gain stages are direct coupled. The input and
output stages are required to match the op-amp with the external world.

2.2 Differential Amplifiers

Previously in Applied electronics I, we have discussed single stage amplifiers of one input
and one output terminal with limited gain, input resistance and output resistance. Here,
another basic transistor circuit configuration called differential amplifier is introduced,
which can give us high gain and specified input and output resistance values. It is the input
stage for most operational amplifiers and is widely used amplifier building block in analogue
integrated circuit. Unlike the other amplifiers we have discussed so far, it has two input
terminals and one output terminal, where the output signal is the difference of the two input
signals as shown in the difference amplifier block diagram below.

V2
Difference
Amplifier VO
V1

Figure 2.1: Difference amplifier block diagram

Where the output voltage V O is given by:

There are two different modes of operation of the differential pair:

1. The differential pair with a common-mode input signal CM:

2. The differential pair with a differential (mode) input signal:

Thus, the total output voltage is given by

Where and respectively are the differential gain and the common mode gain.
The above equations shows that if V 1 = V 2 , the differential mode input signal is zero and the
common mode input signal is V cm = V 1 = V 2 .

The differential amplifier can be implemented with BJTs and FETs. We focus on differential
amplifiers implemented using BJT transistors.

2.2.1. Response for differential inputs

Differential mode: This mode of operation exists when the differential amplifier has one
source connected to each input and the two sources are out of phase with each other and of
the same amplitude.

Common mode: This exists if the sources are equal in amplitude and in phase, the two
opposing forces will balance each other, so that they cancel.

Consider the following basic BJT differential pair configuration

VCC

RC1 RC2

VC1 - +
Vout VC2

iC1 iC2

Q1 Q2

VB1 iE1 VB2

iE2

VEE

Figure 2.2: Basic BJT differential pair configuration

Following the polarity shown in figure 2.2, the ac output voltage can be expressed as:

The output voltage V out is called a differential output since it combines the two ac collector
voltages into one voltage.

Common mode response

First let us consider a circuit in which the two base terminals are connected together and a
common mode voltage V cm is applied as shown in figure 2.3 below.

The voltage at the common emitters is given by KVL in one of the transistor input circuit:
If the transistors Q 1 and Q 2 are identical, the current I Q splits evenly between the two
transistors and is given by:

If base currents are negligible then, ,

Therefore, the collector voltages are given by:

VCC

IQ IQ
RC1 RC2 2
2
IQ IQ
VC1 VCC RC1 VC 2 VCC RC 2
2 2

Q1 Q2
+
Vcm
- IQ IQ
2 VE
2

IQ

VEE

Figure 2.3: Basic diff-amp with applied common mode voltage

From this we conclude that, for an applied common mode voltage, splits equally between
Q 1 and Q 2 and the difference between V C1 and V C2 is zero.

By varying V cm in figure 2.3 above by a small amount and determining the circuit response,
will not result any change in the above equations. Thus, suggesting that both the collector
current and voltages of the transistor will remain unchanged. Hence, we say the circuit does
not respond to changes in the input common mode level; or the circuit “rejects” input CM
variations.

Differential response

Let us now increase the base voltage V B1, in figure 2.2, by a small voltage V d /2 and decrease
V B2 by the same amount. I.e. let
This results to:

By symmetry of the two transistors the total gain of common mode pair is zero.

RC1

+
Ri1 V1 gm1V1
Vcm -

2RE

Figure 2.8: Small signal model for the common mode circuit when Re is added

But if an emitter resistor is connected to the emitter node E of the above figure 2.8, the one sided gain
A C is simply given by:

R i1

Because the same signal is applied for Q 1 and Q 2 both V o1 and V o2 are out of phase with V cm .

2.2.3. Common mode rejection ratio (CMRR)

It is defined as the ratio between the differential gain and the common mode gain, indicates
the ability of the amplifier to accurately cancel voltages that are common to both inputs.

For an ideal diff-amp A c is zero and CMRR goes to infinite.

For the differential amplifier shown in figure 2.2 the one sided differential and common
mode gains are given by:
And

Using these equations the CMRR can be expressed as:

The common mode gain decreases as increases. Therefore, as equation 2.20 shows CMRR
increases as increases.

Hence, the higher the differential gain with respect to the common mode gain, the better the
performance of the diff-amp in terms of the rejection of the common mode signals.

Example 1:

Determine the differential and common mode gains of the diff-amp for the figure 2.2, with
parameters . The transistor
parameters are: . Assume the output resistance looking into the constant current
source is , and again take the assumption that the source resistance of each
transistor is zero.

Solution:

From equation 2.15, the differential mode gain for the one sided output is

Therefore,

Substituting the values of and and taking , we get

From equation 2.18, the common mode gain is

Rewriting the above equation and using

As it is seen in the above result, the common mode gain is significantly less than the
differential-mode gain, but it is not zero because our current source is not ideal.

And the CMRR is given by

Expressing this in decibel,

The CMRR of diff-amp can be improved by increasing the current source output resistance.

Input and output impedances

For the differential pair configuration and its equivalent model shown in figure 2.9 below, we
can write the input impedance as follows:

And also we have from KVL loop between V 1 , node E and V 2 :

From this it follows that

This implies that as if the two base emitter junctions appear in series. And hence, the result is
called the differential input impedance of the circuit.