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Fall 2023 - CS302P - 2

This document provides instructions for Assignment #02 for the course Digital Logic Design Practicals (CS302P). It outlines the rules for marking, topics covered in the assignment, file submission requirements, and a sample question requiring students to design a combinational circuit using two 8-1 multiplexers to implement a given 4-input boolean function. Students must submit a labeled screenshot of their circuit diagram using only 8-1 multiplexers by the deadline of January 16, 2024 to receive marks. No late submissions or alternate file formats will be accepted.

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SHFAIQ BAIG
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50 views2 pages

Fall 2023 - CS302P - 2

This document provides instructions for Assignment #02 for the course Digital Logic Design Practicals (CS302P). It outlines the rules for marking, topics covered in the assignment, file submission requirements, and a sample question requiring students to design a combinational circuit using two 8-1 multiplexers to implement a given 4-input boolean function. Students must submit a labeled screenshot of their circuit diagram using only 8-1 multiplexers by the deadline of January 16, 2024 to receive marks. No late submissions or alternate file formats will be accepted.

Uploaded by

SHFAIQ BAIG
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Digital Logic Design Practicals (CS302P) Total marks = 20

Assignment # 02 Deadline
th
16 of January
Fall 2023 2024

Please carefully read the following instructions before attempting the assignment.

RULES FOR MARKING


It should be clear that your assignment would not get any credit if:
 The assignment is submitted after the due date.
 The submitted assignment does not open or the file is corrupt.
 Strict action will be taken if the submitted solution is copied from any other student or the
internet.

You should consult the recommended books to clarify your concepts as handouts are not
sufficient.

You are supposed to submit your assignment in Doc or Docx format & EWB File (If required).

Any other formats like scanned images, PDF, ZIP, RAR, PPT, BMP, etc. will not be accepted.

Topic Covered:
 Lab Work - Week # 05 - DeMorgan’s Theory and the Universal Gates
 Lab Work - Week # 06 - Simplification of Boolean Expressions
 Lab Work - Week # 07 - The Story of Minterms and Maxterms
 Lab Work - Week # 08 - XOR and XNOR gates: Basics and Applications
 Lab Work - Week # 09 - Building Logic Circuits using Multiplexers
 Lab Work - Week # 10 - Building Digital Logic Circuits using Decoders
 Lab Work - Week # 11 - Sequential Circuits

Lab Work # 05 - 11
NOTE

No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding
or internet malfunctioning etc.). Hence refrain from uploading assignments in the last hour of the deadline. It is
recommended to upload the solution at least two days before its closing date.

If you people find any mistake or confusion in the assignment (Question statement), please consult with your
instructor before the deadline. After the deadline, no queries will be entertained in this regard.

For any query, feel free to email me at:


[email protected]
Question No 01 Marks (20)
Design a combinational circuit using two 8-1 MUX to implement a 4-input boolean function having the
below given function table.

Inputs Output
ID
D C B A F
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 1

You have to submit a clear screenshot of your circuit diagram with your VU Student ID mentioned or
labeled with the output node of the circuit diagram. You must only use 8-1 MUX otherwise you will get 0
marks.

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