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Lab 04

This document describes an experiment on designing encoders and decoders using Verilog. It discusses encoders, decoders, and their operations. It then lists the goals of implementing a 3x8 encoder in Verilog, verifying the design, modifying it to include a master enable, and using decoders to realize logic functions. The document provides code for a 2x4 decoder and describes tasks of completing the code, testing it, using two decoders in a cascaded 3x8 decoder, testing that, and post-lab tasks of drawing a 4x16 decoder diagram and implementing it in Verilog.

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ALISHBA AZAM
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23 views5 pages

Lab 04

This document describes an experiment on designing encoders and decoders using Verilog. It discusses encoders, decoders, and their operations. It then lists the goals of implementing a 3x8 encoder in Verilog, verifying the design, modifying it to include a master enable, and using decoders to realize logic functions. The document provides code for a 2x4 decoder and describes tasks of completing the code, testing it, using two decoders in a cascaded 3x8 decoder, testing that, and post-lab tasks of drawing a 4x16 decoder diagram and implementing it in Verilog.

Uploaded by

ALISHBA AZAM
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Engr Muhammad Hammad

EXPERIMENT # 04
Design of Encoder and Decoder

Goals: The goal of this experiment is to introduce combinational circuits i.e., decoders and encoders
and study its Verilog Programming.

Pre LAB
Discussion
ENCODER:

An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2 n input
lines and n output lines. In encoder the output lines generate the binary code corresponding to the input
value. In octal to binary encoder, it has eight inputs, one for each octal digit and three output that
generate the corresponding binary code. In encoder it is assumed that only one input has a value of one
at any given time otherwise the circuit is meaningless.
DECODER:

A decoder is a multiple input multiple output logic circuits which converts coded input into coded output
where input and output codes are different. The input code generally has fewer bits than the output code.
Each input code word produces a different output code word i.e., there is one to one mapping can be
expressed in truth table. In the block diagram of decoder circuit, the encoded information is present as
n input producing 2n possible outputs. 2n output values are from 0 through out 2n – 1.

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Engr Muhammad Hammad

In LAB

1. Implement the Verilog model of 3x8 encoder using above code.


2. Verify the design using its tester code.
3. What will be the impact of removing default case?
4. Modify the above code with the introduction of master enable. Encoder should be in high
impedance state while disabled.
Function:

• f(a, b, c)
= SPECIFIED BY THE LAB INSTRUCTOR
• g(w, x, y, z) = SPECIFIED BY THE LAB INSTRUCTOR
(You may have to expand the equation to obtain minterms containing all the input variables.)

5. Represent the two functions in truth table and minterms list form. For the three-input
function , obtain a schematic diagram using one 3x8 decoder while two 3x8 decoders will
be needed for the four-input function.

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Engr Muhammad Hammad

3x8 Decoder Component

A 3x8 decoder (Cascaded) made with two 2x4 decoders.

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Engr Muhammad Hammad

module 2x8_dec (en, in, out);


input en; // Enable signal
input [1:0] in;
output [3:0] out;
???? // Declare ‘out’ as a register
always@(????) // Fill the sensitivity list
begin
if(en==1)
case(in)
2'b00: out = 4'b0001;
2'b01: ??? // Fill this line
??? // Fill this line
??? // Fill this line
Endcase
else if(en==0)
begin
out = ??? // What should ‘out’ be?
end
end
endmodule
6. Complete the above code which is implementation of 2x4 decoder using procedural programming.
7. Test the behavior of above code.

module toplevl_3x8_dec (in, out);


input [2:0] in; // 3-bit input
output [7:0] out; // 8-bit output
wire wire1; // Declaring a wire
//module mydecoder24vlog (en, in, out);
mydecoder24vlog decoder1 (in[2], in[1:0], out[7:4]);
mydecoder24blog decoder0 (???, ???, ???);
not inverter0 (wire1, in[2]);
endmodule

8. Complete the Top-level module and implement cascaded 3x8 decoder using 2 2x4 decoders as
shown in the above figure.
9. Test the behavior of the designed Verilog model.

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Engr Muhammad Hammad

Post LAB Tasks


1. Draw Logic diagram of 4x16 decoder using 2x4 decoders only.
2. Using Top level module as in In Lab , write Verilog code for the
above 4x16 decoder and its test bench.
3. Implement a 2-bit magnitude comparator. Verify its functionality.
Show its schematic.
4. What are the advantages of using FPGA over MSI devices and SSI
devices.

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