MEMORY MANAGEMENT

(UNIT IV)

Dr. Indrajeet Kumar

Department of CSE
Graphic Era Hill University
Dehradun
 Memory management
• Memory management is the functionality
of an operating system which handles or
manages primary memory and moves
processes back and forth between
main memory and disk during execution.
• Memory management keeps track of
each and every memory location,
regardless of either it is allocated to some
process or it is free.
 Base and Limit Register
 If the base register holds 300040 and limit register
is 120900, then the program can legally access all
addresses from 300040 through 420940
 Address Binding
• Address binding of instructions and data to memory
addresses can happen at three different stages
– Compile time: at compile time where the process
will reside in memory , then absolute code can be
generated.
– Load time: Must generate relocatable code if
memory location is not known at compile time
– Execution time: Binding delayed until run time if the
process can be moved during its execution from one
memory segment to another. Need hardware support
for address maps (e.g., base and limit registers)
Multistep Processing of a User Program
 Address Space
• Logical Address Space: generated by the CPU;
also referred to as virtual address.

• Physical address Space: address seen by the

memory unit.

• The concept of a logical address space that is

bound to a separate physical address space is
central to proper memory management.
 Address Space

• Logical and physical addresses are the same in

compile-time and load-time address-binding
schemes.

• Logical (virtual) and physical addresses differ in

execution-time address-binding scheme.
 Memory-Management Unit (MMU)

• Hardware device that maps virtual to

physical address.
• In MMU scheme, the value in the
relocation register is added to every
address generated by a user process at
the time it is sent to memory.
• The user program deals with logical
addresses; it never sees the real physical
addresses.
Dynamic relocation using a relocation register
 Dynamic Loading
• The size of a process is limited to the size of physical
memory.
• To obtain better memory-space utilization, we can use
dynamic loading.
• In dynamic loading, routine is not loaded until it is called.
• Advantage of dynamic loading, better memory-space
utilization; unused routine is never loaded.
• Useful when large amounts of code are needed to handle
infrequently occurring cases
• No special support from the operating system is required
implemented through program design
 Dynamic Linking
• Linking postponed until execution time
• Small piece of code, stub, used to locate the
appropriate memory-resident library routine
• Stub replaces itself with the address of the
routine, and executes the routine
• Operating system needed to check if routine is in
processes memory address
• Dynamic linking is particularly useful for libraries
• System also known as shared libraries
 Swapping
• A process can be swapped temporarily out of memory to a
backing store, and then brought back into memory for
continued execution.
• Backing store – fast disk large enough to accommodate copies
of all memory images for all users; must provide direct access
to these memory images.
• Roll out, roll in – swapping variant used for priority-based
scheduling algorithms; lower-priority process is swapped out
so higher-priority process can be loaded and executed.
• Major part of swap time is transfer time; total transfer time is
directly proportional to the amount of memory swapped.
• Modified versions of swapping are found on many systems,
i.e., UNIX and Microsoft Windows.
Schematic View of Swapping
 Contiguous Memory Allocation
Single Partition
• Main memory usually into two partitions:
– Resident operating system, usually held in low memory with
interrupt vector
– User processes then held in high memory

• Relocation registers used to protect user processes from each other,

and from changing operating-system code and data
– Base register contains value of smallest physical address
– Limit register contains range of logical addresses – each logical
address must be less than the limit register
– MMU maps logical address dynamically
 Base and Limit Register
 If the base register holds 300040 and limit register
is 120900, then the program can legally access all
addresses from 300040 through 420940
Hardware Support for Relocation and Limit Registers
Contiguous Allocation (Cont)
Multiple-partition allocation
– Hole – block of available memory; holes of various size are scattered
throughout memory
– When a process arrives, it is allocated memory from a hole large enough
to accommodate it
– Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

OS OS OS OS

process 5 process 5 process 5 process 5

process 9 process 9

process 8 process 10

process 2 process 2 process 2 process 2

 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes
• First-fit: Allocate the first hole that is big enough
• Best-fit: Allocate the smallest hole that is big
enough; must search entire list, unless ordered by
size
– Produces the smallest leftover hole
• Worst-fit: Allocate the largest hole; must also
search entire list
– Produces the largest leftover hole

Note: First-fit and best-fit better than worst-fit in

terms of speed and storage utilization
 Fragmentation
• External Fragmentation – Total memory space
exists to satisfy a request, but it is not contiguous
• Internal Fragmentation – Allocated memory may
be slightly larger than requested memory; this size
difference is memory internal to a partition, but not
being used
• Reduce external fragmentation by compaction
– Shuffle memory contents to place all free
memory together in one large block
– Compaction is possible only if relocation is
dynamic, and is done at execution time
 Page Replacement
• Page replacement is a process of swapping out an existing page from the
frame of a main memory and replacing it with the required page.
• Page replacement is required when-

 All the frames of main memory are already occupied.

 Thus, a page has to be replaced to create a room for the required page.

Page Replacement Algorithms

• Page replacement algorithms help to decide which page must be swapped

out from the main memory to create a room for the incoming page.
A good page replacement algorithm is one that minimizes the number of page
faults.
FIFO Page Replacement Algorithm-

As the name suggests, this algorithm works on the principle of “First in First


out“.

It replaces the oldest page that has been present in the main memory for the


longest time.

It is implemented by keeping track of all the pages in a queue



LIFO Page Replacement Algorithm-

 As the name suggests, this algorithm works on the principle of “Last in

First out“.

 It replaces the newest page that arrived at last in the main memory.

 It is implemented by keeping track of all the pages in a stack.

NOTE

•Only frame is used for page replacement during entire procedure after all the
frames get occupied.
LRU Page Replacement Algorithm-

 As the name suggests, this algorithm works on the principle of “Least

Recently Used“.

 It replaces the page that has not been referred by the CPU for the longest
time.
Random Page Replacement Algorithm-

As the name suggests, this algorithm randomly replaces any page. So, this


algorithm may behave like any other algorithm like FIFO, LIFO, LRU,
Optimal etc.
Optimal Page Replacement Algorithm-
•This algorithm replaces the page that will not be referred by the CPU in
future for the longest time.
•It is practically impossible to implement this algorithm.
•This is because the pages that will not be used in future for the longest
time can not be predicted.
•However, it is the best known algorithm and gives the least number of
page faults.
•Hence, it is used as a performance measure criterion for other algorithms.
A system uses 3-page frames for storing process pages in main memory. It uses
the First in First out (FIFO) page replacement policy. Assume that all the page
frames are initially empty. What is the total number of page faults that will occur
while processing the page reference string given below-

4, 7, 6, 1, 7, 6, 1, 2, 7, 2

Also calculate the hit ratio and miss ratio.

 Paging
• Logical address space of a process can be
noncontiguous; process is allocated physical memory
whenever the latter is available.
• Divide physical memory into fixed-sized blocks called
frames.
• Divide logical memory into blocks of same size called
pages.
• Keep track of all free frames.
• To run a program of size n pages, need to find n free
frames and load program.
• Set up a page table to translate logical to physical
addresses.
 Address Translation Scheme
• Address generated by CPU is divided into:

– Page number (p) – used as an index into a page table which

contains base address of each page in physical memory

– Page offset (d) – combined with base address to define the

physical memory address that is sent to the memory unit
page number page offset
p d
m-n n

– High order = m-n, ((bits of a logical address)

– Lower order = n,
– For given logical address space 2m and page size 2n
Paging Hardware
 Key Formulas-
• For Main Memory-
• Physical Address Space = Size of main memory
• Size of main memory = Total number of frames x
Page size
• Frame size = Page size
• If number of frames in main memory = 2X, then
number of bits in frame number = X bits
• If Page size = 2X Bytes, then number of bits in page
offset = X bits
• If size of main memory = 2X Bytes, then number of
bits in physical address = X bits
• For Process-
• Virtual Address Space = Size of process
• Number of pages the process is divided =
Process size / Page size
• If process size = 2X bytes, then number of
bits in virtual address space = X bits
• For Page Table-
• Size of page table = Number of entries in
page table x Page table entry size
• Number of entries in pages table =
Number of pages the process is divided
• Page table entry size = Number of bits in
frame number + Number of bits used for
optional fields if any
• NOTE-
• In general, if the given address consists of ‘n’ bits,
then using ‘n’ bits, 2n locations are possible.
• Then, size of memory = 2n x Size of one location.
• If the memory is byte-addressable, then size of
one location = 1 byte.
• Thus, size of memory = 2n bytes.
• If the memory is word-addressable where 1 word
= m bytes, then size of one location = m bytes.
• Thus, size of memory = 2n x m bytes.
 Implementation of Page Table
• Page table is kept in main memory
• Page-table base register (PTBR) points to the page table
• Page-table length register (PRLR) indicates size of the page table
• In this scheme every data/instruction access requires two memory
accesses. One for the page table and one for the data/instruction.
• The two memory access problem can be solved by the use of a
special fast-lookup hardware cache called associative memory or
translation look-aside buffers (TLBs)
• Some TLBs store address-space identifiers (ASIDs) in each TLB
entry – uniquely identifies each process to provide address-space
protection for that process
• The percentage of times that a particular page number found in the
TLB is called the hit ratio.
Paging Hardware With TLB
 Memory Protection
• Memory protection implemented by associating
protection bit with each frame

• Valid-invalid bit attached to each entry in the

page table:
– “valid” indicates that the associated page is in
the process’ logical address space, and is thus
a legal page
– “invalid” indicates that the page is not in the
process’ logical address space
Valid (v) or Invalid (i) Bit In A Page Table
 Structure of the Page Table
• Hierarchical Paging

• Hashed Page Tables

• Inverted Page Tables

 Hierarchical Page Tables

• Break up the logical address

space into multiple page
tables

• A simple technique is a two-

level page table
Two-Level Page-Table Scheme
 Two-Level Paging Example
• A logical address is divided into:
– a page number consisting of 22 bits
– a page offset consisting of 10 bits
• Since the page table is paged, the page number is further divided into:
– a 12-bit page number
– a 10-bit page offset
• Thus, a logical address is as follows:

page number page offset

pi p2 d

12 10 10

where pi is an index into the outer page table, and p2 is the

displacement within the page of the outer page table
Address-Translation Scheme
Three-level Paging Scheme
 Hashed Page Tables
• Common in address spaces > 32 bits

• The virtual page number is hashed into a page

table
– This page table contains a chain of elements
hashing to the same location.

• Virtual page numbers are compared in this chain

searching for a match
– If a match is found, the corresponding physical
frame is extracted
Hashed Page Table
 Inverted Page Table
• One entry for each real page of memory
• Entry consists of the virtual address of the page
stored in that real memory location, with
information about the process that owns that
page.
• Decreases memory needed to store each page
table, but increases time needed to search the
table when a page reference occurs
• Use hash table to limit the search to one — or at
most a few — page-table entries
Inverted Page Table Architecture
 Segmentation
• Memory-management scheme that supports user view of memory
• A program is a collection of segments
– A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
User’s View of a Program
Logical View of Segmentation
1

4
1

3 2
4

user space physical memory space

 Segmentation Architecture
• Logical address consists of a two tuple:
<segment-number, offset>,
• Segment table – maps two-dimensional physical
addresses; each table entry has:
– base – contains the starting physical address where
the segments reside in memory
– limit – specifies the length of the segment
• Segment-table base register (STBR) points to the
segment table’s location in memory
• Segment-table length register (STLR) indicates
number of segments used by a program;
segment number s is legal if s < STLR
 Segmentation Architecture (Cont.)
• Protection
– With each entry in segment table associate:
• validation bit = 0  illegal segment
• read/write/execute privileges
• Protection bits associated with segments; code
sharing occurs at segment level
• Since segments vary in length, memory allocation
is a dynamic storage-allocation problem
• A segmentation example is shown in the following
diagram
Segmentation Hardware
Example of Segmentation
 Background
• Virtual memory – separation of user logical memory from
physical memory.
– Only part of the program needs to be in memory for
execution.
– Logical address space can therefore be much larger
than physical address space.
– Need to allow pages to be swapped in and out.
• Virtual memory can be implemented via:
– Demand paging
– Demand segmentation
 Demand Paging
• Bring a page into memory only when it is needed.
– Less I/O needed
– Less memory needed
– Faster response
– More users
• Page is needed  reference to it
– invalid reference  abort
– not-in-memory  bring to memory
 Valid-Invalid Bit
• With each page table entry a valid–invalid bit is associated
(1  in-memory, 0  not-in-memory)
• Initially valid–invalid but is set to 0 on all entries.
• Example of a page table snapshot.
Frame # valid-invalid bit
1
1
1
1
0


0
0
page table
• During address translation, if valid–invalid bit in page table entry
is 0  page fault.
 Page Fault
• If there is ever a reference to a page, first reference will trap to
OS  page fault
• OS looks at another table to decide:
– Invalid reference  abort.
– Just not in memory.
• Get empty frame.
• Swap page into frame.
• Reset tables, validation bit = 1.
• Restart instruction: Least Recently Used
– block move

– auto increment/decrement location

What happens if there is no free
frame?
• Page replacement – find some page in memory, but not
really in use, swap it out.
– algorithm
– performance – want an algorithm which will result in
minimum number of page faults.
• Same page may be brought into memory several times.
Performance of Demand Paging
• Page Fault Rate 0  p  1.0
– if p = 0 no page faults
– if p = 1, every reference is a fault
• Effective Access Time (EAT)
EAT = (1 – p) x memory access
+ p (page fault overhead
+ [swap page out ]
+ swap page in
+ restart overhead)
 Demand Paging Example
• Memory access time = 1 microsecond
• 50% of the time the page that is being replaced has been
modified and therefore needs to be swapped out.
• Swap Page Time = 10 msec = 10,000 msec
EAT = (1 – p) x 1 + p (15000)
1 + 15000P (in msec)
 Page Replacement
• Prevent over-allocation of memory by modifying page-
fault service routine to include page replacement.
• Use modify (dirty) bit to reduce overhead of page
transfers – only modified pages are written to disk.
• Page replacement completes separation between logical
memory and physical memory – large virtual memory
can be provided on a smaller physical memory.
 Page-Replacement Algorithms
• Want lowest page-fault rate.
• Evaluate algorithm by running it on a particular string of
memory references (reference string) and computing the
number of page faults on that string.
• In all our examples, the reference string is
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5.
First-In-First-Out (FIFO) Algorithm
• Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
• 3 frames (3 pages can be in memory at a time per process)

1 1 4 5
2 2 1 3 9 page faults

• 4 frames 3 3 2 4

1 1 5 4
2 2 1 5 10 page faults
3 3 2

4 4 3

• FIFO Replacement – Belady’s Anomaly

– more frames  less page faults
 Optimal Algorithm
• Replace page that will not be used for longest period of time.
• 4 frames example
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5

1 4
2 6 page faults
3

4 5
• How do you know this?
• Used for measuring how well your algorithm performs.
 Least Recently Used (LRU)
Algorithm
• Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5

1 5
2

3 5 4
4 3
• Counter implementation
– Every page entry has a counter; every time page is referenced through
this entry, copy the clock into the counter.
– When a page needs to be changed, look at the counters to determine
which are to change.
 LRU Algorithm (Cont.)
• Stack implementation – keep a stack of page numbers in
a double link form:
– Page referenced:
• move it to the top
• requires 6 pointers to be changed
– No search for replacement
LRU Approximation Algorithms
• Reference bit
– With each page associate a bit, initially -= 0
– When page is referenced bit set to 1.
– Replace the one which is 0 (if one exists). We do
not know the order, however.
• Second chance
– Need reference bit.
– Clock replacement.
– If page to be replaced (in clock order) has
reference bit = 1. then:
• set reference bit 0.
• leave page in memory.
• replace next page (in clock order), subject to
same rules.
 Counting Algorithms
• Keep a counter of the number of references that have been
made to each page.
• LFU Algorithm: replaces page with smallest count.
• MFU Algorithm: based on the argument that the page with the
smallest count was probably just brought in and has yet to be
used.
 Thrashing
• If a process does not have “enough” pages, the page-
fault rate is very high. This leads to:
– low CPU utilization.
– operating system thinks that it needs to increase the
degree of multiprogramming.
– another process added to the system.
• Thrashing  a process is busy swapping pages in and
out.
 Thrashing Diagram

• Why does paging work?

Locality model
– Process migrates from one locality to another.
– Localities may overlap.
• Why does thrashing occur?
 size of locality > total memory size
 Working-Set Model
•   working-set window  a fixed number of page references
Example: 10,000 instruction
• WSSi (working set of Process Pi) =
total number of pages referenced in the most recent  (varies in
time)
– if  too small will not encompass entire locality.
– if  too large will encompass several localities.
– if  =   will encompass entire program.
• D =  WSSi  total demand frames
• if D > m  Thrashing
• Policy if D > m, then suspend one of the processes.
 Keeping Track of the Working Set
• Approximate with interval timer + a reference bit
• Example:  = 10,000
– Timer interrupts after every 5000 time units.
– Keep in memory 2 bits for each page.
– Whenever a timer interrupts copy and sets the values of all
reference bits to 0.
– If one of the bits in memory = 1  page in working set.
• Why is this not completely accurate?
• Improvement = 10 bits and interrupt every 1000 time units.
Page-Fault Frequency Scheme

• Establish “acceptable” page-fault rate.

– If actual rate too low, process loses frame.
– If actual rate too high, process gains frame.
 Other Considerations
• Preparing
• Page size selection
– fragmentation
– table size
– I/O overhead
– locality
 Other Consideration (Cont.)
• Program structure
– Array A[1024, 1024] of integer
– Each row is stored in one page
– One frame
– Program 1 for j := 1 to 1024 do
for i := 1 to 1024 do
A[i,j] := 0;
1024 x 1024 page faults
– Program 2 for i := 1 to 1024 do
for j := 1 to 1024 do
A[i,j] := 0;
1024 page faults
• I/O interlock and addressing
 Demand Segmentation
• Used when insufficient hardware to implement demand paging.
• OS/2 allocates memory in segments, which it keeps track of through
segment descriptors
• Segment descriptor contains a valid bit to indicate whether the segment is
currently in memory.
– If segment is in main memory, access continues,
– If not in memory, segment fault.
Thank you