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DSD Lab13

This Verilog code implements a temperature sensor module using an I2C interface. It contains the following key details: 1. It defines registers and logic to read temperature values from a sensor over I2C and display the reading on 7-segment displays. 2. An I2C state machine reads the temperature register value from the sensor and stores it in a 16-bit register. 3. Seven-segment display logic decodes the temperature reading and sequentially activates the displays using common anode signals.

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20 views9 pages

DSD Lab13

This Verilog code implements a temperature sensor module using an I2C interface. It contains the following key details: 1. It defines registers and logic to read temperature values from a sensor over I2C and display the reading on 7-segment displays. 2. An I2C state machine reads the temperature register value from the sensor and stores it in a 16-bit register. 3. Seven-segment display logic decodes the temperature reading and sequentially activates the displays using common anode signals.

Uploaded by

abid4209995
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Task # 1

Verilog Code

module Temp_sensor(input clk, //clock input to the module 100 MHz


inout SDA, //SDA of I2C BUS
output SCL, //SCL of I2C Bus
output [15:0] led, // Temperature sensor reading 16-bit
output reg [6:0] sseg_temp, // Reading displayed on seven segments
output reg [7:0] an, // common anodes of seven segment displays
output reg dp // decimal point of seven segment displays
);
reg [5:0] SD_COUNTER = 6'd0;
reg [31:0] count= 32'h00000000;
reg SDI; // reg variable to read and write data to/from SDA
reg SCLK; // reg variable to handle SCL of temperature sensor
reg [18:0] Counter; // Counter to handle which seven segment display to be selected
reg [3:0] first; // first seven segment
reg [3:0] second; //second seven segment
reg [3:0] third; //third seven segment
reg [3:0] fourth; // fourth seven segment
reg [3:0] fifth; //fifth seven segment
reg [3:0] sixth; //sixth seven segment
//reg [3:0] seventh;
//reg [3:0] eighth;
reg [3:0] seg; //reg to store active seven segment at a time
reg [15:0] led_temp = 16'b0000000000000000; //reg to hold temperature sensor register
reading displayed on 16 LED's
reg CLK = 0; // CLK generated to handle Serial Data Counter SD_Counter
always @ (posedge clk)
begin
count <= count + 1;
Counter <= Counter + 1;
if (count == 32'h00030D40) //200Khz
begin
count <= 0;
CLK <= ~CLK;
end
end
always @ (posedge CLK)
begin
if (SD_COUNTER == 53)
SD_COUNTER <= 0;
else
SD_COUNTER <= SD_COUNTER + 1;
end
always @ (posedge CLK)
begin
case (SD_COUNTER)
6'd0 : begin SDI <= 1; SCLK <= 1; end
//START
6'd1 : SDI <= 0;
6'd2 : SCLK <= 1;
// SLAVE ADDRESS 4B
6'd3 : SDI <= 1;
6'd4 : SDI <= 0;
6'd5 : SDI <= 0;
6'd6 : SDI <= 1;
6'd7 : SDI <= 0;
6'd8 : SDI <= 1;
6'd9 : SDI <= 1;
6'd10 : SDI <= 0; //write
6'd11 : SDI <= 1'bz; //ACK
// Temp Sens Register
6'd12 : SDI <= 0;
6'd13 : SDI <= 0;
6'd14 : SDI <= 0;
6'd15 : SDI <= 0;
6'd16 : SDI <= 0;
6'd17 : SDI <= 0;
6'd18 : SDI <= 0;
6'd19 : SDI <= 0;
6'd20 : SDI <= 1'bz;
//Start
6'd21 : begin SDI <= 1; SCLK <= 1;end
6'd22 : SDI <= 0;
6'd23 : SCLK <= 1;
//Slave Address
6'd24 : SDI <= 1;
6'd25 : SDI <= 0;
6'd26 : SDI <= 0;
6'd27 : SDI <= 1;
6'd28 : SDI <= 0;
6'd29 : SDI <= 1;
6'd30 : SDI <= 1;
6'd31 : SDI <= 1;//read
6'd32 : SDI <= 1'bz;
//Data Read MSB
6'd33 : led_temp[15] <= SDA;
6'd34 : led_temp[14] <= SDA;
6'd35 : led_temp[13] <= SDA;
6'd36 : led_temp[12] <= SDA;
6'd37 : led_temp[11] <= SDA;
6'd38 : led_temp[10] <= SDA;
6'd39 : led_temp[9] <= SDA;
6'd40 : begin led_temp[8] <= SDA; SDI<=0;end
6'd41 : begin SDI <= 1'b0;SCLK<=0;end
6'd42 : SCLK<=1;
//Data Read LSB
6'd43 : led_temp[7] <= SDA;
6'd44 : led_temp[6] <= SDA;
6'd45 : led_temp[5] <= SDA;
6'd46 : led_temp[4] <= SDA;
6'd47 : led_temp[3] <= SDA;
6'd48 : led_temp[2] <= SDA;
6'd49 : led_temp[1] <= SDA;
6'd50 : led_temp[0] <= 0;
6'd51 : SDI <= 1'b1;
// //STOP
6'd52 : begin SDI <= 1'b0; SCLK <= 1'b1; end
6'd53 : SDI <= 1'b1;
endcase
end
assign led = led_temp;
assign SCL = ((SD_COUNTER >2) && (SD_COUNTER <= 20) || (SD_COUNTER >= 24) &&
(SD_COUNTER <= 40))||((SD_COUNTER>=43) && (SD_COUNTER<=51)) ? CLK : SCLK;
assign SDA = (SD_COUNTER>=0 && SD_COUNTER<=32)|| ((SD_COUNTER>=41) &&
(SD_COUNTER<43))||(SD_COUNTER>50)?SDI:1'bz;
always @ (*)
begin
case (Counter[17:15])
3'b000: begin
seg <= first;
an <= 8'b11111110;
dp <= 1'b1;
end
3'b001: begin
seg <= second;
an <= 8'b11111101;
dp <= 1'b1;
end
3'b010: begin
seg <= third;
an <= 8'b11111011;
dp <= 1'b1;
end
3'b011: begin
seg <= fourth;
an <= 8'b11110111;
dp <= 1'b1;
end
3'b100: begin
seg <= fifth;
an <= 8'b11101111;
dp <= 1'b0;
end
3'b101: begin
seg <= sixth;
an <= 8'b11011111;
dp <= 1'b1;
end
default: begin an <=8'b11111111; dp <= 1'b1;end
endcase
end
always @ (*)
begin
case(seg)
0 : sseg_temp = 7'b1000000; //0
1 : sseg_temp = 7'b1111001; //1
2 : sseg_temp = 7'b0100100; //2
3 : sseg_temp = 7'b0110000; //3
4 : sseg_temp = 7'b0011001; //4
5 : sseg_temp = 7'b0010010; //5
6 : sseg_temp = 7'b0000010; //6
7 : sseg_temp = 7'b1111000; //7
8 : sseg_temp = 7'b0000000; //8
9 : sseg_temp = 7'b0011000; //9
10: sseg_temp = 7'b0001000; //A
11: sseg_temp = 7'b0000011; //B
12: sseg_temp = 7'b1000110; //C
13: sseg_temp = 7'b0100001; //D
14: sseg_temp = 7'b0000110; //E
15: sseg_temp = 7'b0001110; //F
endcase
//converting from 9 digit binary to decimal value
// Starting at 8 degrees.
case (led[15:7])
9'b000000000 : begin fifth <= 4'b0000; sixth <= 4'b0000; end
9'b000000001 : begin fifth <= 4'b0001; sixth <= 4'b0000; end
9'b000000010 : begin fifth <= 4'b0010; sixth <= 4'b0000; end
9'b000000011 : begin fifth <= 4'b0011; sixth <= 4'b0000; end
9'b000000100 : begin fifth <= 4'b0100; sixth <= 4'b0000; end
9'b000000101 : begin fifth <= 4'b0101; sixth <= 4'b0000; end
9'b000000110 : begin fifth <= 4'b0110; sixth <= 4'b0000; end
9'b000000111 : begin fifth <= 4'b0111; sixth <= 4'b0000; end
9'b000001000 : begin fifth <= 4'b1000; sixth <= 4'b0000; end
9'b000001001 : begin fifth <= 4'b1001; sixth <= 4'b0000; end
9'b000001010 : begin fifth <= 4'b0000; sixth <= 4'b0001; end
9'b000001011 : begin fifth <= 4'b0001; sixth <= 4'b0001; end
9'b000001100 : begin fifth <= 4'b0010; sixth <= 4'b0001; end
9'b000001101 : begin fifth <= 4'b0011; sixth <= 4'b0001; end
9'b000001110 : begin fifth <= 4'b0100; sixth <= 4'b0001; end
9'b000001111 : begin fifth <= 4'b0101; sixth <= 4'b0001; end
9'b000010000 : begin fifth <= 4'b0110; sixth <= 4'b0001; end
9'b000010001 : begin fifth <= 4'b0111; sixth <= 4'b0001; end
9'b000010010 : begin fifth <= 4'b1000; sixth <= 4'b0001; end
9'b000010011 : begin fifth <= 4'b1001; sixth <= 4'b0001; end
9'b000010100 : begin fifth <= 4'b0000; sixth <= 4'b0010; end
9'b000010101 : begin fifth <= 4'b0001; sixth <= 4'b0010; end
9'b000010110 : begin fifth <= 4'b0010; sixth <= 4'b0010; end
9'b000010111 : begin fifth <= 4'b0011; sixth <= 4'b0010; end
9'b000011000 : begin fifth <= 4'b0100; sixth <= 4'b0010; end
9'b000011001 : begin fifth <= 4'b0101; sixth <= 4'b0010; end
9'b000011010 : begin fifth <= 4'b0110; sixth <= 4'b0010; end
9'b000011011 : begin fifth <= 4'b0111; sixth <= 4'b0010; end
9'b000011100 : begin fifth <= 4'b1000; sixth <= 4'b0010; end
9'b000011101 : begin fifth <= 4'b1001; sixth <= 4'b0010; end
9'b000011110 : begin fifth <= 4'b0000; sixth <= 4'b0011; end
9'b000011111 : begin fifth <= 4'b0001; sixth <= 4'b0011; end
9'b000100000 : begin fifth <= 4'b0010; sixth <= 4'b0011; end
9'b000100001 : begin fifth <= 4'b0011; sixth <= 4'b0011; end
9'b000100010 : begin fifth <= 4'b0100; sixth <= 4'b0011; end
9'b000100011 : begin fifth <= 4'b0101; sixth <= 4'b0011; end
9'b000100100 : begin fifth <= 4'b0110; sixth <= 4'b0011; end
9'b000100101 : begin fifth <= 4'b0111; sixth <= 4'b0011; end
9'b000100110 : begin fifth <= 4'b1000; sixth <= 4'b0011; end
9'b000100111 : begin fifth <= 4'b1001; sixth <= 4'b0011; end
9'b000101000 : begin fifth <= 4'b0000; sixth <= 4'b0100; end
9'b000101001 : begin fifth <= 4'b0001; sixth <= 4'b0100; end
9'b000101010 : begin fifth <= 4'b0010; sixth <= 4'b0100; end
9'b000101011 : begin fifth <= 4'b0011; sixth <= 4'b0100; end
9'b000101100 : begin fifth <= 4'b0100; sixth <= 4'b0100; end
9'b000101101 : begin fifth <= 4'b0101; sixth <= 4'b0100; end
9'b000101110 : begin fifth <= 4'b0110; sixth <= 4'b0100; end
9'b000101111 : begin fifth <= 4'b0111; sixth <= 4'b0100; end
9'b000110000 : begin fifth <= 4'b1000; sixth <= 4'b0100; end
9'b000110001 : begin fifth <= 4'b1001; sixth <= 4'b0100; end
9'b000110010 : begin fifth <= 4'b0000; sixth <= 4'b0101; end
9'b000110011 : begin fifth <= 4'b0001; sixth <= 4'b0101; end
9'b000110100 : begin fifth <= 4'b0010; sixth <= 4'b0101; end
9'b000110101 : begin fifth <= 4'b0011; sixth <= 4'b0101; end
9'b000110110 : begin fifth <= 4'b0100; sixth <= 4'b0101; end
9'b000110111 : begin fifth <= 4'b0101; sixth <= 4'b0101; end
9'b000111000 : begin fifth <= 4'b0110; sixth <= 4'b0101; end
9'b000111001 : begin fifth <= 4'b0111; sixth <= 4'b0101; end
9'b000111010 : begin fifth <= 4'b1000; sixth <= 4'b0101; end
9'b000111011 : begin fifth <= 4'b1001; sixth <= 4'b0101; end
9'b000111100 : begin fifth <= 4'b0000; sixth <= 4'b0110; end
9'b000111101 : begin fifth <= 4'b0001; sixth <= 4'b0110; end
9'b000111110 : begin fifth <= 4'b0010; sixth <= 4'b0110; end
9'b000111111 : begin fifth <= 4'b0011; sixth <= 4'b0110; end
9'b001000001 : begin fifth <= 4'b0100; sixth <= 4'b0110; end
default : begin fifth <= 4'b1111; sixth <= 4'b1111; end
endcase
//Working on the decimal point values.
case (led[6:3])
4'b0000: begin first <= 4'b0000;
second <= 4'b0000;
third <= 4'b0000;
fourth <= 4'b0000;end
4'b0001: begin first <= 4'b0101;
second <= 4'b0010;
third <= 4'b0110;
fourth <= 4'b0000;end
4'b0010: begin first <= 4'b0000;
second <= 4'b0101;
third <= 4'b0010;
fourth <= 4'b0001;end
4'b0011: begin first <= 4'b0101;
second <= 4'b0111;
third <= 4'b1000;
fourth <= 4'b0001;end
4'b0100: begin first <= 4'b0000;
second <= 4'b0000;
third <= 4'b0101;
fourth <= 4'b0010;end
4'b0101: begin first <= 4'b0101;
second <= 4'b0010;
third <= 4'b0001;
fourth <= 4'b0011;end
4'b0110: begin first <= 4'b0000;
second <= 4'b0101;
third <= 4'b0111;
fourth <= 4'b0011;end
4'b0111: begin first <= 4'b0101;
second <= 4'b0111;
third <= 4'b0011;
fourth <= 4'b0100;end
4'b1000: begin first <= 4'b0000;
second <= 4'b0000;
third <= 4'b0000;
fourth <= 4'b0101;end
4'b1001: begin first <= 4'b0101;
second <= 4'b0010;
third <= 4'b0110;
fourth <= 4'b0101;end
4'b1010: begin first <= 4'b0000;
second <= 4'b0101;
third <= 4'b0010;
fourth <= 4'b0110;end
4'b1011: begin first <= 4'b0101;
second <= 4'b0111;
third <= 4'b1000;
fourth <= 4'b0110;end
4'b1100: begin first <= 4'b0000;
second <= 4'b0000;
third <= 4'b0101;
fourth <= 4'b0111;end
4'b1101: begin first <= 4'b0101;
second <= 4'b0010;
third <= 4'b0001;
fourth <= 4'b1000;end
4'b1110: begin first <= 4'b0000;
second <= 4'b0101;
third <= 4'b0111;
fourth <= 4'b1000;end
4'b1111: begin first <= 4'b0101;
second <= 4'b0111;
third <= 4'b0011;
fourth <= 4'b1001;end
default: begin first <= 4'b0000;
second <= 4'b0000;
third <= 4'b0000;
fourth <= 4'b0000;end
endcase
end
endmodule

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