ST approach to “Zero Defects”

in Automotive applications
P. Epigrafi, M. De Tomasi, R. Cea, G. Rota, P. Zabberoni, A. Mervic

ADG Q&R Digital Products

AEC Workshop 2019 – Munich

 Outlook 2

• Introduction

• MCU Test Flow

• Safe Launch approach

• Burn-In curve methodology

 Automotive Products Qualification
3
Approach
• “Zero defect” is an holistic approach that must be embedded since the
initial phases of process and product development
• Overstress to be applied during production screening is considered from initial design
development
• Customer mission profile and requirements considered since process qualification

• Process Qualification ensures that

elementary structures are able to
withstand stress to be applied during test
and Burn-In in production

• Product qualification screens intrinsic

defectivity (design, process …
weaknesses)

• “Safe Launch” verifies that extrinsic

defectivity is correctly screened to allow
start of production
▪ Process Qualification
▪ Product Qualification/Activity
 MCU Test Flow 4

• ADG 32-bit Automotive Microcontrollers include NVM (Flash)

• High Voltage stress performed at EWS to anticipate as much as possible infant
mortality screening
• Single die traceability is implemented up to Final Test, Burn-In included, allowing
• Statistical correlation among different stress steps
• Wafer map reconstruction also at Final Test and Burn-In

Wafer level test (EWS) Package level test (Final Test)

Package
Retention

Retention

Assembly Package test 2

Bake2
Bake1

Test1 Test2 Test3 Burn-In

test1 Max Tj
flash flash SoC 125°C
SoC Test
Full SoC

Flash + Logic
Flash Stresses
High Voltage

High Voltage
LV Stresses

Stresses
 Safe Launch Approach 5

• Safe Launch is a standard Automotive process that is applied

whenever a new silicon technology is deployed in production

• Purpose of Safe Launch is to stress the line during production start-

up to highlight and address potential weaknesses

• During Safe Launch a series of diffusion lots is closely monitored at

different steps (Inline, Parametric Test, EWS, Burn-In, Final Test)
• Results of test are discussed during dedicated Material Review Board
• Correlation between test and wafer defectivity is performed
• Failure Analysis is done on Burn-In class of fails

Feedback
to Fab

In-Line Defectivity map after Gate patterning Failure analysis performed: Polysilicon defect found
correlates with short signature at EWS Root cause identified at lithography step
 Safe Launch
EWS yield loss crown elimination 6

• Yield loss on EWS BIN identified during Safe Launch exercise in

wafer stacked map
• Analysis pointed out defectivity in Flash array at wet resist removal

• Disqualification of involved equipment of wet resist removal

• Reduction of yield loss confirmed on subsequent production material

Disqualification of equipment
Parts failed at EWS
(SBL triggered) Stacked map Stacked map
Yield loss (Different BIN)

Diffusion Lots
 Safe Launch
PAT implementation 7

• As part of Safe Launch process, PAT algorithms

are defined and implemented
• Parametric-PAT
• Automatic detection of distribution shape and algorithm
choice performed by the tool for outlier detection

• Geographic-PAT
• with proximity analysis a good die can be marked as fail,
based on failing neighborhoods
• with cluster analysis an amount of adjacent dies will be
encircled by fail marked dice

• Stacked-PAT
• comparison of the results of the same X-Y coordinates
across the different wafers of the lot
 Burn-In on microcontroller product family
8

• Burn-In is applied to screen infant mortality due to extrinsic defectivity and it

is applied on 100% of MCU production

• Stress is done at hot temperature

• It is focused on logic (Stress on RAM / ATPG / Functional) and Flash memory
• Test During Burn-In (TDBI) is applied, allowing to perform Burn-In data analysis on production
data (typically 1M parts)

• Burn-In curve is performed during Safe Launch on new technologies to fix

Burn-In time for volume production
• Physical failure analysis is done on all the different categories of fails found during the stress,
to provide feedback to the Fab and implement actions to lower defectivity
• Same Burn-In curve methodology is applied to reduce Burn-In time during
mass production

• Overvoltage is applied to reduce time needed to screen infant mortality

• Maximum overvoltage allowed for each technology (Fast Burn-In) has been qualified and
introduced in production
 Flow Chart to fix Burn-In conditions 9

•Mission Profile evaluation vs Wafer Level Reliability qualification

•% of aging accepted at Burn-In
Max Stress •Definition of Voltage and Time to be applied not to overcome allowed % of aging
Allowed at BI •FAST Burn-In: Voltage applied at Burn-In is out of device operative range

•Validation that stress conditions are correctly implemented at product level

Fast BI •Full reliability exercise to confirm that there is no impact on end of life reliability performances
qualification

•Fast Burn-In effectiveness to screen infant mortality is confirmed by using Burn-In curve methodology
Fast BI
effectiveness

•Burn-In Curve performed during Safe Launch activity

•Failure analysis for all fails categories to provide feedback to FAB for defectivity reduction
Safe Launch

Burn-In curves performed during volume production are done on production data to further reduce Burn-In
BI curve on time according to process defectivity improvement
production
 Burn-In Flow 10

• Burn-In main steps are reported in the picture below

• At Burn-In, test on devices is also executed
• Stress on flash and logic is split at least in 6 segment
• Each stress segment is followed by a test step

Stress on Logic and

Stress on Flash
analog

NVM Test NVM Test Stress Test Stress Test

Test
W/E on W/E on on on on on
Pre BI cycles cycles Logic Logic
flash flash logic logic

• This approach allows to perform Weibull curve on Burn-In fails using production
data
 Safe Launch: Burn-In Curve 11

• Burn-In curve exercise is performed during Safe Launch in order to confirm the correct
duration of different Burn-In segment
• Flash stress (Write / Erase cycling)
• Logic stress

Write/Erase cycling failure rate

Total Burn-In flash cycling

• Burn-In stress time is tuned in order to
Margin vs. total Burn-In
# of fails [a.u.]

cycling • Guarantee full screening of defective parts

• Perform cost effective screening of infant mortality

1X
1 2X
2 3X
3 4X
4 5
5X 6
6X 7
7X 8
8X 9X9 10X
10

W/E cycles

Dynamic Burn In Failure Rate

Total Burn-In time
• Burn-In curve methodology is used whenever
Last BI
# of fails [a.u.]

reject
Margin vs. Burn-In time Burn-In time reduction has to be evaluated

1
1X 2
2X 3
3X 4
4X 5
5X 6X6

Dynamic Stress [time]

Failure Analysis on Burn-In Flash Fails 12

• During Safe Launch activity, each fail category at Burn-In is analyzed in Failure
analysis to identify point of failure and provide feedback to fab
• Failure Analysis on Flash Erase Fail occurred during Write/Erase cycles at Burn-In

• Physical failure analysis is consistent with electrical fails found

• Corrective action identified at FAB level
 Failure Analysis on Dynamic Burn-In Fails 13

• Same activity performed also on logic fails found during Dynamic Burn-In
• Failure Analysis performed on RAM Memory fail

• Physical failure analysis is consistent with electrical fails found

• Corrective action identified at FAB level
 Road to 0ppm… 14

• Continuous path to Zero Defectivity requires full commitment of all entities involved
starting from initial design phase, including test and reliability and up to mass
production

• Defective parts are screened since initial testing steps allowing also cost optimization

• Thanks to full traceability, screened parts are analyzed and feedback is provided to
Fab, in order lo lower Inline defectivity

PPM and Production Volumes

Production Volumes
PPM

Production Date

ppm Production Volume

 15

Thank You!