Half-Adder

Basic rules of binary addition are performed by a

Inputs Outputs
half adder, which has two binary inputs (A and B)
A B Cout S
and two binary outputs (Carry out and Sum).
0 0 0 0
0 1 0 1
The inputs and outputs can be summarized on a 1 0 0 1
truth table. 1 1 1 0

The logic symbol and equivalent circuit are:

S S
A S
A
Cout
B Cout B

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Full-Adder
Inputs Outputs

By contrast, a full adder has three binary A B Cin Cout S

0 0 0 0 0
inputs (A, B, and Carry in) and two binary 0 0 1 0 1
outputs (Carry out and Sum). The truth table 0 1 0 0 1
summarizes the operation. 0 1 1 1 0
1 0 0 0 1
A full-adder can be constructed from two 1 0 1 1 0
half adders as shown: 1 1 0 1 0
1 1 1 1 1

S
A S
B
Cout
Cin

Symbol

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
4
5
 Full-Adder

S S
A A S A S Sum
S
B B Cout B Cout A S
B
Cout
Cin Cin

Cout Symbol

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Parallel Adders
Full adders are combined into parallel adders that can add binary
numbers with multiple bits. A 4-bit adder is shown.
A4 B4 A3 B 3 A 2 B2 A1 B1

C0

A B Cin A B Cin A B Cin A B Cin

Cout S Cout S Cout S Cout S

C4
C3 C2 C1
S4 S3 S2 S1

The output carry (C4) is not ready until it propagates through all of the
full adders. This is called ripple carry, delaying the addition process.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Parallel Subtractor
• Use 2’s complement with binary adder
x – y = x + (-y) = x + y’ + 1

x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

F3 F2 F1 F0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Parallel Adder/Subtractor
• M: Control Signal (Mode)
• M=0  F = x + y
• M=1  F = x – y x3 x2 x1 x0 y3 y2 y1 y0 M

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0

F3 F2 F1 F0
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Decoders
• Extract “Information” from the code
Only one
• Binary Decoder lamp will
– Example: 2-bit Binary Number turn on

1
x1 0 0
Binary
0
x0 0 Decoder
0
 Decoders

Y3
• 2-to-4 Line Decoder

y3 Y2

Decoder
I1 Binary
y2
y1 Y1
I0 y0
Y0
I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1 I1
0 1 0 0 1 0 I0
1 0 0 1 0 0
Y3  I1 I 0 Y2  I1 I 0
1 1 1 0 0 0
Y1  I1 I 0 Y0  I1 I 0
 Decoders
• 3-to-8 Line Decoder Y7  I 2 I1 I 0

Y6  I 2 I1 I 0
Y7 Y5  I 2 I1 I 0
Y6
Y5 Y4  I 2 I1 I 0
Decoder

I2
Binary

Y4 Y3  I 2 I1 I 0
I1 Y3
I0 Y2 Y2  I 2 I1 I 0
Y1 Y1  I 2 I1 I 0
Y0
Y0  I 2 I1 I 0

I2
I1
I0
 Decoders
• “Enable” Control
Y3

Y3

Decoder
I1 Y2
Binary Y2
I0 Y1
E Y1
Y0
Y0
E I1 I0 Y3 Y2 Y 1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
 Decoders
• Active-High / Active-Low

I1 I0 Y 3 Y 2 Y 1 Y 0 I 1 I0 Y 3 Y 2 Y 1 Y 0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
Y3
1 1 1 0 0 0 1 1 0 1 1 1
Y2

Y1
Y3 Y3
Decoder

I1 I1 Decoder
Binary

Binary
Y2 Y2 Y0

Y1 Y1
I0 Y0 I0 Y0 I1
I0
 Decoders
• Each output is a minterm
Binary
• All minterms are produced Decoder
• Sum the required minterms
Y7
Y6
Example: Full Adder Y5
S(x, y, z) = ∑(1, 2, 4, 7) x I2 Y4
C(x, y, z) = ∑(3, 5, 6, 7) y I1 Y3
z I0 Y2
Y1
Y0

S C
 Encoders
• Put “Information” into code
Only one
• Binary Encoder
switch
– Example: 4-to-2 Binary Encoder
should be
activated
at a time

x3 x2 x1 y1 y0
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
1 0 0 1 1
 Encoders
• Put “Information” into code
• Binary 8 to 3 encoder
I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
I5

Encoder
0 0 0 0 0 0 0 1 0 0 0 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0 I3 Y0
0 0 0 0 1 0 0 0 0 1 1 I2
0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 Encoders
Y2  I 7  I 6  I 5  I 4
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 Y1  I 7  I 6  I 3  I 2
0 0 0 0 0 0 0 1 0 0 0
Y0  I 7  I 5  I 3  I1
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
I7
0 0 0 1 0 0 0 0 1 0 0 I6 Y2
0 0 1 0 0 0 0 0 1 0 1 I5
0 1 0 0 0 0 0 0 1 1 0 I4
I3 Y1
1 0 0 0 0 0 0 0 1 1 1
I2
I1
I0 Y0