Exercises, set 6.

INTRODUCTION TO HARDWARE DESIGNING – SEQUENTIAL CIRCUITS.

1. Lathes and flip-flops.

In the same way that gates are basic building blocks of combinational (combinatorial)
circuits, latches and flip-flops are the building blocks of sequential circuits. While gates have
to be built directly from bipolar or FET transistors, latches can be built from gates, and flip-
flops can be built from latches.
Both latches and flip-flops are circuit elements with memory. Their output depends not
only on the current inputs, but also on previous outputs. The difference between a latch and a
flip-flop is that a latch does not have a synchronizing clock signal, whereas a flip-flop always
does. In other words, latches are basic elements of asynchronous sequential circuits, flip-flops
are basic elements of synchronous ones.

1.1. Asynchronous lathes – analysis of SR-Lath.

The way we can force the circuit to remember previous state and take it into
consideration when changing to new state is the feedback. We have to create loops in the
circuit diagrams, and this way the output values depend (indirectly) on themselves. It’s
important to remember that the feedback in electronic circuits can be a reason of their
instability (the circuit then becomes an oscillator).
The simplest latch we can build using two NOR gates is called SR-Latch (or RS-Latch)
and is shown on diagram below.
S
(set) ¬Q (inverted output value)
S Q
≡
R ¬Q

R Q (output value)
(reset)
On this diagram we can see that the latch consists of two logical gates, has two inputs
(set and reset) and it’s very easy to provide output (Q) as ”straight” and inverted value (¬Q)
at the same time.
It’s not very good idea to start learning about asynchronous circuits like RS-Latch using
methods known from combinational circuits designing. These methods will be more
convenient on some steps of synthesis of the synchronous circuits. In the beginning we should
rather use our intuition and/or try to simulate the behavior of this latch with appropriate
software tools (like LogiSim, for example). The procedure (one of the procedures) for
designing the sequential circuits will be described in Chapter 2.
Let’s try to analyze the possible behavior of SR-Latch starting with both inputs (S and
R) equal to 0. In fact, two different states are possible at this moment: with Q = 0 or Q = 1:
State = QSR 0 1 0
S ¬Q S 0
¬Q
0 1
State 000 State 100
1 0
0 1
0 Q 0 Q
R R

1
 Now we will set the S input to 1 for each of two initial states shown above (we are
assuming that the set and reset inputs shouldn’t be set to 1 at the same moment):
State = QSR 0 1 1 0
S ¬Q S ¬Q
0 S ¬R 1
State 000 State 110
1 0
0 1
0 Q 0 Q
R
0 0 1
S ¬Q S 0
¬Q
1 S ¬R 1
State 100 State 110
0 0
1 1
0 Q 0 Q
R R
Regardless of initial state (State 000 or State 100) we’ve came to the same current state
(State 110), defined by values of all inputs and output (the ¬Q signal is not an independent
output, so we are taking the combination of QSR values as the status of the circuit). The
output (Q) value becomes 1 after setting S input to 1. In fact, the value of 1 on input of upper
gate forces the output of this gate to become 0 (we can check it in the table of truth for NOR
function). That gives 0 on both inputs of lower gate and finally 1 o its output.
Now let’s try to set the S input back to 0. This will not change the output from upper
gate (lower input is still 1, so the NOR function returns 0). So the output value is also the
same as previous (in State 110), but the input values are different. It’s easy to check that we
have returned to State 100:
1 0 0 0
S ¬Q S ¬Q
1 1
¬S ¬R State 100
State 110 0 0
1 1
0 Q 0 Q
R R

Now, having the output value of 1, we will set the R input to 1:

0 0 S 0 1
S ¬Q ¬Q
1 0
State 100 ¬S R State 001
0 1
1 0
0 Q 1 Q
R R

The 1 value on any of inputs of lower gate sets its output (Q) to 0 (we have reset the
output to 0). This value passed to lower input of upper gate, while its upper input is 0, sets the
¬Q output to 1. The output values (¬Q Q) are the same as they was for State 000, but the
combination of inputs (¬S R) is different. So we have passed to quite new State 001. Setting R
input to 0 in this state doesn’t change the output, the combination of values S, R and Q (000)
shows that we are back in State 000:
0 S 0 1
S 1 ¬Q
¬Q
0 0
State 001 ¬S ¬R State 000
1 1
0 0
1 Q 0 Q
R R

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 Other possible way to go out from State 001 is to set R input to 0 and S input to 1 at the
same moment (this is not always possible, for asynchronous circuits especially – try to do it
with simulator…). The circuit will then return back to State 110.
0 S 1 0
S 1 ¬Q
¬Q
0 1
State 001 S ¬R State 110
1 0
0 1
1 Q 0 Q
R R

Now let’s try to go out from State 000 setting the R input to 1 (the opposite combination
of S = 1 and R = 0 we’ve checked at the beginning). Now we are passing from State 000 back
to State 001:
0 1 0 1
S S ¬Q
0 ¬S R 0
State 000 State 001
1 1
0 0
0 1 Q
R R
We have tried to go out from State 001 changing the value of R input from 1 to 0, the
result was State 000. The second theoretically possible way out (setting S input to 1 when R
input is already set to 1) doesn’t make sense from the point of view of the definition of this
circuit (what we want to do: set or reset the output value?). For SR-Latches this combination
of inputs is simply not defined and should never happen.
The same situation we can encounter trying to analyze way out from State 110 with
setting R input to 1 (the combination of ¬S ¬R leads to State 100).
The last thing to do is to check, what happens if we try to go out from state 000 setting
the R input to 1. This change doesn’t affect the output from lower gate, nor output of the
entire circuit. The only difference is the different State 001, which we’ve already defined:
0 1 0 1
S ¬Q S ¬Q
0 ¬S R 0
State 000 State 001
1 1
0 0
0 Q 1 Q
R R

This step-by-step analysis shows, that circuit works as it was assumed: the active signal
on S input sets the memorized value of output to 1, the R input resets this value to 0. The
disadvantage of this circuit is lack of well-defined reaction for (disabled) combination of both
inputs active.
More formally we can describe the function of sequential circuit using table of truth or
drawing the graph representing all possible states the circuit can distinguish and all passes
between these states, caused by possible combinations of S and R input signals (that means:
00, 01, 10). The table of truth for this asynchronous SR-Latch looks like this:
Q S R New Q
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Not used
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Not used

3
 Please notice, that table of truth includes two shadowed states (010 and 101) which are
not seen while analyzing the circuit using intuition only. We can explain it easily:
− when the output Q = 0 and the input S (set) value is 1, the latch will immediate change
the output value to Q = 1 (State 110); so the State 010 is unstable, the circuit passes to
the State 110 without changing the inputs.
− when the output Q = 1 and the input R (reset) value is 1, the latch will immediate
change the Q output value to Q = 0; so the Status 101 is unstable too, the circuit passes
to the State 001 without changing the inputs.
Knowing all these things we can illustrate the results of our analysis with the graph of
passes between the states. The unstable states (010 and 101) are shadowed, as they were in the
table of truth. It’s easy to see, that all stable states have loops (like pass 00 for State 000),
which show that they are not changing if combination of inputs doesn’t change. The
theoretically only possible passes from unstable states are shown with dotted arrows (like 10
for State 101). They could be possible only if we change the combination of inputs before
circuit pass to appropriate stable state.

01 10
101
00

00 00
000 100 00
10 10
01 10 00 01
110 10
010
01 10
00 01
001

01

The process shown above was just analysis of the circuit. For designing we will need
the synthesis procedure rather. Two important things we will assume before starting with
synthesis of simple sequential circuits:
− The synthesis of asynchronous circuits is much harder than synthesis of synchronous
ones (that means circuits which are passing from one state to another only after one
entire clock cycle on synchronization input). In the Chapter 2. we will discuss the
method suitable for synchronous circuits, using synchronous flip-flops instead of
asynchronous lathes.
− In example shown above we were defining the unique states of circuit using each unique
combination of one output and two inputs as one state. A bit different approach is used
in practical design methods, using internal states (defined by outputs of flip-flops used
in design) rather than direct output values.
1.2. Synchronous flip-flops.
1.2.1. Synchronous D flip-flop.
The D flip-flop is easiest for intuitive understand as simple, one-bit synchronous
memory element. It’s function is to store the bit provided to single data-input (D) after one
clock cycle. In other words, the information on output (Q) at the end of cock cycle is equal to

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information seen by input at the beginning of clock cycle. Having the elementary (one-bit)
memory cells like this, we can arrange them in longer words (registers) and entire RAM
memory arrays.
The graphical symbol and different formal descriptions of D flip-flop are shown below:
Graphical Characteristic State transition table Karnaugh map Excitation table
symbol table (table of truth) for Qn+1

Qn Dn Qn+1 Qn Qn+1 Dn
Qn+1
Dn Qn+1 Dn
D Q 0 0 0 Qn 0 1 0 0 0
CLK 0 0 0 1 1 0 0 1 0 1 1
¬Q
1 1 1 0 0 1 0 1 1 0 0
Qn+1 = Dn
1 1 1 1 1 1

The characteristic table shows (in most compact form), what combinations of inputs
force which new state of output. Sometimes the information about current state encoded in
different forms is added on the left-side of this table.
The state transition table in form shown above defines the passes between different
states, as it was described in Chapter 1.1. for asynchronous circuit. This time we should
interpret the Qn value as current state and Dn as an event (excitation) on input, which may
cause the transition to other state. This table sows each possible combination of current state
and input values (excitations).
The Karnaug map can be used to minimize the function of the circuit and show it in
form of shortest algebraic formula, as it was shown for combinational circuits.
The excitation table shows the minimum inputs that are necessary to generate a
particular next state when the current state is known. It is similar to table of truth (state
transition table), but rearranges the data so that the current state and next state are next to each
other on the left-hand side of the table, and the inputs needed to make that state change
happen are shown on the right side of the table.
The implementation of synchronous flip-flops in many cases utilizes master-slave idea,
that means two flip-flops are connected in chain. The data from input is read on the rising
edge (or high level) of clock signal by the first flip-flop (master), the second one (slave) reads
and stores the data for output on the falling edge (or low level) of this clock pulse. In other
words the master-slave flip-flop is pulse triggered (entire clock pulse is needed to change the
state of flip-flop). This makes the flip-flop less sensitive for temporary fluctuations of input
signal, which may be caused by different delays of signals (races).
Interesting example is the implementation of the synchronous master-slave D flip-flop
from two asynchronous SR-latches. Finally, we can show that synchronous flip-flop can be
built of simple logical gates:
SR flip-flop #1 (master) SR flip-flop #2 (slave)
D S1 ¬Q1 S2
¬Q2
¬Q

Q1 Q2
R1 R2 Q

CLK

5
 To make the circuit synchronous, each input of asynchronous latch is gated (using AND
gate) with clock signal (inverted for slave section of circuit). To make D flip-flop from SR we
have connected R input with inverted S signal (so only two input combinations of 01 and 10
are now possible). The simulation of this circuit (using LogiSim, for example) and observing
signals like Q1, Q and others or comparison with non master-slave flip-flop (from ”memory”
library of LogiSim) can show, how it really works.
One more thing which we should notice is, that we can spare one NOT inverter
connecting the input R2 of the slave section directly to inverted output ¬Q1 from the master
section of the circuit. Maybe it’s not much important in this very simple example, but it can
help to reduce number of elements in integrated circuits utilizing thousands and millions of
flip-flops. Another advantage is shorter time of signal propagation in the circuit (each gate has
a delay-time).
1.2.2. Synchronous SR flip-flop.
As it was mentioned above, it’s easy to implement the synchronous flip-flop from
asynchronous latch. All we need is to gate the input signals with synchronizing clock signal,
to have pulse-triggered flip-flops we should connect two single ones in master-slave chain. So
there’s no problem with implementation of synchronous SR flip-flop.
The graphical symbol and different formal descriptions of SR flip-flop are shown
below:
Graphical Characteristic State transition table Karnaugh map Excitation table
symbol table (table of truth) for Qn+1

Sn Rn Qn+1 Qn Sn Rn Qn+1 Qn Qn+1 Sn Rn

Qn+1
SnRn
S Q 0 0 Qn 0 0 0 0 Qn 00 01 11 10 0 0 0 any
CLK 0 1 0 0 0 1 0 0 0 0 ? 1 0 1 1 0
R ¬Q
1 0 1 0 1 0 1 1 1 0 ? 1 1 0 0 1
1 1 ? 0 1 1 ? Sn 1 1 any 0
1 0 0 1 ¬Rn Qn
1 0 1 0
Qn+1 = Sn + ¬Rn Qn
1 1 0 1
1 1 1 ?

As it was mentioned before for asynchronous SR-Latch, the input combination of S = 1

and R = 1 is not allowed, so it is also not pointed out in excitation table for synchronous SR
flip-flop (designer must avoid this combination of input values using SR flip-flops).
Some rows in the excitation table are also glued together in comparison with table of
truth – passing from state Qn = 0 to state Qn+1 = 0 with Sn = 0 doesn’t depend on Rn input;
passing from state Qn = 1 to state Qn+1 = 1 with Rn = 0 doesn’t depend on Sn input.
1.2.3. Synchronous JK flip-flop.
The difference between SR and JK flip-flops relies on that input combination of J = 1
and K = 1 is allowed and changes the output state Q of the flip-flop to opposite value, that
means Qn+1 = ¬Qn when J = K = 1. The rest works exactly the same (assuming J replaces S
and K replaces R). This kind of flip-flop (implemented as master-slave usually) is most
flexible as far as functionality is concerned.

6
 The graphical symbol and different formal descriptions of JK flip-flop are shown below:
Graphical Characteristic State transition table Karnaugh map Excitation table
symbol table (table of truth) for Qn+1

Jn Kn Qn+1 Qn Jn Kn Qn+1 Qn Qn+1 Jn Kn

Qn+1 Jn ¬Qn
JnKn
J Q 0 0 Qn 0 0 0 0 Qn 00 01 11 10 0 0 0 any
CLK 0 1 0 0 0 1 0 0 0 0 1 1 0 1 1 any
K ¬Q
1 0 1 0 1 0 1 1 1 0 0 1 1 0 any 1
1 1 ¬Qn 0 1 1 1 Sn 1 1 any 0
1 0 0 1 ¬Kn Qn
1 0 1 0 Qn+1 = Jn ¬Qn + ¬Kn Qn
1 1 0 1
1 1 1 0

We can consider also that using JK flip-flop with J = K = 1 is the easy way to divide the
clock frequency by two (”counting two”).
1.2.4. Synchronous T flip-flop.
The T (toggle) flip-flop changes the output Q value to opposite if there’s a 1 on it’s T
input and leaves the output unchanged when T = 0.
The graphical symbol and different formal descriptions of T flip-flop are shown below:
Graphical Characteristic State transition table Karnaugh map Excitation table
symbol table (table of truth) for Qn+1
Qn+1
Qn Tn Qn+1 Tn Qn Qn+1 Tn
0 1
Tn Qn+1 Qn
T Q 0 0 0 1
0 0 0
0 0
CLK 0 Qn
0 1 1 1 0 0 1 1
¬Q 1
1 ¬Qn
1 0 1 1 0 1
Qn+1 = Tn ¬Qn + ¬Tn Qn
1 1 0 Qn+1 = Tn ⊕ Qn 1 1 0

1.2.5. General considerations about synchronous flip-flops.

Most of practically implemented and available on market (as TTL or C-MOS integrated
circuits) flip-flops are similar to shown above, but usually they have additional asynchronous,
programming inputs Preset and Clear. In general we can assume, that:
− the input signals should be connected to synchronized, ”informational” inputs according
to the state transition table of particular flip-flop;
− clock pulse makes the influence of these inputs on status (output) of flip-flop possible;
− the status of flip-flop can be initiated regardless of clock and synchronized inputs with
asynchronous, programming inputs (Preset sets the output value to 1, Clear resets to 0).

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2. Synthesis of sequential circuits.
2.1. Basic definitions.
The sequential circuits, from the abstract point of view, are considered as finite state
machines (FSM) or finite state automates. This is a model of behavior composed of a finite
number of states, transitions (passes) between those states, and actions which are initiating
these transitions.
There are two types (conceptual models) of finite state machine that can be built from
sequential logic circuits:
− Moore machine – the output depends only on the (memorized) internal state: Y = f(Q).
Since in synchronous circuits the internal state only changes on a clock edge, the output
only changes on a clock edge too.
− Mealy machine – the output depends not only on the internal state, but also on the
inputs: Y = f(Q, X).
It’s possible to prove that these approaches are equivalent, that means for each possible
design we can use Mealy or Moore model. The diagram below illustrates both these concepts
for synchronous sequential automates.
Mealy approach:
x0 Finite State Machine (FSM) y0
x1 Combinational circuit
y1 Y = f(Q, X)
X … (gates)
… Moore approach:
xn ym
Y = f(Q)
Memory of the state
(flip-flops)
Q = {q0, q1, …, qk}

CLK
2.2. Design procedure for Moore machine.
The following steps we have to perform to complete designing procedure based on
Moore approach:
− Functional description – starts with not strictly formalized verbal description, should be
accomplished with formal definition of circuit’s algorithm (graph and state transition
table), which defines:
− all the unique states the circuit can distinguish;
− the values of outputs y0, .., ym for each state;
− the conditions for passes between states (reactions for different input
combinations x0, .., xn in each state).
− Defining state variables and encoding the states – each state defined in first step should
be encoded with unique code using different values of state variables q0, .., qk
(practically the outputs of flip-flops). The number of state variables should be large
enough to encode all states.
− State transition and output table – using the codes of states established in second step
we should compose the table similar to that defined in first step, but with appropriate
codes of states.

8
 − Choosing the flip-flop type – most of designs use D or JK flip-flops to store the values
of state variables. The outputs of flip-flops are set after each clock pulse by their input
signals (D for D flip-flop or J and K for JK flip-flop), depending on current output
value. The input values are established by excitation functions provided by
combinational section of the circuit, taking into consideration the current values of state
variables (current outputs of flip-flops) and values of input signals. The desirable new
values of state variables will be established by flip-flops, according to their own
excitation tables.
− Composing the excitation table and defining excitation functions – knowing the
behavior of chosen flip-flops we can point out the values of signals which should be
delivered to their inputs to force passing from each current state to the desirable new
state. These input signals define the combinational excitation functions for flip-flops.
We can minimize these functions (using Karnaugh maps, for example) and implement
them with logical gates.
− Output functions – in Moore’s approach, the output values are combinational functions
of state variables only. So it’s relatively easy to define and minimize logical functions
which convert the code of each internal state to set of output values.
− Circuit’s diagram – having all the information needed to define the connections between
different gates and flip-flops we should draw the diagram of the circuit. This can be
verified using simulation software.
− Choosing elements – the flip-flops and gates are implemented in different technologies
by series of integrated circuits. Using the catalogue of chips, we should choose the
appropriate elements and rearrange the diagram adding the information about each gate
and / or flip flop (which chip and which pin derives each input and output signal).
2.3. Example design – reversible counter.
The circuit we are trying to design should be ”programmable” cyclic counter, which
counts clock pulses modulo 4. The direction of counting (incrementing or decrementing the
output value) should depend on ”programming” input. We assume, that circuit should have
two informational inputs:
− Direction of counting (x1) – if the value of this input will be 1, the counter will be
incrementing the output value, for x1 = 0 the value will be decremented.
− Counting enable (x0) – counter will be counting only when there’s 1 on this input,
otherwise the output value will be left unchanged.

Direction of counting x1 y1
enable x0
Counting enable Reversible counter y0 Y – Output value (modulo 4)

CLK
After this description we should draw the diagram of states and compose the first
version of state transition table for our circuit.
Each state on diagram is described by its unique name (S0, S1, S2, S3). The output
values for each state are shown nearby (Y = 10 for S2 means y1 = 1 and y0 = 0 in this state, for
example). According to Moore’s approach, the output values will be the combinational
functions of state codes, which we will define in the next step.

9
 ¬x1 ¬x0
Y = 00 x1 ¬x0
S0
x1 x0 x1 x0
¬x1 x0 ¬x1 ¬x0
¬x1 ¬x0 ¬x1 x0 x1 ¬x0
x1 ¬x0 S1
S3
Y = 01
Y = 11 ¬x1 x0
¬x1 x0
x1 x0

x1 x0 S2
Y = 10 ¬x1 ¬x0
x1 ¬x0

State transition table, based on this diagram, will look like this:
Current state Condition Next sate Output (current)
x1 x0 y1 y0
S0 0 0 S0 0 0
0 1 S3
1 0 S0
1 1 S1
S1 0 0 S1 0 1
0 1 S0
1 0 S1
1 1 S2
S2 0 0 S2 1 0
0 1 S1
1 0 S2
1 1 S3
S3 0 0 S3 1 1
0 1 S2
1 0 S3
1 1 S0
After formal specification we should go to second step of design procedure – defining
of the state variables and encode each state with unique combinations of these variables. In
our example we have defined 4 different states, so 2 bits (2 state values: q0 and q1) will be
enough to encode each state.
It is reasonable to use for subsequent states the binary codes which differ on one
position only (Grey code), less changes in signals help keep the circuit less sensitive for
hazards and races. This can also help us with further optimization of logical functions. So our
state encoding should look like this:
State Code
q1 q0
S0 0 0
S1 0 1
S2 1 1
S3 1 0
Next step of procedure is to combine the first form of state transition table with
combinations of state values.

10
 Current state Code Condition Next sate Code Output
q1 q0 x1 x0 q1 q0 y1 y0
S0 0 0 0 0 S0 0 0 0 0
0 1 S3 1 0
1 0 S0 0 0
1 1 S1 0 1
S1 0 1 0 0 S1 0 1 0 1
0 1 S0 0 0
1 0 S1 0 1
1 1 S2 1 1
S2 1 1 0 0 S2 1 1 1 0
0 1 S1 0 1
1 0 S2 1 1
1 1 S3 1 0
S3 1 0 0 0 S3 1 0 1 1
0 1 S2 1 1
1 0 S3 1 0
1 1 S0 0 0
Now we have to decide, which type of flip-flop should be used in our design. Most clear
excitation table has the D flip-flop (we should simply provide to its input the same value,
which we want to have on output, also the number of inputs couldn’t be less). So let’s assume
the D flip-flop for further steps. We will need 2 such flip-flops (one for each state variable, of
course).
The last form of state transition table will be enlarged to excitation table, with the values
of signals we should provide to inputs of flip-flops to force passes defined in the table.
Current state Code Condition Next sate Code Flip-flops Output
q1 q0 x1 x0 q1 q0 D1 D0 y1 y0
S0 0 0 0 0 S0 0 0 0 0 0 0
0 1 S3 1 0 1 0
1 0 S0 0 0 0 0
1 1 S1 0 1 0 1
S1 0 1 0 0 S1 0 1 0 1 0 1
0 1 S0 0 0 0 0
1 0 S1 0 1 0 1
1 1 S2 1 1 1 1
S2 1 1 0 0 S2 1 1 1 1 1 0
0 1 S1 0 1 0 1
1 0 S2 1 1 1 1
1 1 S3 1 0 1 0
S3 1 0 0 0 S3 1 0 1 0 1 1
0 1 S2 1 1 1 1
1 0 S3 1 0 1 0
1 1 S0 0 0 0 0
It’s easy to observe that the added columns, which describe the excitations of D1 and D0
flip-flops are (when we are using D flip-flops) exactly the same as the columns which
describe the codes of desired next states.
Now we should minimize the combinational excitation functions D1 and D0 using
Karnaugh maps and, eventually, making some arithmetical transformations.

11
 D1 q1q0 D0 q1q0
x 1x 0 00 01 11 10 x1x0 00 01 11 10

00 0 0 1 1 00 0 1 1 0
01 1 0 0 1 01 0 0 1 1
11 0 1 1 0 11 1 1 0 0
10 0 0 1 1 10 0 1 1 0

D1 = q1 ¬x0 + ¬q0 ¬x1 x0 + q0 x1 x0 D0 = q0 ¬x0 + q1 ¬x1 x0 + ¬q1 x1 x0

D1 = q1 ¬x0 + x0 (¬q0 ¬x1 + q0 x1) D0 = q0 ¬x0 + x0 (q1 ¬x1 + ¬q1 x1)
D1 = q1 ¬x0 + x0 ¬(q0 ⊕ x1) ← XNOR D0 = q0 ¬x0 + x0 (q1 ⊕ x1) ← XOR

The ”⊕” symbol means EXOR (Exclusive OR) operation, which is implemented in easy
accessible integrated circuits (TTL of series 74, for example). The inverted XOR (XNOR) is
also accessible as standard logical gate. Using these gates simplifies both functions.
The last step which demands some calculations is to define the output functions y1 and
y0 from status variables for each state. We can start with following table of truth:
State Code Output
q1 q0 y1 y0
S0 0 0 0 0
S1 0 1 0 1
S2 1 1 1 0
S3 1 0 1 1
Now we can try to minimize the functions y1 and y0:

y1 q1 y0 q1
0 1 q0 0 1
q0
0 0 1 0 0 1
1 0 1 1 1 0

y1 = q1 y0 = ¬q1 q0 + q1 ¬q0
y0 = q1 ⊕ q0
Finally we should draw the diagram of the entire circuit:

x1
q1
x0 D Q y1
y0

q0
D Q

CLK

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Exercises:

1. Using LogiSim prepare simulation of asynchronous SR-Latch built of NOR gates.

Observe behavior of circuit for disabled combination of inputs (S = 1 and R =1).
2. Using LogiSim prepare simultaneous simulation of normal D flip-flop (from ”Memory”
library of LogiSim) and two master-slave D flip-flops: first built of two normal flip-
flops and second built of NOR gates. Observe differences in behavior of these circuits in
different moments of simulated clock pulse.
3. Prepare simulation of reversible counter described in example design using LogiSim.
4. Re-design the counter shown in example using JK flip-flops instead of D ones:
− verify the state transition table (excitation table) for JK flip-flops shown below (the ”-”
symbol means ”any” and can be ”glued” with neighboring 1 in Karnaugh map);
− minimize the excitation functions for JK flip-flops (use Karnaugh maps, then EXOR
and EXNOR gates);
− use the same output function as it was defined before (this function for Moore’s
automat depends on state variables only);
− draw the diagram of the circuit with JK flip-flops;
− perform the simulation of this circuit with LogiSim.
Current state Code Condition Next sate Code Flip-flops Output
q1 q0 x1 x0 q1 q0 J1 K1 J0 K0 y1 y0
S0 0 0 0 0 S0 0 0 0 - 0 - 0 0
0 1 S3 1 0 1 - 0 -
1 0 S0 0 0 0 - 0 -
1 1 S1 0 1 0 - 1 -
S1 0 1 0 0 S1 0 1 0 - - 0 0 1
0 1 S0 0 0 0 - - 1
1 0 S1 0 1 0 - - 0
1 1 S2 1 1 1 - - 0
S2 1 1 0 0 S2 1 1 - 0 - 0 1 0
0 1 S1 0 1 - 0 - 0
1 0 S2 1 1 - 0 - 0
1 1 S3 1 0 - 0 - 1
S3 1 0 0 0 S3 1 0 - 0 0 - 1 1
0 1 S2 1 1 - 0 1 -
1 0 S3 1 0 - 0 0 -
1 1 S0 0 0 - 1 0 -
5. Using the designing procedure described in Chapter 2. prove, that it’s easy to convert:
− D flip-flop into the JK flip-flop (the circuit consists of one D flip-flop and a few
logical gates);
− JK flip-flop into the D flip-flop (the circuit consists of one JK flip-flop and one NOT
inverter).
Perform the simulation of designed circuits with LogiSim.

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