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Assignment 3 With Solution

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anoopaman5
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COIS 2300H – Computer Organization

Assignment 3— the Processor

Note. The assignment should be attempted through individual efforts, and any
concerns related to academic integrity will be handled in accordance with the
university's guidelines

Objectives:

This assignment examine your understanding the processor design and


performance concepts. To cover these concepts, answer the bellow questions:

Fall 2023
COIS 2300H – Computer Organization

Assignment 3— the Processor

Question 1. Given the following full Datapath of a simple CPU implementation


(Slide number 27 – Chapter 4).

a) What are the values of the control signals for the instruction as listed in the below table?

Instruction RegDst Branch MemRead MemReg ALUO MemWrite ALUSrc RegWrite


p

Fall 2023
COIS 2300H – Computer Organization

Assignment 3— the Processor

add $s1, $S3, $S2 1 0 0 0 1 0 0 1 1


addi $S3, $S2, 50 1 0 0 0 1 0 0 1 1
lw $t1, 32($s1) 1 0 1 1 0 0 0 1 1
sw $s1, 8($s3) 1 0 0 1 0 0 1 1 0
beq $s0,$s1, 120 1 1 0 1 0 1 0 0 0
b) Assume that the PC value for all instructions is 0x00af1511. What is the value of the
Program Counter (PC) after executing the following instructions? Assume that all
conditions are true.

Instruction PC
add $s1, $S3, $S2 0x00af1511
bne $s0,$s1, 8 (0x00af1511+4) and branch location (8)
lw $t1, 32($s1) ((0x00af1511+4) and branch location (8))+4
sw $s1, 8($s3) (((0x00af1511+4) and branch location (8))+4)+4
beq $s0,$s1, 4 ((((0x00af1511+4) and branch location (8))+4)+4) and new branch location
(4)
j 2000 (((((0x00af1511+4) and branch location (8))+4)+4) and new branch location
(4) & new branch location (2000)

Question 2. Recall that the clock cycle time in a non-pipelined processor is


determined by the instruction (considering all stages) that takes the longest
time to execute as no instruction can take more than one cycle. In a pipelined
datapath, the cycle time is determined by the individual stage that takes the

Fall 2023
COIS 2300H – Computer Organization

Assignment 3— the Processor

longest time as each cycle will execute exactly one stage. Now assume the
distribution of time required by independent stages are as follows:

IF ID EX MEM WB
250 350 150 300 200

Now answer the following questions:

a) What should be the clock cycle time for a non-pipelined and a pipelined
processor? Provide justification for your answer.

Answer: For non-pilelined processor, one instruction completes in one


cycle. The instruction that requires the longest time will decide the cycle
time. Load word (lw) is the instruction that uses all stages. And so, the
cycle time will be: 150+350+150+300+200

For pipelines processor, one stage completes in one cycle. The longest
stage will decide the cycle time. That’s why the cycle time is 350 (ID
stage).

b) How long will it take to execute the lw instruction in a non-pipelined


processor? Why?

Answer: as explained in (a), lw will take one cycle and for non-pipelined
one cycle time = 150+350+150+300+200

Fall 2023
COIS 2300H – Computer Organization

Assignment 3— the Processor

c) How long will it take to execute the lw instruction in a pipelined


processor? Why?

Answer: In a pipelined processor, lw will require to go through all stages.


As we saw in (a), the cycle time is the longest stage: 350. Total 5 cycles will
be required for 5 stages. So, total time = 5*350

Question 3. The following MIPS code might produce data hazard when
executed. Study the code and answer the following questions:

lw $t0, 0($a0)
add $t2, $t0, $t1
sw $t2, 4($a0)

d) Explain the nature of the data hazard and identify the instructions involved.

Answer. The data hazard in the given MIPS code is a Read-After-Write (RAW) hazard.
This occurs because Instruction 2 depends on the result of Instruction 1, and Instruction 3
depends on the result of Instruction 2.

e) Explain how the data hazard affects the pipeline stages.

Answer. The data hazard affects the ID and EX stages. In the ID stage, the hazard is
detected, and in the EX stage, the hazard can lead to a stall or bubble in the pipeline.

f) Discuss potential pipeline stalls or bubbles and their impact on performance.

Fall 2023
COIS 2300H – Computer Organization

Assignment 3— the Processor

Answer. Pipeline stalls or bubbles may occur as the dependent instruction (e.g.,
Instruction 2) waits for the result of the previous instruction (e.g., Instruction 1).

g) Discuss possible techniques for resolving the data hazard.

Answer. Forwarding or data forwarding can be used to resolve the data hazard. This
involves providing the necessary data directly to the dependent instruction without
waiting for it to be written to the register file. In this case, forwarding would involve
forwarding the result from Instruction 1 to Instruction 2 and from Instruction 2 to
Instruction 3.

h) Propose modifications to the code to avoid or minimize the data hazard.

Answer. To avoid the hazard, the code can be modified by rearranging the
instructions or using different registers to eliminate the dependency.

For example, Instruction 1 and Instruction 2 could be swapped but add another
instruction to make the value of $t0 available, or different temporary registers or
buffers could be used in each instruction to break the dependency chain.

Deliverables:

Download this word document, answer the questions on it and save as


pdf for submission.
Note: Do not Zip your submissions. Zipped submissions will NOT be
graded.

Fall 2023

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