Bilkent University EEE313: Electronic Circuit Design Spring 2019-20, 01.06.

2020
FINAL EXAM

• Find the symbolic expression first and then plug in the numerical values for all
your answers

• Show all the derivation for your answers, no points will be given to direct
answers with no explanation even though they are correct

• Call 0312-290-3193 in case of emergency or connection failure

 Bilkent University EEE313: Electronic Circuit Design Spring 2019-20, 01.06.2020
FINAL EXAM
Formula Page

BJT nMOS
• Forward active region, B-E forward, B-C reverse biased • Non-saturation (VDS<VGS-VTN)
𝑉𝐵𝐸 2
𝐼𝐶 = 𝐼𝑆 (𝑒 𝑉𝑇 − 1ቁ 𝐼𝐷 = 𝐾𝑁 2 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉𝐷𝑆 1 + 𝜆𝑉𝐷𝑆

• Saturation (VDS>VGS-VTN)
𝛼𝐼𝐸 = 𝐼𝐶 , 𝐼𝐶 = 𝛽𝐼𝐵 , 𝛼 = 𝛽Τ 𝛽 + 1
𝐼𝐷 = 𝐾𝑁 𝑉𝐺𝑆 − 𝑉𝑇𝑁 2 1 + 𝜆𝑉𝐷𝑆
𝑉𝑇 𝐼𝐶𝑄 𝑉𝐴
𝑟𝜋 = , 𝑔𝑚 = , 𝑟𝑜 = , 𝑉 = 26𝑚𝑉 𝑎𝑡 300𝐾
𝐼𝐵𝑄 𝑉𝑇 𝐼𝐶𝑄 𝑇 • for pMOS replace VGS with VSG, -VTN with VTP ,
and VDS with VSD
Diode
𝑔𝑚 = 2𝐾𝑁 𝑉𝐺𝑆𝑄 − 𝑉𝑡ℎ = 2 𝐾𝑁 𝐼𝐷𝑄 , 𝑟0 = 1ൗ𝜆𝐼
• VT=26mV at 300K 𝐷𝑄
𝑉𝐷
𝐼𝐷 = 𝐼𝑆 𝑒 𝑉𝑇 −1
 Bilkent University EEE313: Electronic Circuit Design Spring 2019-20, 01.06.2020
FINAL EXAM – Part 1, 60 minutes
1. (15 points) 2. (25 points) +VCC

VCC=2.5V
RC+ΔR RC-ΔR β=100
R 2R VBEon=0.7V
D1 - + VCEsat=0. 2V
Vout Vout VA=∞
Vin
Q1 Q2 VTN=1V
𝑣𝑑 −𝑣𝑑
2R R + 𝑣𝐶𝑀 + 𝑣𝐶𝑀 KN=1mA/V2
2 2
RC=2kΩ
ΔR=100Ω
λ=0.04 1/V
M1
Von=0.7V for D1
Plot Vout vs Vin for the above circuit.
Clearly label all the critical values -VCC
and slopes. Note that there is a mismatch between the collector resistances
a. Calculate the small signal parameters (Take vd=0, vCM=0 for
Hint: Start by assuming D1 is OFF this purpose), and find the range of vCM to keep the circuit
and finding the corresponding Vin functional.
range b. Find the small signal differential and common mode gain of
this circuit first symbolically and then numerically.
 Bilkent University EEE313: Electronic Circuit Design Spring 2019-20, 01.06.2020
FINAL EXAM – Part 2, 40 minutes
3. (25 points) VCC

VCC=5V
β=100
R1 RC
VA=∞
C2 VBEon=0.7V
Vout
VCEsat=0.2V
RS C1
Q1 R1=R2=200kΩ
RE=0.6kΩ
RC=2.5kΩ
Vin RS=5kΩ
R2 RE CE C1=1µF
C2=10pF
CE very large

a. Verify the state of Q1 at the Q-point and find the small signal parameters.
b. Calculate AV(j ω)=Vout(jω)/Vin(jω), and provide the basic bode plot.
Express AV(jω)=A0*H1(jω)*H2(jω)*… where A0 is the mid-band gain.
Hi(jω) should be in the form of (jf/fc)/(1+jf/fc), or 1/(1+jf/fc), or
multiplication of such factors. Indicate all the breaking point frequencies,
slopes and mid-band gain in the bode plot.
Hint: How many poles does C2 introduce?
 Bilkent University EEE313: Electronic Circuit Design Spring 2019-20, 01.06.2020
FINAL EXAM – Part 3, 40 minutes
4.a. (20 points) 4.b. (15 points)
VDD
VDD

R1 VDD=5V
RD R1=R2=20kΩ
VDD=5V
RD=4kΩ C R3=2kΩ
vout1 M1 KN=1mA/V2
VTN=1V
VB1=2V vout2 VTN=0.5V
VB2 M1 Rout vin2 λ=0
KN=0.5mA/V2 R2 R3
λ=0.04 1/V

VB1+vin1 M2

a. Calculate the small signal parameters and verify the

transistor state.
a. M1 and M2 are matched transistors. Find the DC biasing b. Find AV2=vout2/vin2
voltage VB2 such that M1 and M2 have the same VDS. c. Instead of vin2, vout1 is connected to the left side of C,
b. Find AV1=vout1/vin1 (Assume λ=0 in this part) calculate the overall gain Aoverall=vout2/vin1 using the already
c. Find Rout (Note that it is NOT simply RD). found AV1 and AV2.
Reminder: λ=0 only for part b.