1.

4bit counter

module up_down_counter(input clk, reset,up_down, output[3:0]counter);

reg [3:0] counter_up_down;

always @(posedge clk or posedge reset)

begin
if(reset)
counter_up_down <= 4'h0;
else if(~up_down)
counter_up_down <= counter_up_down + 4'd1;
else
counter_up_down <= counter_up_down - 4'd1;
end
assign counter = counter_up_down;
endmodule

-----------------------testbench------------------
module updowncounter_testbench();
reg clk, reset,up_down;
wire [3:0] counter;

up_down_counter dut(clk, reset,up_down, counter);

initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
#200;
up_down=1;
#300 $finish;
end
endmodule

//rc_script.tcl for sequential ckts

##Loading the Timing Library File path based on Technology choosen

##set_db / .init_lib_search_path {lib}
##set_db lib_search_path /home/install/FOUNDRY/digital/90nm/dig/lib
##set_db / .library "slow.lib"
read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib

##Loading the Physical Library file path based on Technology choosen(optional)

##set_db lef_library
{/home/install/FOUNDRY/digital/90nm/dig/LIBS/lef/gsclib090_tech.lef
/home/install/FOUNDRY/digital/90nm/dig/LIBS/lef/gsclib090_macro.lef}

##set_db / .init_hdl_search_path {rtl} ##From Current Directory

##Loading the HDL(Verilog/VHDL) file

read_hdl "counter.v"

##Elaborate the design

elaborate
##Setting the Top module
##set_top_module filename

##Check the design status

check_design -unresolved

set_dont_use *XL

##Loading the constraints file

read_sdc constraints.sdc

##Setting the effort level to synthesis

set_db syn_generic_effort medium
set_db syn_map_effort medium
set_db syn_opt_effort medium

##Performing the Synthesis

syn_generic
syn_map
syn_opt

write_hdl > counter_netlist.v

write_sdc > counter_sdc.sdc

##Generation of Outputs

report_timing > timing.rep

##Generation of Reports(Area,Power,Gates & Timing)

report_area > area.rpt
report_power > power.rpt
report_gates > gates.rpt
##Command to get timing report for Combinational Design
##report_timing > timing.rpt ##Command to get timing report for Sequential Design

##Getting Graphical User Interface

gui_show

2.32bit counter

module up_down_counter(input clk, reset,up_down, output[31:0]counter);

reg [31:0] counter_up_down;

always @(posedge clk or posedge reset)

begin
if(reset)
counter_up_down <= 32'h0;
else if(~up_down)
counter_up_down <= counter_up_down + 32'd1;
else
counter_up_down <= counter_up_down - 32'd1;
end
assign counter = counter_up_down;
endmodule

----------------------testbench-----------
module updowncounter_testbench();
reg clk, reset,up_down;
wire [31:0] counter;

up_down_counter dut(clk, reset,up_down, counter);

initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
#200;
up_down=1;
#300 $finish;
end
endmodule

3. D flipflop
module dff(d,clk,rst,q,qb);
input d,clk,rst;
output q,qb;
reg q;
always@(posedge clk)
begin
if(rst)
q<=1'b0;
else
q<=d;
end
assign qb=-q;
endmodule
-------------------------testbench--------------
module dff_tb();
reg d,clk,rst;
wire q,qb;
dff dff_tb(d,clk,rst,q,qb);
initial
begin
clk=0;
forever#5 clk=~clk;
end
initial
begin
#10 rst=0;
#10 rst=1;
#10 rst=0;
#10 rst=1;
end
initial
begin
d=0;
#15 d=1;
#15 d=0;
#15 d=1;
#30 d=0;
#300 $finish;
end
endmodule

4.JK flipflop

module jkff(j,k,clk,rst,q,qb);
input j,k,clk,rst;
output q,qb;
reg q;
wire j,k,clk,rst,qb;
always@(posedge clk)
begin
if(rst==1)
q<=1'b0;
else if(j==0 && k==0)
q<=q;
else if(j==0 && k==1)
q<=1'b0;
else if(j==1 && k==0)
q<=1'b1;
else if(j==1 && k==1)
q<=~q;
end
assign qb=~q;
endmodule

----------------testbench-------------
module jk_tb;
reg j,k,clk,rst=1;
wire q,qb;
jkff jkff_tb(.clk(clk),.rst(rst),.j(j),.k(k),.q(q),.qb(qb));

always #10 clk = ~clk;

initial
begin
clk=0;
rst=1;
j=0;
k=0;
#30
j <= 0;
k <= 0;
rst=0;

#30 j <= 0;
k <= 1;
#30 j <= 1;
k <= 0;
#30 j <= 1;
k <= 1;
#200 $finish;
end
endmodule
5.SR flipflop

module srff(s,r,clk,q,q1);
input s,r,clk;
output reg q,q1;
initial
begin
q=0;
q1=1;
end
always@ (posedge clk)
begin
case({s,r})
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bx;
endcase
q1=~q;
end
endmodule
--------------------------testbench-------------
module srff_tb();
reg s,r,clk;
wire q,q1;
srff srff_tb(.s(s),.r(r),.clk(clk),.q(q),.q1(q1));
initial
clk=0;
always
#10 clk=~clk;
initial
begin
s=0;r=0;
#100 s=0;r=0;
#100 s=1;r=0;
#100 s=1;r=1;
#100 s=0;r=1;
#300 $finish;
end
endmodule

6.Parallel adder

//full.v
module full(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
reg s,cout;
always @(a,b,cin)
begin
s=a^b^cin;
cout=(a&b)|(b&cin)|(a&cin);
end
endmodule

//para.v
module para(a,b,cin,s,cout);
input cin;
input[3:0] a,b;
output cout;
output[3:0] s;
wire c1,c2,c3;
full fa0(a[0],b[0],cin,s[0],c1);
full fa1(a[1],b[1],c1,s[1],c2);
full fa2(a[2],b[2],c2,s[2],c3);
full fa3(a[3],b[3],c3,s[3],cout);
endmodule

---------------testbench------------------
module pa_tb;
reg cin;
reg[3:0] a,b;
wire cout;
wire [3:0] s;
para pa0(a,b,cin,s,cout);
initial
begin
a=4'd0;b=4'd0;cin=1'b0;
#20 a=4'd1;b=4'd3;cin=1'b0;
#20 a=4'd6;b=4'd3;cin=1'b1;
#20 a=4'd1;b=4'd5;cin=1'b0;
#100 $finish;
end
endmodule

//make changes in rc_script.tcl for combinational ckt

##Loading the Timing Library File path based on Technology choosen

##set_db / .init_lib_search_path {lib}
##set_db lib_search_path /home/install/FOUNDRY/digital/90nm/dig/lib
##set_db / .library "slow.lib"
read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
##Loading the Physical Library file path based on Technology choosen(optional)
##set_db lef_library
{/home/install/FOUNDRY/digital/90nm/dig/LIBS/lef/gsclib090_tech.lef
/home/install/FOUNDRY/digital/90nm/dig/LIBS/lef/gsclib090_macro.lef}

##set_db / .init_hdl_search_path {rtl} ##From Current Directory

##Loading the HDL(Verilog/VHDL) file

read_hdl "full.v" "para.v"

##Elaborate the design

elaborate

##Setting the Top module

set_top_module para

##Check the design status

check_design -unresolved

set_dont_use *XL

##Loading the constraints file

##read_sdc constraints.sdc

##Setting the effort level to synthesis

set_db syn_generic_effort medium
set_db syn_map_effort medium
set_db syn_opt_effort medium

##Performing the Synthesis

syn_generic
syn_map
syn_opt

write_hdl > para_netlist.v

write_sdc > para_sdc.sdc

##Generation of Outputs

report_timing -unconstrained > timing.rep

##Generation of Reports(Area,Power,Gates & Timing)

report_area > area.rpt
report_power > power.rpt
report_gates > gates.rpt
##Command to get timing report for Combinational Design
##report_timing > timing.rpt ##Command to get timing report for Sequential Design

##Getting Graphical User Interface

gui_show

7. ALU
module alu(a,b,c,y);
input[31:0]a;
input[31:0]b;
input[2:0]c;
output reg[31:0]y;
always@(*)
begin
if (c==3'b000)
y=a&b;
else if (c==3'b001)
y=a/b;
else if (c==3'b010)
y=a^b;
else if (c==3'b011)
y=~(a&b);
else if (c==3'b100)
y=a+b;
else if (c==3'b101)
y=a-b;
else if (c==3'b110)
y=a*b;
else if (c==3'b111)
y=a%b;
else
y=32'bxxx;
end
endmodule

---------testbench--------------
module alu_tb();
reg [31:0]a;
reg [31:0]b;
reg [2:0]c;
wire [31:0]y;
alu alu_tb(a,b,c,y);
initial
begin
a=32'b00000000;
b=32'b01010101;
c=3'b000;
#10 c=3'b001;
#10 c=3'b010;
#10 c=3'b011;
#10 c=3'b100;
#10 c=3'b101;
#10 c=3'b110;
#10 c=3'b111;
#10 c=3'bxxx;
end
initial
begin
#100 $finish;
end
endmodule

//make changes in rcscript for combinational ckt

##Loading the Timing Library File path based on Technology choosen
##set_db / .init_lib_search_path {lib}
##set_db lib_search_path /home/install/FOUNDRY/digital/90nm/dig/lib
##set_db / .library "slow.lib"
read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib

##Loading the Physical Library file path based on Technology choosen(optional)

##set_db lef_library
{/home/install/FOUNDRY/digital/90nm/dig/LIBS/lef/gsclib090_tech.lef
/home/install/FOUNDRY/digital/90nm/dig/LIBS/lef/gsclib090_macro.lef}

##set_db / .init_hdl_search_path {rtl} ##From Current Directory

##Loading the HDL(Verilog/VHDL) file

read_hdl "alu.v"

##Elaborate the design

elaborate

##Setting the Top module

##set_top_module filename

##Check the design status

check_design -unresolved

set_dont_use *XL

##Loading the constraints file

##read_sdc constraints.sdc

##Setting the effort level to synthesis

set_db syn_generic_effort medium
set_db syn_map_effort medium
set_db syn_opt_effort medium

##Performing the Synthesis

syn_generic
syn_map
syn_opt

write_hdl > alu_netlist.v

write_sdc > alu_sdc.sdc

##Generation of Outputs

report_timing -unconstrained > timing.rep

##Generation of Reports(Area,Power,Gates & Timing)

report_area > area.rpt
report_power > power.rpt
report_gates > gates.rpt
##Command to get timing report for Combinational Design
##report_timing > timing.rpt ##Command to get timing report for Sequential Design

##Getting Graphical User Interface

gui_show