FUNDAMENTALS OF

DIGITAL CIRCUITS
FOURTH EDITION

A. Anand Kumar
Principal
K.L. University College of Engineering
K.L. University
Green Fields, Vaddeswaram
Guntur District
Andhra Pradesh

Delhi-110092
2016
xx CONTENTS

16.12.3 TTL to CMOS ................................................................................................ 900

16.12.4 CMOS to TTL ................................................................................................ 901
SHORT QUESTIONS AND ANSWERS ..................................................................................... 901
REVIEW QUESTIONS .............................................................................................................. 906
FILL IN THE BLANKS ............................................................................................................. 906
OBJECTIVE TYPE QUESTIONS .............................................................................................. 908

17 ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS... 910–942

17.1 INTRODUCTION ......................................................................................................... 910
17.2 DIGITAL-TO-ANALOG (D/A) CONVERSION ........................................................... 911
17.2.1 Parameters of DAC ........................................................................................ 912
17.2.2 DAC Using BCD Input Code ........................................................................ 914
17.2.3 Bipolar DACs ................................................................................................ 915
17.3 THE R-2R LADDER TYPE DAC ................................................................................ 915
17.4 THE WEIGHTED-RESISTOR TYPE DAC .................................................................. 920
17.5 THE SWITCHED CURRENT-SOURCE TYPE DAC .................................................. 923
17.6 THE SWITCHED-CAPACITOR TYPE DAC ............................................................... 924
17.7 ANALOG-TO-DIGITAL CONVERSION ..................................................................... 926
17.8 THE COUNTER-TYPE A/D CONVERTER ................................................................ 926
17.9 THE TRACKING-TYPE A/D CONVERTER ............................................................... 928
17.10 THE FLASH-TYPE A/D CONVERTER ...................................................................... 930
17.11 THE DUAL-SLOPE TYPE A/D CONVERTER ........................................................... 933
17.12 THE SUCCESSIVE-APPROXIMATION TYPE ADC .................................................. 934
17.12.1 A Specific A/D Converter .............................................................................. 935
17.12.2 Voltage-to-Frequency ADC .......................................................................... 936
SHORT QUESTIONS AND ANSWERS ..................................................................................... 937
REVIEW QUESTION ................................................................................................................ 940
FILL IN THE BLANKS ............................................................................................................. 940
OBJECTIVE TYPE QUESTIONS .............................................................................................. 941
PROBLEMS .............................................................................................................................. 941

18 MEMORIES ................................................................................................ 943–981

18.1 THE ROLE OF MEMORY IN A COMPUTER SYSTEM ............................................ 943
18.1.1 Program and Data Memory ............................................................................ 943
18.1.2 Main and Peripheral Memory ....................................................................... 944
18.2 MEMORY TYPES AND TERMINOLOGY ................................................................. 944
18.2.1 Memory Organization and Operation ........................................................... 944
18.2.2 Reading and Writing ..................................................................................... 946
18.2.3 RAMs, ROMs and PROMs ............................................................................ 947
18.2.4 Constituents of Memories ............................................................................. 947
18.2.5 Applications of ROMs .................................................................................. 948
930 FUNDAMENTALS OF DIGITAL CIRCUITS

EXAMPLE 17.14 Determine the maximum conversion time that an ADC can have, if it is
used to convert signals in the range of 1 kHz to 50 kHz.
Solution
Since the highest input frequency is 50 kHz, conversions should be performed at the rate of
2 ¥ 50 ¥ 103 = 100 ¥ 103 conversions/s. The maximum allowable conversion time is, therefore,
equal to 1/(100 ¥ 103) = 10 ms.
EXAMPLE 17.15 An ADC has a total conversion time of 200 ms. What is the highest
frequency that its analog input should be allowed to contain?
Solution
The highest frequency that the analog signal can contain is
1 1
= = 2.5 kHz
2 ¥ conversion time 2 ¥ 200 ms

17.10 THE FLASH-TYPE A/D CONVERTER

The flash (or simultaneous or parallel) type A/D converter is the fastest type of A/D converter.
This type of converter utilizes the parallel differential comparators that compare reference voltages
with the analog input voltage. The main advantage of this type of converter is that the conversion
time is less, but the disadvantage is that, an n-bit converter of this type requires 2n – 1 comparators,
2n resistors, and a priority encoder. Figure 17.19 shows a 3-bit flash type A/D converter which

Figure 17.19 The flash-type ADC.

 ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS 931

requires 7(= 23 – 1) comparators. A reference voltage EREF is connected to a voltage divider that
divides it into seven equal increment levels. Each level is compared to the analog input by a
voltage comparator. For any given analog input, one comparator and all those below it will have a
HIGH output. All comparator outputs are connected to a priority encoder, which produces a digital
output corresponding to the input having the highest priority, which in this case is the one that
represents the largest input. Thus, the digital output represents the voltage that is closest in value
to the analog input.
The voltage applied to the inverting terminal of the uppermost comparator in Figure 17.19 is
(by voltage divider action),
Ê 7R ˆ 7
ÁË 7R + R ˜¯ ¥ EREF = 8 ¥ EREF
Similarly, the voltage applied to the inverting terminal of the second comparator is
Ê 6R ˆ 6
ÁË 7R + R ˜¯ ¥ EREF = 8 ¥ EREF
1
and so forth. The increment between voltages is ¥ EREF.
8
The flash converter uses no clock signal, because there is no timing or sequencing period.
The conversion takes place continuously. The only delays in the conversion are in the comparators
and the priority encoders.
Figure 17.20 shows the block diagram of a modified flash A/D converter. To perform an 8-
bit conversion, it requires two 4-bit flash converters. So, an 8-bit conversion can be done by using
30[= 2 ¥ (24 – 1)] comparators instead of 255(= 28 – 1) comparators. One 4-bit flash converter is
used to produce the four most significant bits (MSBs). Those four bits are converted back to an
analog voltage by a D/A converter and this voltage is subtracted from the analog input. The
difference between the analog input and the analog voltage corresponding to the four most significant
bits, is an analog voltage corresponding to the four least significant bits (LSBs). Therefore, that
voltage is converted to the four least significant bits by another 4-bit flash converter.
4 MSBs
4-bit flash
ADC

4-bit
Latches 8-bit digital
DAC
output

4 LSBs
– 4-bit flash
Analog + Analog ADC
input subtractor
Figure 17.20 Modified flash ADC.

EXAMPLE 17.16 Determine the digital output of a 3-bit simultaneous A/D converter for
the analog input signal and the sampling pulses (encoder enable) shown in Figure 17.21.
VREF = + 8 V.
932 FUNDAMENTALS OF DIGITAL CIRCUITS

Figure 17.21 Example 17.16: Waveforms.

Solution
The resulting A/D output sequence is listed as follows and shown in Figure 17.22 in relation
to the sampling pulses.
000, 010, 101, 110, 110, 100, 010, 000, 000, 011, 101, 110.

Figure 17.22 Example 17.16: A/D output sequence.

 ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS 933

17.11 THE DUAL-SLOPE TYPE A/D CONVERTER

The dual-slope converter is one of the slowest converters, but is relatively inexpensive because it
does not require precision components such as a DAC or VCO. Another advantage of the dual-
slope ADC is its low sensitivity to noise, and to variations in its component values caused by
temperature changes. Because of its large conversion time, the dual-slope ADC is not used in any
data acquisition applications. The major applications of this type of converter are in digital
voltmeters, multimeters, etc. where slow conversions are not a problem. Since it is not fast enough,
its use is restricted to signals having low to medium frequencies.
A dual-slope ADC uses an operational amplifier to integrate the analog input. The output of
the integrator is a ramp, whose slope is proportional to the input signal Ein, since the components
R and C are fixed. If the ramp is allowed to continue for a fixed time, the voltage it reaches in that
time, depends on the slope of the ramp and, therefore, on the value of Ein. The basic principle of
the integrating ADC is that, the voltage reached by the ramp controls the length of time that the
binary counter is allowed to count. Thus, a binary number proportional to the value of Ein is
obtained. In the dual-slope ADC, two integrations are performed.
Figure 17.23 shows the functional block diagram of a dual-slope ADC. Assume that the
counter is reset and the output of the integrator is zero. A conversion begins with the switch
connected to the analog input. Assume that the input is a negative voltage and is constant for a
period of time; so, the output of the integrator is a positive ramp. The ramp is allowed to continue
for a fixed time and the voltage it reaches in that time is directly dependent on the analog input.
The fixed time is controlled by sensing the time when the counter reaches a particular count. At
that time, the counter is reset and the control circuitry causes the switch to be connected to a
reference voltage EREF, having a polarity opposite to that of the analog input; in this case a positive
reference voltage. Therefore, the output of the integrator is a negative going ramp, beginning from
the positive value it reached during the first integration. The AND gate is enabled and the counter
starts counting. When the ramp reaches 0 V, the voltage comparator switches to LOW, inhibiting
the clock pulses and the counter stops counting. The binary count is latched, thus, completing one
conversion. The count it contains at that time is proportional to the time required for the negative
ramp to reach zero, which is proportional to the positive voltage reached during the first integration,
which in turn is proportional to the analog input.
The accuracy of the converter does not depend on the values of the integrator components or
upon any changes in them. The accuracy does depend on EREF; so, the reference voltage should be
very precise.

Figure 17.23 The dual-slope ADC.

934 FUNDAMENTALS OF DIGITAL CIRCUITS

17.12 THE SUCCESSIVE-APPROXIMATION TYPE ADC

The successive-approximation (SA) converter is one of the most widely used types of ADCs. It
has a much shorter conversion time than the other types, with the exception of the flash type.
It also has a fixed conversion time which is not dependent on the value of the analog input.
Figure 17.24 shows a basic block diagram of a 4-bit successive-approximation type ADC. It
consists of a DAC, an output register, a comparator, and control circuitry or logic. The basic operation
is as follows: The bits of the DAC are enabled one at a time, starting with the MSB. As each bit is
enabled, the comparator produces an output that indicates whether the analog input voltage is greater
or less than the output of the DAC VAX. If the D/A output is greater than the analog input, the
comparator output is LOW, causing the bit in the control register to reset. If the D/A output is greater
than the analog input, the comparator output is HIGH, and the bit is retained in the control register.
VA
Analog + CLK
Control
input logic START
–
EOC
Comparator
...

Output
register
MSB LSB
... Binary output

DAC

VAX

Figure 17.24 The successive-approximation type ADC.

The system enables the MSB first, then the next significant bit, and so on. After all the bits of
the DAC have been tried, the conversion cycle is complete. The processing of each bit takes one
clock cycle; so, the total conversion time for an N-bit SA-type ADC will be N clock cycles. That is,
tc for SAC = (N ¥ 1) clock cycles
The conversion time will be the same regardless of the value of VA. This is because the
control logic has to process each bit to see whether a 1 is needed or not.
The method is best explained by an example. Let us assume that the output of the DAC
ranges from 0 V to 15 V as its binary input ranges from 0000 to 1111, with 0000 producing 0 V,
and 0001 producing 1 V, and so on. Suppose that the unknown analog input voltage VA is 10.3 V.
On the first clock pulse, the output register is loaded with 1000, which is converted by the DAC to
8 V. The voltage comparator determines that 8 V is less than the analog input (10.3 V); so, the
control logic retains that bit. On the next clock pulse, the control circuitry causes the output register
to be loaded with 1100. The output of the DAC is now 12 V, which the comparator determines as
greater than the analog input. Therefore, the comparator output goes LOW. The control logic
clears that bit; so, the output goes back to 1000. On the next clock pulse, the control circuitry
causes the output register to be loaded with 1010. The output of the DAC is now 10 V, which the
comparator determines as less than the analog input. Thus, on the next clock pulse, the control
 ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS 935

logic causes the output register to be loaded with 1011. The output of the DAC is now 11 V, which
the comparator determines as greater than the analog input; so, the control logic clears that bit.
Now the output of the ADC is 1010 which is the nearest integer value to the input (10.3 V).
At this point, all of the register bits have been processed, the conversion is complete and the
control logic activates its EOC output to signal that the digital equivalent of VA is now in the
output register.
EXAMPLE 17.17 Compare the maximum conversion periods of an 8-bit digital ramp
ADC and an 8-bit successive approximation ADC if both utilize a 1 MHz clock frequency.
Solution
For the digital-ramp converter, the maximum conversion time is
(2N – 1) ¥ (1 clock cycle) = 255 ¥ 1 ms = 255 ms
For an 8-bit successive-approximation converter, the conversion time is always 8 clock
periods, i.e. 8 ¥ 1 ms = 8 ms.
Thus, the successive-approximation conversion is about 30 times faster than the digital-
ramp conversion.
EXAMPLE 17.18 An 8-bit SAC has a resolution of 30 mV. What will its digital output be
for an analog input of 2.86 V?
Solution
Since, 2.86 V/30 mV = 95.3, the step 95 would produce 2.85 V and step 96 would produce
2.88 V. The SAC always produces a final output, that is, at the step below the analog input.
Therefore, for the case of VA = 2.86 V, the digital result would be 9510 = 010111112.

17.12.1 A Specific A/D Converter

The ADC 0801 is an example of a successive-approximation type analog-to-digital converter. The
pin diagram is shown in Figure 17.25. This device operates from a + 5 V supply, and has a resolution
of 8 bits with a conversion time of 100 ms. Also, it has guaranteed monotonicity and an on-chip
clock generator. The data outputs are tri-stated so that it can be interfaced with a microprocessor
bus system. The two analog inputs are VIN+ and VIN–.
CS (Chip Select): This input has to be in active-LOW state, for RD and WR inputs to have any
effect. With CS HIGH, the digital outputs are in the Hi-Z state and no conversion takes place.
RD (Output Enable): This input is used to enable the digital output buffers. With CS = RD
= LOW, the digital output pins have logic levels representing the results of the last A/D conversion.
WR (Start Conversion): A LOW pulse is applied to this input to signal the start of a new
conversion.
INTR (End of Conversion): This output signal will go HIGH at the start of a conversion and
return LOW to indicate the end of the conversion.
Vref /2: This is an optional input that can be used to reduce the internal reference voltage and
thereby change the analog input range that the converter can handle.
CLK OUT: A resistor is connected to this pin to use the internal clock. The clock signal appears
on this pin.
936 FUNDAMENTALS OF DIGITAL CIRCUITS

CLK IN: It is used for the external clock input, or for the capacitor connection when the internal
clock is used.

Figure 17.25 Pin configuration of the ADC 0801.

17.12.2 Voltage-to-Frequency ADC

The voltage-to-frequency ADC is simpler than other ADCs, because it does not use a DAC. Instead,
it uses a linear voltage controlled oscillator (VCO) that produces an output frequency proportional
to its input voltage. The analog voltage is applied to the VCO to generate an output frequency.
This frequency is fed to a counter, to be counted for a fixed time interval. The final count is
proportional to the value of the analog input.
To illustrate this, suppose the VCO generates a frequency of 5 kHz for each volt of input
(i.e.1 V produces 5 kHz, 1.5 V produces 7.5 kHz, 2.6 V produces 13 kHz). If the analog input is
4.65 V, then the VCO output will be a 23.25 kHz signal that clocks a counter for, say, 10 ms. After
the 10 ms counting interval, the counter will hold the count of 232.
Although this is a simple method of conversion, it is difficult to achieve a high degree of
accuracy because of the difficulty in designing VCOs with accuracies better than 0.1per cent.
One of the main applications of this type of converter is in noisy industrial environments,
where small analog signals have to be transmitted from transducer circuits to a control computer.
The small analog signals can get drastically affected by noise, if they are transmitted directly to the
control computer. A better approach is to feed the analog signal to a VCO, which generates a
digital signal whose output frequency changes according to the analog input. The digital signal is
transmitted to the computer and will be much less affected by noise. Circuitry in the control computer
will count the digital pulses to produce a digital value, equivalent to the original analog input.