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7 Labrephometasks

The document is a lab report submitted by students to their professor describing their exploration of Verilog for gate-level and behavioral-level modeling using the Vivado software. The report details the objectives of developing proficiency in Verilog modeling within Vivado, implementing circuits using basic logic gates and flip-flops, and modifying clock signals through Verilog modules. The procedures covered include creating a new Vivado project, adding Verilog modules, defining inputs/outputs, implementing gate-level logic, simulating designs, and synthesizing designs. Specific circuits modeled at the gate-level include a full adder, 4x1 MUX, 3x8 decoder, and SR latch. Behavioral modeling includes a module to change a clock

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Umar Ayub
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16 views17 pages

7 Labrephometasks

The document is a lab report submitted by students to their professor describing their exploration of Verilog for gate-level and behavioral-level modeling using the Vivado software. The report details the objectives of developing proficiency in Verilog modeling within Vivado, implementing circuits using basic logic gates and flip-flops, and modifying clock signals through Verilog modules. The procedures covered include creating a new Vivado project, adding Verilog modules, defining inputs/outputs, implementing gate-level logic, simulating designs, and synthesizing designs. Specific circuits modeled at the gate-level include a full adder, 4x1 MUX, 3x8 decoder, and SR latch. Behavioral modeling includes a module to change a clock

Uploaded by

Umar Ayub
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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INSTITUTE OF SPACE TECHNOLOGY

ISLAMABAD

VLSI
Electrical Engineering Department
Lab Report No.7
(Gate level modeling)

Submitted To:
Sir Asad Ur Rehman
Submitted By:
Zain Rizwan (200401011)
Muhamad Bilawal (200401016)
Amna Ahmed (200401031)
Zujaja Ibrahim (200401053)
Jawad Ali Abbasi (200401056)
Shaheer Arshad (200401014)
Muhammad Idrees (200401065)
EE-19 Section A
Objectives:
1. Develop proficiency in gate-level modeling using Verilog within the Vivado software
environment.
2. Implement circuits using basic logic gates and flip-flops, emphasizing low-level details crucial
for FPGA implementation
3. Explore behavioral-level modeling to conceptualize and simulate digital systems at a higher
level of abstraction.
4. Developing proficiency in modifying clock signals by creating Verilog modules
5. Understanding and applying gate-level modeling techniques to derive the Boolean function
6.
Software Used:
• Xilinx Vivado

Introduction:
In the realm of digital design, Verilog is a powerful tool for simulating electronic systems. This
lab report encapsulates our exploration of Verilog for both gate-level and behavioral-level
modeling using Vivado software. Developed by Xilinx, Vivado is a helpful tool for designing and
simulating digital circuits, especially for FPGAs (Field-Programmable Gate Arrays). The goal of
this hands-on experience is to help us understand Verilog better and how it's used to represent
digital circuits at different levels – from low-level gates to higher-level behavior. The report aims
to improve our skills in using Verilog with Vivado, setting the stage for successful FPGA design.

Procedure:
1. Launch Vivado:
• Open Vivado software on your computer.
2. Create a New Project:
• Click on "Create Project" in the Vivado dashboard.
• Follow the wizard to set up the project, providing details such as project
name, location, and target FPGA device.
3. Add a Verilog Module:
• In the project manager, select "Create Block Design."
• Add a new Verilog module to the design.
4. Define Inputs and Outputs:
• Specify the inputs and outputs for the Verilog module.
• Define any necessary parameters or constants.
5. Implement Gate-Level Logic:
• Open the Verilog module and use Verilog HDL to describe the gate-level
logic.
• Utilize Verilog constructs such as AND, OR, NOT gates to represent the
desired functionality.
6. Simulate the Design:
• Create a simulation testbench to verify the functionality of the gate-level
design.
• Simulate the design using Vivado's simulation tools.
7. Synthesize the Design:
• Return to the project manager and select "Run Synthesis."
• Review the synthesis report to ensure there are no errors and that the logic
is correctly implemented.
TASK 1: Obtain function F=[a+b+ac+bd]` using gate level modeling.
Schematic

Source code
Testbench code

Simulation
2. Implement following designs using gate level modelling.

Full Adder
Schematic:

Souce code
Test bench

Simulation
4x1 MUX:
Schematic

Source code
Testbench

Simulation
3x8 Decoder:
schematic

Source code:
Testbench

Simulation
SR Latch

Schematic

Source code
Testbench

Simulation
3. Design a Verilog module such that it takes an input clock signal and
generates an output by changing the phase of that clock by π.
Schematic

Source code
Testbench

Simulation
4. Draw a circuit and write Verilog code that tests if an 8-bit value is zero using
only one line of code (besides module/endmodule/initial/always statements)
Schematic

Source code
Testbench

Simulation

Conclusion: learning gate-level and behavioral-level modeling using Vivado enhances our
proficiency in digital design, providing a solid foundation for effective FPGA implementation. The
practical insights gained contribute to a deeper understanding of Verilog's applications in simulating
and designing electronic systems.

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