VLSI LAB

LAB NO:08
DATE OF PERFOMANCE:
09-DEC-2023
SECTION:
EE 19 A
SUBMITTED TO:
SIR ASAD
SUBMITTED BY:
IMAN FATIMA (200401047)
JAWERIA ARSHAD (200401063)
MUHAMMAD UMER AYYUB (200401063)
OBJECTIVE:
In lab we will focus on following main points:
1) Learn the fundamental principles of digital circuit design,
including the architecture and operation of Arithmetic and Logic
Units (ALUs).
2) Gain insights into modular design by implementing a 4-bit
adder using 1-bit Full Adders and explore the importance of
scalability in digital systems.
3) Explore concise coding practices using the ternary
operator (? :) to handle reset and conditional jumps based on
flags.
Software:
For this lab we used following software and board
1.Vivado
2. zed board
INTRODUCTION:
In this VLSI lab, the primary objective is to delve into the design and
implementation of various digital circuits using Data Flow modeling. In the realm
of digital systems design, the ability to model and implement circuits efficiently
is a cornerstone of success. This Lab 8 focuses on Data Flow Modeling, a
powerful paradigm in digital design, aiming to deepen understanding and
proficiency in creating complex digital circuits. Through a series of tasks,
participants will delve into the design of crucial components, from Arithmetic
and Logic Units (ALUs) to various specialized modules. Now I will explain all
the tasks briefly;
Lab Tasks:
1. ALU Design (8 Functions):
• The primary task involves designing an Arithmetic and Logic Unit
(ALU) capable of executing eight distinct functions. This not only
emphasizes the importance of computational efficiency but also
challenges participants to create a versatile unit suitable for diverse
applications.
2. 4-Bit Adder Implementation:
• In this task we will instantiate four 1-bit Full Adders using Data
Flow modeling to construct a 4-bit adder. This task underscores the
 significance of modular design principles and the application of
fundamental building blocks in digital circuits.
3. Data Flow Modeling Designs:
• The lab extends its focus beyond addition with the implementation
of various designs using Data Flow modeling:
• 2x2 Multiplier: Efficient multiplication operations
leveraging Data Flow modeling.
• 8x1 MUX (Tertiary Operator): A versatile multiplexer
design capable of selecting one output from eight inputs.
• BCD to 7-Segment Decoder: Converting Binary Coded
Decimal to a format suitable for 7-segment display output.
• 4-Bit Binary to Gray Converter: Conversion of binary
numbers to Gray code, a critical operation in digital
communication systems.
4. Microprocessor Program Flow Management:
• The lab concludes with a practical application: designing an
assembler to manage the program flow of a microprocessor.
Emphasis is placed on handling the Program Counter (PC)
efficiently. The code's challenge lies in encapsulating the
functionality within a single line using the ternary operator (?:).
Specific conditions are defined for PC adjustments based on a reset
flag or a branch flag, adding a layer of complexity that mirrors real-
world microprocessor operations.
Procedure:
1. Open Vivado using the desktop shortcut.
2. Initiate the project creation process by clicking on "Create Project" in the
Quick Start panel, leading to the New Project dialog.
3. Provide a descriptive name for your project, avoiding the use of spaces.
4. Specify the project type to configure the design tools and customize the
appearance of the Integrated Development Environment (IDE).
5. Choose the appropriate board that aligns with the requirements of your
project. I choosed Zedboard but we can change it.
6. Verify the project configuration details on the last page of the wizard,
ensuring the correct selection of the FPGA part. Click "Finish" to create
the project without any specific content.
7. Access the main IDE window, where you can perform Verilog code entry,
simulation, synthesis, and board programming.
8. Here each tasks have following data
• .v file / workbech
• Test bench file
• Logic diagram (if needed)
• Output
• Device design
• schematic
Lab Task no 1:
Design an Arithmetic and Logic Unit (ALU) that implements 8
functions.
Solution:
Work bench:
Test bench:

At control = 000: (summation operation)

At control =001(subtraction operation)

 At control =010: (or operation)

at control = 011: (and operation)

at control = 100 concatenation operation:

at control = 101: concatenation operator:

at control = 110 (shift left operation)

at control = 111 (shift right operation)

Synthesis design:

Schematic design:
Lab Task no 2:
Implement 4-bit Adder by instantiating four 1-bit Full Adder
designed in data flow modelling.
Logic diagram:
Design of one bit adder:

.v file of adder_four_bit:
Test bench code:

Output:
Device design:

Schematic design:

Lab Task no 3:
Implement following designs using Data Flow modelling.
• 2x2 Multiplier
. v file :

Test bench:
Output:

Device design:

Schematic:
 • 8x1 MUX (Tertiary Operator)
Logic diagram:

.v file for mux:

Test bench:
`timescale 1ns / 1ps
module mux_8to1_tb;
reg [7:0] D;// we can change value of d on each step but i kept it constant later to identify
result easily
reg a, b, c;
wire out;
// Instantiate the mux_8to1 module
mux_8to1 uut
(.out(out),.D0(D[0]),.D1(D[1]),.D2(D[2]),.D3(D[3]),.D4(D[4]),.D5(D[5]),.D6(D[6]),.D7(D[7
]),.a(a),.b(b),.c(c));
// Testbench stimulus
initial begin
//here i set select lines so that i can selet all inputs from D0 to D7 after delay of 10 sec
// Test case 1: a=0, b=0, c=0 (Selects D0)
a = 0; b = 0; c = 0;
D = 8'b11011010;
#10;

// Test case 1: a=0, b=0, c=0 (Selects D1)

a = 0; b = 0; c = 1;
D = 8'b11011010;
#10;
// Test case 1: a=0, b=0, c=0 (Selects D2)
a = 0; b = 1; c = 0;
D = 8'b11011010;
#10;
// Test case 1: a=0, b=0, c=0 (Selects D3)
a = 0; b = 1; c = 1;
D = 8'b11011010;
#10;
// Test case 1: a=0, b=0, c=0 (Selects D4)
a = 1; b = 0; c = 0;
D = 8'b11011010;
#10;
// Test case 1: a=0, b=0, c=0 (Selects D5)
a = 1; b = 0; c = 1;
 D = 8'b11011010;
#10;
// Test case 1: a=0, b=0, c=0 (Selects D6)
a = 1; b = 1; c = 0;
D = 8'b11011010;
#10;
// Test case 1: a=0, b=0, c=0 (Selects D0)
a = 1; b = 1; c = 1;
D = 8'b11011010;
#10;
$finish;
end
endmodule
Device design:
Schematic design:

• BCD to 7-Segment Decoder

I used following table to make BCD to & segment Decoder
Picture of simple 7 segment Decoder:
.v file:

Test bench:
Output:

Device design:

Schematic:
• 4 bit binary to gray converter:

Table:

Logic diagram:
.v file:

Test bench:
Output:

Device design:

Schematic:
 Lab Task no 4:
Design code for an assembler to manage program flow of a
microprocessor i.e. handle Program counter PC. Try to code the
functionality in one line using ?: operators.PC is 16-bit. OFFSET is 8-
bit but in 2’s complement. If reset flag is high, jump PC to 0000. If
branch flag is high, jump PC to PC + OFFSET.

Explanation of task:
1. Assembler Module (Assembler.v):
• Initially, I designed an Assembler module to manage program flow
in a microprocessor.
• This module takes inputs such as reset_flag, branch_flag, PC, and
OFFSET.
• It provides the next Program Counter value as output (next_PC)
based on the conditions of the reset and branch flags.
• The ternary operator ?: is employed to decide the next PC value:
• If reset_flag is high, next_PC is set to 16'h0000.
• If branch_flag is high, the offset is added to the current PC.
• If neither reset nor branch flags are high, the PC is
incremented by 1.
• All these three tasks I have displayed in output.
2. Testbench Module (Testbench_Assembler.v):
• To verify the functionality of the Assembler module, I created a
testbench module.
• The testbench includes signals (reset_flag_tb, branch_flag_tb,
PC_tb, OFFSET_tb) to simulate different scenarios.
• The Assembler module (uut) is instantiated in the testbench with
proper connections to the testbench signals.
• Test cases are designed to observe the behavior of the Assembler
module under various conditions:
• In the first test case, I set reset_flag_tb and observed the
effect on next_PC_tb.
• In the second test case, I set branch_flag_tb and observed the
effect on next_PC_tb.
 • In the third test case, I observed the effect of incrementing
PC_tb.
• I used #10; to advance simulation time for each test case, and the
testbench finishes ($finish;) after executing the specified test cases.

. v file :

Test bench:
Output:

Device design:
Schematic:

CONCLUSION:

The lab has provided us valuable hands-on experience in

designing digital circuits using Data Flow modelling. we have
successfully achieved the objectives of implementing an 8-
function ALU, a modular 4-bit adder, and various complex
designs like a 2x2 multiplier, 8x1 MUX, BCD to 7-Segment
Decoder, and a 4-bit binary to grey converter. The culmination of
the lab involves the development of an assembler, showcasing the
practical application of these digital circuits in managing the
program flow of a microprocessor. Through these tasks, we have
honed our skills in VLSI design, gaining insights into efficient
coding practices and circuit optimization techniques.

****THE END****