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Chapter 14

The document discusses the process of logic synthesis, which involves converting a high-level design description into an optimized gate-level representation given a standard cell library and design constraints. The logic synthesis process includes translation to an unoptimized intermediate representation, logic optimization, technology mapping and optimization to the target library, with the goal of producing an optimized gate-level netlist that meets timing, area, and power constraints.

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Christina josephine malathi
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42 views23 pages

Chapter 14

The document discusses the process of logic synthesis, which involves converting a high-level design description into an optimized gate-level representation given a standard cell library and design constraints. The logic synthesis process includes translation to an unoptimized intermediate representation, logic optimization, technology mapping and optimization to the target library, with the goal of producing an optimized gate-level netlist that meets timing, area, and power constraints.

Uploaded by

Christina josephine malathi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter-14

Samir Palnitkar
Logic Synthesis
► The process of converting a high-level
description of the design into an optimized
gate-level representation, given a standard
cell library and certain design constraints.

Dr. Behnam Arad 2


EEE/CSC-273
Basic computer-aided logic synthesis process
Architectureal Description

High-level Description

Place and Route


Computer-Aided Logic Synthesis

Standard Cell
Optimized Gate-level Library
Netlist
(technology
Dependent)

Meets Constraints
no

yes
Place and Route
Dr. Behnam Arad 3
EEE/CSC-273
Limitations without Logic synthesis
► For large designs, manual conversion was prone to
human errors. A small gate missed somewhere
could mean redesign of entire blocks
► The designer could never be sure that the design
constraints were going to be met until the gate-
level implementation was completed and tested
► If the gate-level design did not meet
requirements, the turnaround time for redesign of
blocks was very high.
► Each designer would implement the blocks
differently. There was little consistancy in design
styles.
Dr. Behnam Arad 4
EEE/CSC-273
Limitations (continue…)
► Timing, area and power dissipation in library
cells are fabrication-technology specific.
Thus if IC fabrication vendor changed after
the gate-level design was complete, this
would mean redesign of entire circuit and a
possible change in design methodology.
► Design reuse was not possible. Designs
were technology specific, hard to port and
very difficult to reuse.

Dr. Behnam Arad 5


EEE/CSC-273
Logic synthesis flow from RTL to gates
RTL Description

Translation

Unoptimized Intermediate
Representation

Logic Optimization

Library of
available gates
Design Technology Mapping
(technology
Constraints and Optimization
library)

Optimized gate-level
representation

Dr. Behnam Arad 6


EEE/CSC-273
Verilog HDL constructs for logic synthesis
Construct type Keyword or description Notes

ports input, inout, output

parameters parameter

module definition module

signals and variables wire, reg, tri Vectors are allowed

instantiation Module instances, primitive E.g., mymux m1(out,i0,i1,s);


gate instances e.g., nand (out,a,b);
functions and tasks function, task Timing constructs ignored

Dr. Behnam Arad 7


EEE/CSC-273
Verilog HDL constructs for logic synthesis
(continue…..)
Construct type Keyword or description Notes

procedural always, if, then, else, case, initial is not supported


casex, casez
procedural blocks begin, end, named blocks, Disabling of named blocks
disable allowed
data flow assign Delay information is ignored

loops for, while, forever While and forever loops


must contain @(posedge
clk) or @(negedge clk)

Dr. Behnam Arad 8


EEE/CSC-273
RTL Description
► The designer describes the design at a high
level by using RTL constructs.
► The designer spends time in functional
verification to ensure that the RTL
description functions correctly.
► After the functionality is verified, the RTL
description is input to the logic synthesis
tool.
Dr. Behnam Arad 9
EEE/CSC-273
Translation
► The RTL description is converted by the
logic synthesis tool to an unoptimized,
intermediate, internal representation.
► Design constraints such as area, timing and
power are not considered in the translation
process.

Dr. Behnam Arad 10


EEE/CSC-273
Unoptimized intermediate representation

► The translation process yields an


unoptimized intermediate representation of
the design.
► The design is represented internally by the
logic synthesis tool in terms of internal data
structures.

Dr. Behnam Arad 11


EEE/CSC-273
Logic optimization
► The logic is now optimized to remove
redundant logic. Various technology
independent Boolean logic optimization
techniques are used.
► It is a very important step in logic synthesis,
and it yields an optimized internal
representation of the design.

Dr. Behnam Arad 12


EEE/CSC-273
Technology mapping and optimization

► Until this step, the design description is


independent of a specific target technology.
► In this step the synthesis tool takes the
internal representation and implements the
representation in gates, using the cells
provided in the technology library.
► The design is mapped to the desired target
technology.
Dr. Behnam Arad 13
EEE/CSC-273
Technology library
► The technology library contains library cells.
► Physical layout of library cells is done first. Then
the area of each cell is computed from the cell
layout. Then the area of each cell is computed
from the cell layout. This process is called cell
characterization.
► The cell description contains information about the
following:
ƒ Functionality of the cell
ƒ Area of the cell layout
ƒ Timing information about the cell
ƒ Power information about the cell
Dr. Behnam Arad 14
EEE/CSC-273
Design constraints
► Timing Æ The circuit must meet certain timing
requirements. An internal static timing analyzer
checks timing.
► Area Æ The area of the final layout must not
exceed a limit.
► Power Æ The power dissipation in the circuit
must not exceed a threshold.
area

timing
Dr. Behnam Arad 15
EEE/CSC-273
Optimized gate-level description
► After the technology mapping is complete,
an optimized gate-level netlist described in
terms of target technology components is
produced.
► If this netlist meets the required constraints,
it is handed out for final layout. Otherwise
the designer modifies the RTL or
reconstrains the design to achieve the
desired results.
Dr. Behnam Arad 16
EEE/CSC-273
Modeling tips for logic synthesis
► Use meaningful names for signals and
variables
► Avoid mixing positive and negative edge-
triggered flip-flops
► Use basic building blocks instead of
continuous assign statements
ƒ The final structure is not always symmetrical.
ƒ Basic building blocks creates symmetric designs.
Dr. Behnam Arad 17
EEE/CSC-273
Modeling tips (Continue..)
► Instantiatemultiplexers instead if-else or
case statements
► Use parentheses to optimize logic structure
ƒ Out = a + b + c + d; //3 adders in series
ƒ Out = (a + b) + (c + d);
//2 adders in series and one final adder to sum results
► Use arithmetic operators *, /, and %
instead design building blocks
Dr. Behnam Arad 18
EEE/CSC-273
Modeling tips (continue..)
► Be careful with multiple assignments to the same
variable
► Define if-else or case statements explicitly
ƒ if(control)
out <= a; //latch is inferred, incomplete specification
ƒ if(control)
out <= a;
else
out <= b; //complete specification for all values of control

Dr. Behnam Arad 19


EEE/CSC-273
Design Partitioning
► Horizontal Partitioning
ƒ Use bit slices to give the logic synthesis tool a
smaller block to optimize. This is called
horizontal partitioning.
ƒ It reduces complexity of the problem and
produces more optimal results for each block.
ƒ e.g. Instead of directly designing a 16-bit ALU,
design a 4-bit ALU and build the 16-bit ALU with
four 4-bit ALUs.
►Thus the logic synthesis tool has to optimize only the
4-bit ALU, which is a smaller problem than optimizing
the 16-bit ALU.
Dr. Behnam Arad 20
EEE/CSC-273
Design Partitioning (continue..)
► Vertical Partitioning
ƒ Vertical partitioning implies that the
functionality of a block is divided into smaller
submodules.
ƒ Different from horizontal partitioning
►In horizontal partitioning all blocks do the same
function
►In vertical partitioning all blocks do different function
ƒ e.g. Divide the ALU module in add, subtract,
shift right, ,and shift left blocks.
Dr. Behnam Arad 21
EEE/CSC-273
Parallelizing design structure
► In this technique we use more resources to
produce faster designs.
► We convert sequential operations into
parallel operations by using more logic.
ƒ E.g. Carry look ahead adder….

Dr. Behnam Arad 22


EEE/CSC-273
Dr. Behnam Arad 23
EEE/CSC-273

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