TABLE OF CONTENTS

EX. LIST OF PAGE

NO. EXPERIMENTS NO.

1. Verification of Boolean theorems using digital logic gates

Design and implementation of combinational circuits using basic gates
2. for arbitrary functions.

3. Implementation of 4-bit binary adder / subtractor circuits

4. Implementation of code converters

Implementation of BCD adder, encoder and decoder circuits
5.
Implementation of functions using Multiplexers
6.

7. Implementation of Synchronous counters.

8. Implementation of Universal Shift Register

Simulator based study of Computer Architecture
9.
ADDITIONAL EXPERIMENT

10. Simulation of combinational circuits using VERILOG HDL

 STUDY OF LOGIC GATES

AIM:

To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. 2- I/P AND gate IC 7408 1
2. 3-I/P AND gate IC7411 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. 2- I/P NAND gate IC7400 1
6. 3-I/P NAND gate IC7410 1
7. NOR gate IC7402 1
8. EX-OR gate IC7486 1
9. IC Trainer Kit - 1
10. Patch cords - Few

THOERY:

Logic gates are the basic elements that make up a digital system. The gate is a digital
circuit with one or more inputs, but only one output. By connecting the different gates in
different ways, we can build circuits that perform arithmetic and other functions.
The operation of a logic gate can be easily understood with the help of “truth table”.
A truth table is a table that shows all the input-output possibilities of a logic circuit ie., the
truth table indicates the outputs for different possibilities of the inputs.
The types of gates available are the AND, OR, NOT, NAND, NOR, exclusive-OR
and the exclusive-NOR. Except for the exclusive-NOR gate they are available in monolithic
integrated form.

AND gate:
The AND gates has two or more inputs. It performs a logical multiplication. The
output is HIGH (1), when both the inputs are 1; otherwise the output from the gate is LOW
(0). The output from the AND gate is written as A.B.

4
OR gate:

NOT gate:

5
AND gate:

3- Input AND gate:

6
OR gate:
The OR gates has two or more inputs. It performs a logical addition. The output is
HIGH (1), if any of the inputs are 1; the output is LOW (0) if and only if all the inputs are 0.
The output from the AND gate is written as A+B.

NOT gate:
The NOT gate has only one input. It performs a basic logic function called inversion.
The output is HIGH (1), when the input is 0; the output is LOW (0) when the input is 1. The
output from the NOT gate is written as A’.

NAND gate:
The NAND gate is a contraction of AND-NOT. It has two or more inputs. The output
is HIGH (1), when any of the inputs are 0; the output is LOW (0), if and only if all the inputs
are 1. The output from the AND gate is written as (A.B)’. It is a universal gate.

NOR gate:
The NOR gate is a contraction of OR-NOT. It has two or more inputs. The output is
HIGH (1), when all inputs are 0; the output is LOW (0), when any of the inputs are 1. The
output from the AND gate is written as (A+B)’. It is a universal gate.

EX-OR gate:
The EX-OR gate has two or more inputs. The output is HIGH (1), when odd number
of inputs is 1. The output from the AND gate is written as (AB).

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth table.

7
2- Input NAND gate:

3- Input NAND gate:

8
NOR gate:

EX-OR gate:

RESULT:
Thus the logic gates are studied and their truth tables are verified.

9
EX.NO: 1 VERIFICATION OF BOOLEAN THEOREMS USING LOGIC GATES

AIM:
To verify the Boolean theorems using logic gates.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. AND GATE IC 7486 1
2. IC 7404 1
OR GATE
3. IC 7432 1
4. NOT GATE IC7408 1
5. IC TRAINER KIT - 1
6. CONNECTING WIRES Few

THEORY:
Boolean algebra is used to simplify and rearrange Boolean equations to make
simple logic circuit. There are three basic laws of Boolean algebra. They are commutative
law, distributive law and associative law.

COMMUTATIVE LAW:
1. A+B = B+A

This law states that order in which variable makes no changes in output. The truth
table are identical. Therefore A OR B is same as B OR A

2. A.B=B.A
This law states that order in which variable and AND makes no difference in
output The truth table A AND B and B AND A are same.

Commutative Law:-
(i) A.B = B.A
IC7408 IC7408
A 1 B 1
C = A. B C = B .A
B 2 3 A 2 3

A B A.B A B B.A
0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 1 1 1

10
 (ii) A+B=B+A

IC7432 IC7432
A 1 B 2
A+B B+A
B 2 3 A 1 3

A B A+B A B B+A
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 1

Associative law
(i) A(BC) = (AB)C
IC 7408

A 4 A(BC) A 1 3 4
6 B (AB) C
5 IC 7408
2 6

5
B 1 IC 7408

C 3 C
2 IC 7408

A B C BC A (BC) A B C AB (AB) C
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 0
0 1 0 0 0 0 1 0 0 0
0 1 1 1 0 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 1 0 0
1 1 0 0 0 1 1 0 1 0
1 1 1 1 1 1 1 1 1 1

11
 (ii) A +(B + C) = (A+B) +C

IC7432
A 4 A + (B + C) A 1 A+B 4
6 = 3 6(A+B)+C
B

B 1 5 IC7432 2 5 IC7432

C 3 B+C C
2

A B C B+C A + (B+C) A B C A+B (A+B) + C

0 0 0 0 0 0 0 0 0 0
0 0 1 1 1 0 0 1 0 1
0 1 0 1 1 0 1 0 1 1
0 1 1 1 1 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1
1 0 1 1 1 1 0 1 1 1
1 1 0 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1

Distributive law
IC7408

A A(B+C)
4 6

B 1 C+B

C 2 3
IC7432

A 1 IC7408

AB
B 2 3
1 IC7432

AB + AC

4 2 3

AC
C 5 6 IC7408

12
 A B C B+C A (B+C)
A B C AB AC AB +A C
0 0 0 0 0
0 0 0 0 0 0
0 0 1 1 0
0 0 1 0 0 0
0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0
0 1 1 0 0 0
1 0 0 0 0
1 0 0 0 0 0
1 0 1 1 1
1 0 1 0 1 1
1 1 0 1 1
1 1 0 1 1 1
1 1 1 1 1
1 1 1 1 1 1

DeMorgan’s Theorem

IC7408
A 1 A.B (A.B )’
B 2 3 2
1 IC7404

IC7404

A’
A 1 2
3
A’ + B’
IC7404

B’ 4 5
IC7432

B 3 4

A B A.B (A.B)’ A B A’ B’ A’+B’

0 0 0 1 0 0 1 1 1
0 1 0 1 0 1 1 0 1
1 0 0 1 1 0 0 1 1
1 1 1 0 1 1 0 0 0

13
 IC7432
A 1 A+B (A + B)’

B 2 3 2
1 IC7404

A 1 2 A’
3

IC7404

A’ B’

IC7404 B’ 4 5

B IC7432
3 4

A B A+B (A+B)’ A B A’ B’ A’B’

0 0 0 1 0 0 1 1 1
0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 0 1 0
1 1 1 0 1 1 0 0 0

ASSOCIATIVE LAW:
1. A+(B+C) = (A+B)+C
This law states that in opening at several variables that reslts same regards at grouping
of variables A OR B with open with c is same as A opened with B OR C.

2. (AB)C = A(BC)

The associative law at multiplication states that if makes different is what order the
variable are grouped when AND use in several variable A and B AND with B AND A.

DISTRIBUTIVE LAW:

A (B+C) = AB + AC
This distributive law states that opening several variable using and adding the result with a
single variables is equivalent to A.It is important to note the distribution property. System
design used in reverse use to as expression out of (AB+AC)

14
DUALITY THEOREM:
By the duality theorem we can derive another Boolean equation by changing each OR sign
to an AND sign and changing each AND sign to an OR sign and complementing any 0 or 1
altering in the equation.

DEMORGAN’S THEOREM
DeMorgan‟s suggested two Theorem that form an important part of Boolean algebra.
They are,
1. (AB)‟ = A‟ + B‟
The complement of the product is equal to the sum of the complements.
2. (A+B)‟ = A‟B‟
The complement o sum is equal to the product of the complements.

Procedure:

1. The given AND gate and OR gate are placed in a given track in current position.

2. The pin number of AND and OR gate is shortened and then grounded.

3. The input and output is given to pin number as per the diagram.

4. The switches are on and the corresponding output is noted.

Result:
Thus the Boolean Theorems were verified using logic gates.

15
EX NO 2. Design and Implementation of combinational circuits using basic
gates for arbitrary function

Aim:-

To simplify the Boolean function

F1 (A,B,C,D) =  (0,2,3,7,5,8,11,15)
F2 (A,B,C,D) =  (1,4,5,6,12,14,15)

Components required:-

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 3 In put AND gate IC 7411 1
3. OR gate IC 7432 1
4. AND gate IC7408 1
5. Patch cords - 1

Theory:-
The Boolean function can implemented using logic gates. The components of the logic
gates directly related to implicitly of algebra expression for which it is essential to simply the
expression
Algebra means of minimization because it tools specific process value product such step
in manipulation proves the other hand the map – method.

Function – 1
F1 (A,B,C,D) =  (0,2,3,7,5,8,11,15)
Procedure:-
The above expression is first simplify by K-map and given by
F1 (A, B, C, D) = (D +BCD + ABC + ABD)
The implement function are need two input OR, AND, NOT Gates.
The connection is given as shown in connecting diagram ad the out is tabulated.

Function – 2
F2 (A, B, C, D) =  (1, 4, 5, 6, 12, 14, 15)
Procedure:-
The above expression is first simplify by K-map and given by
F1 (A, B, C, D) = ABC + ACD + BD
The implement function are need two input OR, AND, NOT Gates.
The connection is given as shown in connecting diagram ad the out is tabulated.

16
 CD
00 01 11 10
AB

00
1

01
1
1 1
1
1 1

Input Output
A B C D Y = CD + B’C’D’ + A’BD + A’B’C Y = BD’ + A’C’D + ABC
0 0 0 0 1 0
0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 1 1 1
0 1 1 0 0 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 1 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 0 0
1 1 1 0 0 1
1 1 1 1 1 1

Pin detail of IC7411 (3 Input AND gate)

17
 VCC 2
1 13
2 12

3 I 1
4 C 10
5 7 9
4
1
6 1 8
7 GND

00 01 11 10
AB
00 1 1 1

01
1
1
11
1

1
10 1

Y = CD + A’BD + A’B’C + B’C’D’

18
Pin diagram for IC 74180

19
Function table:
inputs Active Outputs
Number at high data PE PO E )
inputs
Even 1 0 1 0
Odd 1 0 0 1
Eve 0 1 0 1
Odd 0 1 1 0
X 1 1 0 0
X 0 0 1 1

Result:
Thus the Boolean function was simplified and verified successfully

20
 EX NO 3 DESIGN OF 4 BIT BINARY ADDER/SUBTRACTOR

AIM:
To Design and implement the 4-bit binary adder/ subtractor using IC 7483.

APPARATUS REQUIRED:
SL.NO COMPONENT SPECIFICATION QUANTITY
1. IC Trainer kit - 1
2. 4-bit binary full adder IC 7483 1
3. EX-OR gate IC 7486 1
4. AND gate IC 7408 1
5. OR gate IC 7432 1
6. Patch cords - Few

THEORY:
4- Bit binary adder/ subtractor:
The 4-bit binary adder/ subtractor circuit performs the operation of both addition and
subtraction. It has two 4-bit inputs A0, A1, A2, A3 and B0, B1, B2, B3. The Mode input M
controls the operation of the circuit. When M= 0, the circuit is an adder and when M=1, the
circuit becomes a Subtractor. Each exclusive-OR gate receives input M and one of the inputs
of B.
When M=0, the operation is B 0= B. The full adders receive the value of B and the
input carry is 0, and the circuit performs the addition operation, A+ B.
When M=1, the operation is B 1= B‟ and C0=1. The B inputs are all complemented
and a 1 is added through the input carry. Thus the circuit performs the subtraction operation,
i.e., A+ (2‟s complement of B) = A- B.

21
4- BIT BINARY ADDER/ SUBTRACTOR:
PIN DIAGRAM:

LOGIC DIAGRAM:

22
TRUTH TABLE:

Input data A Input data B Addition Subtraction

A3 A2 A1 A0 B3 B2 B1 B0 C S3 S2 S1 S0 B D3 D2 D1 D0
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

RESULT:
Thus the 4-bit adder/ subtractor using IC 7483 was designed and implemented.

23
EX NO 4. IMPLEMENTATION OF CODE CONVERTORS

AIM:

To design and implement 4-bit

1. Binary to Gray code Converter
2. Gray to Binary code Converter
3. BCD to Excess-3 code Converter
4. Excess-3 code to BCD Converter

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

IC Trainer kit
1. IC7486 1
EX-OR gate
2. IC7404 1
NOT gate
3. IC7432 1
OR gate
4. IC7408 1
2-Input AND gate
5. IC7411 1
3-Input AND gate
6. - 1
Patch cords
7. -
THEORY:
An availability of large variety of codes for the same discrete elements of information results in the use of
different codes by different systems. A conversion circuit must be inserted between the two systems if
each uses different codes for the same information. Thus, code converter is a circuit that makes the two
systems compatible even though each uses different binary code. The input variable are designed as
B3,B2,B1,B0 and the output variables are designed as G3,G2,G1,G0. From the truth table, combinational
circuit is designed. The Boolean functions are obtained from K-Map for each output variable

24
25
26
To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as
specified by code and the output lines generate the corresponding bit combination of code. Each one of the
four maps represents one of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps.
These are various other possibilities for a logic diagram that implements this circuit

27
28
29
PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

RESULT:
Thus the 4-bit
1. Binary to Gray code Converter
2. Gray to Binary code Converter
3. BCD to Excess-3 code Converter
4. Excess-3 code to BCD Converter was designed and implemented.

30
 EX NO 5. IMPLEMENTATION OF BCD ADDER ENCODER AND DECODER CIRCUITS

AIM:
To Design and implement the BCD adder, Encoder and Decoder Circuits using IC 7483.

APPARATUS REQUIRED FORBCD:

SL.NO COMPONENT SPECIFICATION QUANTITY
1. IC Trainer kit - 1
2. 4-bit binary full adder IC 7483 1
3. EX-OR gate IC 7486 1
4. AND gate IC 7408 1
5. OR gate IC 7432 1
6. Patch cords - Few
APPARATUS REQUIRED FOR ENCODER AND DECODER:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 3-I/P NAND gate IC7410 2
3. NOT gate IC7404 1
4. OR gate IC7432 3
5. Patch cords - Few

BCD ADDER:
LOGIC DIAGRAM:

31
5- Bit BCD Adder:
The digital system handles the decimal number in the form of binary coded decimal
numbers (BCD). A BCD adder is a circuit that adds two BCD bits and produces a sum digit
also in BCD.
In examining the contents of the table, it is apparent that when the binary sum is equal
to or less than (1001)2, the corresponding BCD number is identical, and therefore no

conversion is needed. When the binary sum is greater than 9 (1001)2, we obtain a non-valid

BCD representation. The addition of binary 6 (0110)2 to the binary sum converts it to the
correct BCD representation and also produces an output carry as required.
The logic circuit to detect sum greater than 9 can be determined by simplifying the
Boolean expression of the given truth table.
The two decimal digits, together with the input carry, are first added in the top 4-bit
binary adder to provide the binary sum. When the output carry is equal to zero, nothing is
added to the binary sum. When it is equal to one, binary (0110)2 is added to the binary sum
through the bottom 4-bit adder. The output carry generated from the bottom adder can be
ignored, since it supplies information already available at the output carry terminal. The
output carry from one stage must be connected to the input carry of the next higher-order
stage.

PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

Truth table:

32
THEORY:
Encoder:
An encoder is a digital circuit that performs inverse operation of a decoder. An
encoder has 2n input lines and „n‟ output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight inputs,
one for each octal digit and three output that generates the corresponding binary code. In
encoder it is assumed that only one input has a value of one at any given time otherwise the
circuit is meaningless. It has an ambiguila that when all inputs are zero the outputs are zero.
The zero outputs can also be generated when D0=1.

Decoder:
A decoder is a multiple output logic circuit which converts input into coded output
where input and output codes are different. The input code generally has few bits than the
output code. Each input code word produces a different output code word i.e., there is one to
one mapping can be expressed in truth table. In block diagram of decoder circuit the encoded
information is present as n input producing 2n possible outputs. The 2n output values are from
0 through out 2n-1.

ENCODER:
Logic Diagram ( 2-to-4- Line Decoder with Enable Input):

33
Truth Table:
INPUTS OUTPUTS
E A B D3 D1 D2 D3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
Logic Diagram:

Truth Table:

INPUTS OUTPUTS
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
Observe the logic output and verify with the truth tables.

RESULT:Thus the BCD adder, encoder and Decoder using IC 7483 was designed and implemented.

34
 EX NO 6. IMPLEMENTATION OF FUNCTION USING MULTIPLEXER

AIM:
To design and implement multiplexer using logic gates and study of IC74150 and 74154.

APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 3-I/P AND GATE IC7411 2
3. NOT GATE IC7404 1
4. OR GATE IC7432 1
5. Patch cords - Few

THEORY:
Multiplexer:
Multiplexer means transmitting a large number of information units over a small
number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there are
2n input line and „n‟ selection lines whose bit combination determine which input is selected.
It is called as data selector, because the output depends on the input data bit that is selected.

4:1 MULTIPLEXER:
BLOCK DIAGRAM:

35
Function table:

S1 S0 INPUTS, (Y)

0 0 D0= D0 S1‟S0‟
0 1 D1= D1 S1‟S0
1 0 D2= D2 S1S0‟
1 1 D3= D3 S1S0

Output, Y= D0 S1’S0’ +D1 S1’S0+ D2 S1S0’ +D3 S1S0

Logic Diagram:

Truth table:

S1 S0 OUTPUTS, (Y)

0 0 D0
0 1 D1
1 0 D2
1 1 D3

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.
RESULT:
Thus the multiplexer was designed and implemented using logic gates and IC74150, IC74154
was studied.
36
 EX NO 7 . DESIGN AND IMPLEMENTATION OF 3-BIT SYNCHRONOUS
UP/DOWN COUNTER

AIM:
To design and implement 3 bit synchronous up/down counter using JK flip-flop.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. JK Flip-flop IC7476 2
3. 3-I/P NAND gate IC7411 1
4. NOT gate IC7404 1
5. OR gate IC7432 1
6. EX-OR gate IC7486 1
7. Patch Cords Few

THEORY:
A Counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is one that
is capable of progressing in increasing order or decreasing order through a certain sequence.
An up/down counter is also called bi-directional counter. Usually up/down operation of the
counter is controlled by up/down signal. When this signal high counter goes through up
sequence and when up/down signal is low counter follows reverse sequence.
The counter counts upwards when UP control are logic „1‟ and DOWN control is
logic „0‟. In this case the clock input of each flip-flop other than the LSB flip-flop is fed from
the normal output of the immediately preceding flip-flop. The counter counts downwards
when the UP controls input are logic „0‟ and DOWN control is logic „1‟. In this case, the
clock input of each flip-flop other than the LSB flip-flop is fed from the complemented
output of the immediately preceding flip-flop.

37
3- BIT SYNCHRONOUS UP/DOWN COUNTER:
STATE DIAGRAM:

TRUTH TABLE:

Input Present State Next State A B C

Up/Down’ QA QB QC QA+1 QB+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 x 1 x 1 x
0 1 1 1 1 1 0 x 0 X 0 x 1
0 1 1 0 1 0 1 x 0 X 1 1 x
0 1 0 1 1 0 0 x 0 0 x x 1
0 1 0 0 0 1 1 x 1 1 x 1 x
0 0 1 1 0 1 0 0 x X 0 x 1
0 0 1 0 0 0 1 0 x X 1 1 x
0 0 0 1 0 0 0 0 x 0 x x 1
1 0 0 0 0 0 1 0 x 0 x 1 x
1 0 0 1 0 1 0 0 x 1 x x 1
1 0 1 0 0 1 1 0 x X 0 1 x
1 0 1 1 1 0 0 1 x X 1 x 1
1 1 0 0 1 0 1 x 0 0 x 1 x
1 1 0 1 1 1 0 x 0 1 x x 1
1 1 1 0 1 1 1 x 0 X 0 1 x
1 1 1 1 0 0 0 x 1 X 1 x 1

38
EXCITATION TABLE: (JK Flip-Flop)
Q Q t+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
K-MAP SIMPLIFICATION:

39
LOGIC DIAGRAM:

PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the logic diagram.
3. Observe the logic output and verify with the truth tables.

RESULT:

Thus 3- bit synchronous up/down counter was designed and implemented successfully.

40
 EX NO 8. IMPLEMENTATION OF SHIFT REGISTERS USING FLIP-FLOPS

AIM:
To design and implement
1. Serial in serial Out(SISO)
2. Serial in parallel Out(SIPO)
3. Parallel in serial Out(PISO)
4. Parallel in parallel Out(PIPO)

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. D-Flip flop IC7474 2
3. AND gate IC7408 1
4. OR gate IC7432 1
5. NOT gate IC7404 1
6. Patch cords - Few

THEORY:
A register is capable of shifting its binary information in one or both directions is
known as shift register. A logical configuration of shift register consist of a D flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip flop is
connected to the input of next flip flop of the register. Each clock pulse shifts the content of
register one bit position to right.

41
SHIFT REGISTER:
PIN DIAGRAM: (D-Flip-Flop)

Function Table:

Inputs Outputs
Preset Clear Clock D Q Q’
0 1 X X 1 0
1 0 X X 0 1
0 0 X X 1 1
1 1 0 0 1
1 1 1 1 0
1 1 0 X No Change

SERIAL IN SERIAL OUT:

LOGIC DIAGRAM:

42
TRUTH TABLE:
CLK Serial IN Serial OUT
1 1 0
2 1 0
3 1 0
4 1 1
5 0 1
6 0 1
7 0 1
8 0 0

Serial IN Parallel OUT:

LOGIC DIAGRAM:

TRUTH TABLE:

OUTPUT
CLK DATA
Q3 Q2 Q1 Q0
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 0
4 1 1 0 0 1

43
Parallel IN Serial OUT:
LOGIC DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUT
S/ L’ CLK
A B C D Q
0 0 1 0 0 1 1
1 1 1 0 0 1 0
1 2 1 0 0 1 0
1 3 1 0 0 1 1

44
Parallel IN Parallel OUT:
Logic Diagram:

TRUTH TABLE:

DATA INPUTS OUTPUT

CLK
D3 D2 D1 D0 Q3 Q2 Q1 Q0
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the logic diagram.
3. Observe the logic output and verify with the truth tables.
RESULT:
Thus the design and implementation of
1. Serial in serial Out (SISO)
2. Serial in parallel Out (SIPO)
3. Parallel in serial Out (PISO)
4. Parallel in parallel Out (PIPO) were done successfully.

45
EXP.NO. 9 SIMULATOR BASED STUDY OF COMPUTER ARCHITECTURE

1. Starting the ISE Software

To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting:

Start → Programs → Xilinx ISE 9.1i → Project Navigator

2. Create a New Project

To create a new project:
1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory
is created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.

Figure 1: Create New Project

6. Fill in the properties in the table as shown below:

46
 ♦ Product Category: All
♦ Family: Spartan3
♦ Device: XC3S200
♦ Package: FT256
♦ Speed Grade: -4
♦ Top-Level Source Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Preferred Language: Verilog (or VHDL)
♦ Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
When the table is complete, your project properties will look like the following:

Figure 2: Project Device Properties

7. Click Next to proceed to the Create New Source window in the New Project Wizard.

3. Creating a Verilog Source

Create the top-level Verilog source file for the project as follows:
1. Click New Source in the New Project dialog box.
2. Select Verilog Module as the source type in the New Source dialog box.
3. Type in the file name adder.
4. Verify that the Add to Project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown below:

47
 Figure 3: Define Module
7. Click Next, then Finish in the New Source Information dialog box to complete the new
source file template.
8. Click Next, then Next, then Finish.

The source file containing the adder Module displays in the Workspace, and the adder
displays in the Sources tab, as shown below:

Figure 4: New Project in ISE

4. Checking the Syntax of the New Counter Module

When the source files are complete, check the syntax of the design to find errors.
1. Verify that Synthesis/Implementation is selected from the drop-down list in the
48
Sources window.

Figure 5: Synthesis/Implementation Selection

2. Select the adder design source in the Sources window to display the related
processes in the Processes window.
3. Click the “+” next to the Synthesize-XST process to expand the process group.

Figure 6: Synthesize- XST Expansion

3. Double-click the Check Syntax process.

49
 Figure 7: Double click to Check Syntax

Note: You must correct any errors found in your source files. You can check for errors in
the Console tab of the Transcript window. If you continue without valid syntax, you will not
be able to simulate or synthesize your design.

Figure 8: After correcting errors

5. Close the HDL file.

5. Simulating Design Functionality

Verify that the adder design functions as you expect by performing behavior simulation as
follows:
1. Verify that Behavioral Simulation is selected in the Sources window.

50
Figure 9: Behavioral Simulation Selection
2. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process
and double-click the Simulate Behavioral Model process.

Figure 10: Simulate Behavioral Model

The ISE Simulator opens and runs the simulation to the end of the test bench.
3. To view your simulation results, select the Simulation tab and zoom in on the
transitions.
The simulation waveform results will look like the following:

Figure 11: Simulation waveform

51
 ADDITIONAL EXPERIMENT

EX NO 10. SIMULATION OF COMBINATIONAL CIRCUITS USING

VERILOG HDL
AIM:
To design Adder/Subtractor using HDL software
FULL ADDER:

VERILOG CODE FOR FULLADDER

Module fulladder (a,b,c,sum,carry);

input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry= a&b|b&c|a&c;
end Module

OUTPUT

52
HALF SUBTRACTOR:

VERILOG CODE FOR HALF SUBTRACTOR:

Module halfsubtractor (a,b,difference ,borrow);

input a,b;
output difference,borrow;
assign difference=a^b;
assign borrow = ~a&b;
end Module

53
4:1 MULTIPLEXER

VERILOG CODE FOR 4:1 MULTIPLEXER:

Module mux(s,d0,d1,d2,d3,y);
input d0,d1,d2,d3;
input[1:0]s;
output y;
assign y=((d0&~s[1]&~&s[0])|( d1&~s[1]&s[0])|( d2&s[1]&~s[0])|
(d3&s[1]&s[0]));
end Module
OUTPUT:

54
1:4 DEMULTIPLEXER:

VERILOG CODE FOR 1:4 DEMULTIPLEXER:

Module mux(s,a,d0,d1,d2,d3);
input a;
input[1:0]s;
output d0,d1,d2,d3;
assign d0=(~s[1]&~s[0]&a);
assign d1=(~s[1]&s[0]&a);
assign d2=(s[1]&~s[0]&a);
assign d3=(s[1]&s[0]&a);
end Module
OUTPUT:

55
PROCEDURE:

2. Draw the Digital logic circuits.

3. Write the Verilog code for above circuits.
4. Enter the Verilog code in ModelSim software.
5. Check the syntax and simulate the above verilog code using ModelSim and
verify the output waveform as obtained.

RESULT:

Thus the combinational logic circuits using Verilog HDL was simulated.

56