CHAPTER ONE

THE 8086 MICROPROCESSOR AND ITS ARCHITECTURE

The Intel 8086 is a 16-bit microprocessor that is intended to be used as the CPU in a
microcomputer. The term 16-bit means that its arithmetic logic unit, its internal registers,
and most of its instructions are designed to work with 16-bit binary words. The 8086 has
a 16-bit data bus, so it can read data from or write data to memory and ports either 16 bits
or 8 bits at a time. The 8086 has a 20-bit address bus, so it can address any one of 220, or
1,048,576, memory locations. Each of the 1,048,576 memory addresses of the 8086
represent a byte-wide location. Sixteen-bit words will be stored in two consecutive
memory locations.

8086 Internal Architecture

The 8086 microprocessor is divided into two independent functional units. These are the
Bus Interface Unit (BIU) and the Execution Unit (EU). These two functional unit can
work simultaneously to increase system speed and hence the throughput. Throughput is a
measure of number of instructions per unit time.

Bus Interface Unit

The bus interface unit is the 8086’s interface to the outside world. It provides a full 16-bit
bi-directional data bus and 20-bit address bus. The bus interface unit is responsible for
performing all external bus operations.
Functions of the bus interface unit are:
 It sends address to the memory or I/O
 It fetches instruction from memory
 It reads data from memory/port
 It writes data into memory/port
 It supports instruction queuing
To implement these functions the BIU contains the instruction queue, segment registers,
instruction pointers, and address summer.

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Instruction Queue
To speed up program execution, the BIU fetches six instruction bytes ahead of time from the
memory. These prefetched instruction bytes are held for the execution unit in a group of register
called Queue. With the help of queue it is possible to fetch next instruction when the current
instruction is in execution. For example, current instruction in execution is a multiplication
instruction. In 8086, operands for multiplication operations are within the register that requires
100 clock cycles to execute it. During this execution time the BIU fetches the next instruction or
instructions from memory into the instruction queue instead of remaining idle. The BIU
continues this process as long as the queue is not full. Due to this, the execution unit gets the
ready instruction in the queue and instruction fetch time is eliminated.

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The queue operates on the principle of first-in-first-out (FIFO). So that the execution unit gets
the instructions for execution in the order they are fetched. In case of JUMP and CALL
instructions, instructions already fetched in the queue are of no use. Hence, in these cases queue
is dumped and newly formed by loading instructions from new address specified by JUMP or
CALL instruction. Feature of fetching the next instruction while the current instruction is
executing is called pipelining.

Segment Registers
The physical address of the 8086 is 20-bits wide to access 1 Mbyte memory locations. However,
its registers and memory locations which contain logical addresses are just 16-bits wide. Hence
8086 uses memory segmentation. It treats the 1 Mbyte of memory as divided into segments, with
a maximum size of a segment as 64Kbytes. Thus any location within the segment can be
accessed using 16 bits. The 8086 allows only four active segments at a time. For the selection of
the four active segments the 16-bit segment registers are provided within the BIU of the 8086.
These four registers are:

❖ Code Segment (CS) register: - used to holds the upper 16-bits of the starting of the
segment from which the BIU is currently fetching the instruction code byte.
❖ Data Segment (DS) register:- used to hold the 16-bits of the starting address of the
memory segment which is used for data.
❖ Extra Segment (ES) register: - used to hold the 16-bits of the starting address of the
memory segment which is used for data.
❖ Stack Segment (SS) register:- used for the upper 16-bits of the starting address for the
program stack.
The four segments can overlap for small programs. The segment can begin/start at any memory
address divisible by 16.

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 Physical
Address
FFFFFH Highest address
7FFFFH Top of extra segment

64 K

70000H Extra segment base ES = 7000H

5FFFFH Top of stack segment

64 K

50000H Stack segment base SS = 5000H

4489FH Top of code segment

64 K

348A0H Code segment base CS = 348AH

2FFFFH Top of data segment

64 K

20000H Bottom of data segment

Instruction Pointer
The instruction pointer register holds the 16-bit address of the next code byte within the code
segment. The value contained in the IP is referred to as an offset. This value must be offset from
(added to) the segment base address to produce the required 20-bit physical address.

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 To generate the 20-bit physical address, the content of the CS register is multiplied by 16 i.e.
shifted by four to the left, and then the offset i.e. the content of IP register are added to the
shifted contents of CS.
For example: If CS = 348AH and IP = 4214H then the physical address is

CS 3 4 8 A 0 Implied zero
IP + 4 2 1 4
Physical Address 3 8 A B 4

Execution Unit (EU)

The execution unit of the 8086 tells the BIU where to fetch instructions or data from, decodes
instructions and executes instruction.
The EU contains control circuitry which directs the internal operations. A decoder in the EU
translates the instructions fetched from memory into a series of actions which the EU carries out.
ALU is a 16-bit which can add, subtract, AND, OR, XOR, increment, complement and shift
binary numbers.

Flag Register
A flag is a flip-flop which indicates some condition produced by the execution of an instruction
or controls certain operations of the EU. The flag register contains nine active flags.

U U U U OF DF IF TF SF ZF U AF U PF U CF

❖ Carry Flag (CF):- In case of addition this flag is set if there is a carry out of the MSB.
The carry flag also serves as a borrow flag for subtraction and it is set when borrow is
needed.
❖ Parity Flag (PF):- It is set to 1 if the result of byte operation contains an even number of
ones; otherwise it is cleared.

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❖ Auxiliary Flag (AF):- This is set if there is an overflow out of bit 3 i.e. carry from lower
nibble to higher nibble. This flag is used for BCD operations.
❖ Zero Flag (ZF):- The zero flag is set if the result of operation in ALU is zero and resets
if the result is nonzero.
❖ Sign Flag (SF):- After the execution of arithmetic or logic operations, if the MSB of the
result is 1, the sign bit is set. Sign bit 1 indicates the result is negative; otherwise it is
positive.
❖ Overflow Flag (OF):- This flag is set if the result is out range. For addition this flag is
set when there is a carry into the MSB and no carry out of the MSB or vice versa.
Example:
0110 0101 1101 0001
+
0010 0011 0101 1001
1000 1001 0010 1010
SF = 1, ZF = 0, PF = 1, CF = 0, AF = 0, OF = 1

The three remaining flags are used to control certain operations of the processor.
❖ Trap Flag (TF):- One way to debug a program is to run the program one instruction
at a time and see the contents of used registers and memory variables after execution
of every instruction. This process is called single stepping through a program. Trap
flag is used for single stepping through a program. If set, a trap is executed after
execution of each instruction, i.e. interrupt service routine is executed which displays
various registers and memory variable contents on the display after execution of each
instruction.
❖ Interrupt Flag (IF):- It is used to allow/prohibit the interruption of a program. If set,
a certain type of interrupt (a maskable interrupt) can be organized by the 8086;
otherwise, these interrupts are ignored.
❖ Direction Flag (DF):- It is used with string instructions. If DF = 0, the string is
processed from its beginning with the first element having the lowest address.
Otherwise, the string is processed from the high address towards the low address.

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General Purpose Register
The EU has eight general purpose registers labelled AH, AL, BH, BL, CH, CL, DH, and DL.
These registers can be used individually for temporary storage of 8 bit data. The AL register is
also called accumulator. Certain pairs of theses general purpose registers are used together to
store 16-bit data, such as AX, BX, CX, and DX.

Pointers and Index Registers

All segment registers are 16-bits. But it is necessary to put 20-bit address (physical address) on
the address bus. To get 20-bit physical address one more register is associated with each segment
register like IP associated with CS. These additional registers belong to the pointer and index
group. The pointer and index group consists of IP, SP, BP, SI, and DI register.
The stack pointer (SP) contains the 16-bit offset from the start to the top of stack segment. Base
pointer (BP) can also be used for accessing the stack. Source Index (SI) can be used to hold the
offset of a data word in the data segment. Destination Index (DI) string instruction always uses
ES and DI to determine the 20-bit physical address for the destination.