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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers

MAX22700E–MAX22702E

General Description Benefits and Features

The MAX22700–MAX22702 are a family of single-channel ● Matching Propagation Delay
isolated gate drivers with ultra-high common-mode tran- • 20ns Minimum Pulse Width
sient immunity (CMTI) of 300kV/μs (typ). The devices are • 35ns Propagation Delay at Room Temperature
designed to drive silicon-carbide (SiC) or gallium-nitride • 2ns Part-to-Part Propagation Delay Matching at
(GaN) transistors in various inverter or motor control appli- Room Temperature
cations with different output gate-drive circuitry and B-side • 5ns Part-to-Part Propagation Delay Matching over
supply voltages. The devices feature variants with output -40°C to +125°C Temperature Range
options for gate driver common pin GNDB (MAX22700), ● High CMTI (300kV/μs, typ)
Miller Clamp (MAX22701), and adjustable undervoltage- ● Robust Galvanic Isolation
lockout UVLO (MAX22702). In addition, variants are of- • Withstands 3kVRMS (Narrow SOIC) or 5kVRMS
fered as differential (D versions) or single-ended (E ver- (Wide SOIC) for 60s (VISO)
sions) inputs. All devices have integrated digital galvanic • Continuously Withstands 600VRMS (Narrow SOIC)
isolation using Maxim’s proprietary process technology. or 848VRMS (Wide SOIC) (VIOWM)
The MAX22700–MAX22702 feature isolation for a with- • Withstands ±5kV Surge Between GNDA and VSSB
stand voltage rating of 3kVRMS (narrow SOIC package) or with 1.2/50μs Waveform
5kVRMS (wide SOIC package) for 60 seconds.
● Precision UVLO
All devices support a minimum pulse width of 20ns with ● Options to Support a Broad Range of Applications
a maximum pulse width distortion of 2ns. The part-to-part • 3 Output Options: GNDB, Miller Clamp, or
propagation delay is matched within 2ns (max) at +25°C Adjustable UVLO
ambient temperature, and 5ns (max) over the -40°C to • 2 Input Configurations: Single-Ended with Enable
+125°C operating temperature range. This feature re- (E versions) or Differential (D versions)
duces the power transistor’s dead time, thus improving
overall efficiency.
The MAX22700 and the MAX22702 have a maximum
Safety Regulatory Approvals
RDSON of 1.25Ω for the low-side driver, and the ● UL According to UL1577
MAX22701 has an RDSON of 2.5Ω for the low-side driver. ● cUL According to CSA Bulletin 5A
All devices have a maximum RDSON of 4.5Ω for the high- ● VDE 0884-11 Basic Insulation (Wide SOIC) (Pending)
side driver. See the Ordering Information for suffixes as-
sociated with each option.
The MAX22700–MAX22702 are available either in an
8-pin wide-body SOIC package with 8mm creepage and
clearance, or in a smaller 8-pin narrow-body SOIC pack-
age with 4mm of creepage and clearance. The narrow
SOIC package material has a minimum comparative track-
ing index (CTI) of 600, which gives it a group I rating in
creepage tables, while the wide SOIC package material
has a minimum CTI of 400, which gives it a group II rating
in creepage tables. All devices are rated for operation at
ambient temperatures of -40°C to +125°C.

Applications
● Isolated Gate Driver for Inverters
● Motor Drives
● UPS and PV Inverters

Ordering Information appears at end of data sheet. 19-100581; Rev 11; 7/22

© 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2022 Analog Devices, Inc. All rights reserved.
MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Functional Diagrams
MAX22701

VDDA VDDB VDDA VDDB

MAX22701E MAX22701D

IN UVLO, INP UVLO,

UVLO CONTROL UVLO CONTROL
AND LOGIC, OUT AND LOGIC, OUT
LOGIC AND LOGIC AND
EN INPUTS OUTPUT INN INPUTS OUTPUT
DRIVER DRIVER
VSSB VSSB
GNDA CLAMP GNDA CLAMP
2V 2V

VSSB VSSB

MAX22700 and MAX22702

VDDA MAX22700E VDDB VDDA MAX22700D VDDB

MAX22702E MAX22702D
IN UVLO, INP UVLO,
UVLO CONTROL UVLO CONTROL
AND LOGIC, OUT AND LOGIC, OUT
LOGIC AND LOGIC AND
EN INPUTS OUTPUT INN INPUTS OUTPUT
DRIVER DRIVER
VSSB VSSB
GNDA GNDA
GNDB/ADJ GNDB/ADJ

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Absolute Maximum Ratings

VDDA to GNDA ......................................................... -0.3V to +6V Continuous Power Dissipation (TA = +70°C)
VDDB to GNDB ....................................................... -0.3V to +40V Narrow SOIC (derate 9.39mW/°C above +70°C) .....750.89mW
GNDB to VSSB ....................................................... -0.3V to +40V Wide SOIC (derate 8.51mW/°C above +70°C) ........681.14mW
VDDB to VSSB ......................................................... -0.3V to +40V Operating Temperature Range ...........................-40ºC to +125ºC
INP, INN, IN, EN to GNDA ....................................... -0.3V to +6V Maximum Junction Temperature ...................................... +150ºC
VDDB to ADJ............................................................. -0.3V to +6V Storage Temperature Range .............................. -60ºC to +150ºC
CLAMP to VSSB ....................................... -0.3V to (VDDB + 0.3V) Soldering Temperature (reflow) ........................................ +260ºC
OUT to VSSB ............................................ -0.3V to (VDDB + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Package Information
8 Narrow SOIC
Package Code S8MS+23
Outline Number 21-0041
Land Pattern Number 90-0096
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient (θJA) 106.54°C/W
Junction-to-Case Thermal Resistance (θJC) 44.91°C/W

8 Wide SOIC
Package Code W8MS+6
Outline Number 21-100415
Land Pattern Number 90-100146
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient (θJA) 117.45°C/W
Junction-to-Case Thermal Resistance (θJC) 58.48°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

DC Electrical Characteristics
(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB = 0V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
VDDA Relative to GNDA 3 5.5
Relative to GNDB, MAX22700 13 28
Supply Voltage VDDB Relative to VSSB, MAX22701 13 28 V
Relative to VSSB, MAX22702 6 28
VSSB Relative to GNDB, MAX22700 -16 0
Differential Supply VDIFF VDDB - VSSB, MAX22700 13 28 V
Undervoltage-Lockout VUVLOAP VDDA rising 2.69 2.82 2.95
V
Threshold VUVLOAN VDDA falling 2.59 2.72 2.85
Undervoltage-Lockout
VUVLOA_HYST 100 mV
Threshold Hysteresis
VDDB rising, relative to GNDB,
VUVLOBP 13 13.3
MAX22700
VDDB falling, relative to GNDB,
VUVLOBN 11.6 12
MAX22700
Undervoltage-Lockout
VUVLOBP VDDB rising, relative to VSSB, MAX22701 13 13.3 V
Threshold
VUVLOBN VDDB falling, relative to VSSB, MAX22701 11.6 12
VUVLOBP VDDB rising, relative to ADJ, MAX22702 2 2.05
VUVLOBN VDDB falling, relative to ADJ, MAX22702 1.79 1.84
Undervoltage-Lockout MAX22700, MAX22701 1
VUVLOB_HYST V
Threshold Hysteresis MAX22702 0.16
SUPPLY CURRENT
A-Side Quiescent VDDA = 5V, INN/EN = VDDA 5 6.5
IDDA mA
Supply Current VDDA = 3.3V, INN/EN = VDDA 3 4
A-Side Active Supply VDDA = 5V, fPWM = 1MHz 5 6.5
IDDA mA
Current VDDA = 3.3V, fPWM = 1MHz 3 4
B-Side Quiescent
IDDB INN/EN = VDDA 3.5 6 mA
Positive Supply Current
B-Side Active Positive
IDDB fPWM = 1MHz (Note 2) 6 10 mA
Supply Current
B-Side Ground Current IGNDB MAX22700 -25 µA
LOGIC INTERFACE (INP, INN, IN, EN)
0.7 x
Input High Voltage VIH V
VDDA
0.3 x
Input Low Voltage VIL V
VDDA
0.1 x
Input Hysteresis VHYS mV
VDDA
Input Pullup Current IPU INN, EN (Note 3) -10 -5 -1.5 µA
Input Pulldown Current IPD INP, IN (Note 3) 1.5 5 10 µA
Input Capacitance CIN fPWM = 1MHz 2 pF

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

DC Electrical Characteristics (continued)

(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB = 0V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADJ (MAX22702 ONLY)
Input Leakage Current IADJ VDDB - VADJ = 3V -100 100 nA
GATE DRIVER
High-Side Transistor
RDSON_H IOUT = -100mA (Note 3) 4.7 Ω
On-Resistance
MAX22700/
Low-Side Transistor IOUT = 100mA 1.25
RDSON_L MAX22702 Ω
On-Resistance (Note 3)
MAX22701 2.5
Output-Voltage High VOH IOUT = -10mA (Note 3) 19.95 V
MAX22700/
IOUT = 10mA 0.01
Output-Voltage Low VOL MAX22702 V
(Note 3)
MAX22701 0.02
High-Side Transistor
IOH CL = 10nF, fPWM = 1kHz (Note 2) 2.35 4 A
Peak Output Current
MAX22700/
Low-Side Transistor CL = 10nF, fPWM = 3.7 5.7
IOL MAX22702 A
Peak Output Current 1kHz (Note 2)
MAX22701 1.9 2.85
Active Pulldown Voltage VOUTSD IOUT = 150mA (Note 3) 2.2 V
MILLER CLAMP (MAX22701 ONLY)
Miller Clamp Transistor
RDSON_CLMP ICLAMP = 100mA (Note 3) 2.5 Ω
On-Resistance
Miller Clamp Threshold VTH_CLMP 1.7 2 2.3 V
Miller Clamp Turn-On
tON See Figure 2 20 ns
Time
THERMAL SHUTDOWN
Thermal-Shutdown
TSHDN 160 °C
Threshold
Thermal-Shutdown
TSHDN_HYS 25 °C
Hysteresis

Dynamic Characteristics
(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB = 0V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Common-Mode
CMTI (Note 4) 300 kV/µs
Transient Immunity
Minimum Pulse Width PWMIN CL = 200pF 20 ns
Maximum PWM
fPWM 1 MHz
Frequency

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Dynamic Characteristics (continued)

(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB = 0V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TA = +25°C to
34 39
+125°C
tPLH TA = +25°C 34 35 36
CL = 200pF, output TA = -40°C to
is not connected to 31 36
Propagation Delay +25°C
CLAMP pin ns
(Figure 1) TA = +25°C to
(MAX22701) 34 39
(Note 5) +125°C
tPHL TA = +25°C 34 35 36
TA = -40°C to
31 36
+25°C
TA = +25°C 2
Part-to-Part Propagation TA = -40°C to
CL = 200pF
Delay Matching tPM +125°C, parts at ns
(Note 5) 5
(Figure 1) the same
temperature
Pulse Width Distortion PWD CL = 200pF, |tPLH - tPHL| 2 ns
Peak Eye Diagram Jitter TJIT(PK) 1MHz square wave, CL = 200pF 60 ps
Rise Time (Figure 1) tR CL = 200pF, 20% to 80% (Note 2) 3.6 ns
MAX22700/
CL = 200pF, 80% 1.8
Fall Time (Figure 1) tF MAX22702 ns
to 20% (Note 2)
MAX22701 2.5

ESD Protection
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ESD Human Body Model, All Pins ±4 kV

Insulation Characteristics - 8 Narrow SOIC

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Partial Discharge Test Method B1 = VIORM x 1.5
VPR 1272 VP
Voltage (t = 1s, partial discharge < 5pC)
Maximum Repetitive-
VIORM (Note 6) 848 VP
Peak Isolation Voltage
Maximum Working
VIOWM Continuous RMS voltage (Note 6) 600 VRMS
Isolation Voltage
Maximum Transient
VIOTM t = 1s (Note 6) 4242 VP
Isolation Voltage
Maximum Withstand fSW = 60Hz, duration = 60s (Note 6, Note
VISO 3000 VRMS
Isolation Voltage 7)
Maximum Surge Basic insulation, 1.2/50µs pulse per IEC
VIOSM 5 kV
Isolation Voltage 61000-4-5 (Note 6, Note 9)

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Insulation Characteristics - 8 Narrow SOIC (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VIO = 500V, TA = 25°C > 1012
Insulation Resistance RIO VIO = 500V, 100°C ≤ TA ≤ 125°C > 1011 Ω
VIO = 500V at TS = 150°C > 109
Barrier Capacitance
CIO fSW = 1MHz (Note 8) 1 pF
Side A-to-Side B
Minimum Creepage
CPG Narrow SOIC 4 mm
Distance
Minimum Clearance
CLR Narrow SOIC 4 mm
Distance
Internal Clearance Distance through insulation 0.015 mm
Comparative Tracking
CTI Material Group I (IEC 60112) > 600
Index
40/125/
Climate Category
21
Pollution Degree
(DIN VDE 0110, Table 2
1)

Insulation Characteristics - 8 Wide SOIC

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Partial Discharge Test Method B1 = VIORM x 1.5
VPR 1800 VP
Voltage (t = 1s, partial discharge < 5pC)
Maximum Repetitive
VIORM (Note 6) 1200 VP
Peak Isolation Voltage
Maximum Working
VIOWM Continuous RMS voltage (Note 6) 848 VRMS
Isolation Voltage
Maximum Transient
VIOTM t = 1s (Note 6) 7000 VP
Isolation Voltage
Maximum Withstand fSW = 60Hz, duration = 60s (Note 6, Note
VISO 5000 VRMS
Isolation Voltage 7)
Maximum Surge Basic insulation, 1.2/50µs pulse per IEC
VIOSM 5 kV
Isolation Voltage 61000-4-5 (Note 6, Note 9)
VIO = 500V, TA = 25°C > 1012
Insulation Resistance RIO VIO = 500V, 100°C ≤ TA ≤ 125°C > 1011 Ω
VIO = 500V at TS = 150°C > 109
Barrier Capacitance
CIO fSW = 1MHz (Note 8) 1 pF
Side A-to-Side B
Minimum Creepage
CPG Wide SOIC 8 mm
Distance
Minimum Clearance
CLR Wide SOIC 8 mm
Distance
Internal Clearance Distance through insulation 0.015 mm
Comparative Tracking
CTI Material Group II (IEC 60112) > 400
Index

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Insulation Characteristics - 8 Wide SOIC (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
40/125/
Climate Category
21
Pollution Degree
(DIN VDE 0110, Table 2
1)

Note 1: All devices are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design and
characterization.
Note 2: Not production tested. Guaranteed by design and characterization.
Note 3: All currents into the device are positive. All currents out of the device are negative. All voltages are referenced to their
respective ground (GNDA or VSSB), unless otherwise noted.
Note 4: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output. CMTI applies to both
rising and falling common-mode voltage edges. CMTI is tested with the transient generator connected between GNDA and
VSSB (VCM = 1000V).
Note 5: Propagation delay is measured from 50% of the input to 2V at the output.
Note 6: VISO, VIOTM, VIOSM, VIOWM, and VIORM are defined by the IEC 60747-5-5 standard.
Note 7: Product is qualified at VISO for 60s and 100% production tested at 120% of VISO for 1s.
Note 8: Capacitance is measured with all pins on side A and side B tied together.
Note 9: Devices are immersed in oil during surge characterization.

VDDA VDDA VDDB VDDB

MAX2270_E
IN VDDA
IN
OUT1 IN
TEST OUT 50% 50%
CL
SOURCE EN
200pF GNDA
tPLH tPHL
GNDA VSSB

VDDB

OUT1

VSSB 2V 2V
tPM tPM
VDDA VDDB
VDDB
OUT2 80%
MAX2270_E
IN 20%
OUT2 VSSB 2V 2V
OUT
CL
EN 200pF tR tF
GNDA VSSB

(A) (B)

Figure 1. Test Circuit (A) and Timing Diagram (B)

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

VDDA
INPUT
SOURCE
GNDA
VDDA VDDB
VDDA VDDB
VDDB
MAX22701E
50Ω TEST
IN CLAMP SOURCE
CL VSSB
INPUT TEST
EN 200pF
SOURCE SOURCE
GNDA VSSB VDDB

VTH_CLMP = 2V
CLAMP
VSSB

tON = 20ns
(A) (B)

Figure 2. MAX22701 Miller Clamp Test Circuit (A) and Timing Diagram (B)

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Operating Characteristics

(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB, TA = +25°C, unless otherwise noted.)

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Operating Characteristics (continued)

(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB, TA = +25°C, unless otherwise noted.)

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Operating Characteristics (continued)

(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB, TA = +25°C, unless otherwise noted.)

Pin Configurations - MAX22700

TOP VIEW

+ +
VDDA 1 8 VSSB VDDA 1 8 VSSB
MAX22700D MAX22700E

INP 2 7 GNDB IN 2 7 GNDB

INN 3 6 OUT EN 3 6 OUT

GNDA 4 5 VDDB GNDA 4 5 VDDB

NARROW AND WIDE SOIC NARROW AND WIDE SOIC

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Pin Description - MAX22700

PIN REF
NAME FUNCTION
MAX22700D MAX22700E SUPPLY
POWER
Power Supply Input for Side A (Transmitter Side). Bypass VDDA
1 1 VDDA to GNDA with 1nF || 0.1μF || 1μF ceramic capacitors as close as GNDA
possible to the pin.
4 4 GNDA Ground Reference for Side A (Transmitter Side). GNDA
Positive Power Supply Input for Side B (Driver Side). Bypass
VDDB to VSSB with 1nF || 0.1μF || 1μF ceramic capacitors as
5 5 VDDB GNDB
close as possible to the pin. Place an additional 22μF capacitor
between VDDB and VSSB.
8 8 VSSB Negative Power Supply Input for Side B (Driver Side). GNDB
Gate Driver Common Pin. Connect to the power transistor’s
7 7 GNDB source pin. The B-side UVLO is referenced to GNDB in the GNDB
MAX22700 versions.
INPUTS
Non-Inverting PWM Input on Side A (D Version). Has a weak
2 - INP internal pulldown. Connect the differential PWM control inputs to GNDA
INP and INN. Refer to Table 2 for Inputs vs. Output Truth table.
Inverting PWM Input on Side A (D Version). Has a weak internal
3 - INN pullup to VDDA. Connect the differential PWM control inputs to GNDA
INP and INN. Refer to Table 2 for Inputs vs. Output Truth table.
Single-Ended PWM Input on Side A (E Version). Has a weak
- 2 IN internal pulldown. Refer to Table 3 for Inputs vs. Output Truth GNDA
table.
Active-Low Enable on Side A (E Version). Has a weak internal
- 3 EN GNDA
pullup to VDDA.
OUTPUT
6 6 OUT Gate Driver Output on Side B. GNDB

Pin Configurations - MAX22701

TOP VIEW

+ +
VDDA 1 8 VSSB VDDA 1 8 VSSB
MAX22701D MAX22701E

INP 2 7 CLAMP IN 2 7 CLAMP

INN 3 6 OUT EN 3 6 OUT

GNDA 4 5 VDDB GNDA 4 5 VDDB

NARROW AND WIDE SOIC NARROW AND WIDE SOIC

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Pin Description - MAX22701

PIN REF
NAME FUNCTION
MAX22701D MAX22701E SUPPLY
POWER
Power Supply Input for Side A (Transmitter Side). Bypass VDDA
1 1 VDDA to GNDA with 1nF || 0.1μF || 1μF ceramic capacitors as close as GNDA
possible to the pin.
4 4 GNDA Ground Reference for Side A (Transmitter Side). GNDA
Positive Power Supply Input for Side B (Driver Side). Bypass
VDDB to VSSB with 1nF || 0.1μF || 1μF ceramic capacitors as
5 5 VDDB VSSB
close as possible to the pin. Place an additional 22μF capacitor
between VDDB and VSSB.
8 8 VSSB Negative Power Supply Input for Side B (Driver Side). VSSB
INPUTS
Non-Inverting PWM Input on Side A (D Version). Has a weak
2 - INP internal pulldown. Connect the differential PWM control inputs to GNDA
INP and INN. Refer to Table 2 for Inputs vs. Output Truth table.
Inverting PWM Input on Side A (D Version). Has a weak internal
3 - INN pullup to VDDA. Connect the differential PWM control inputs to GNDA
INP and INN. Refer to Table 2 for Inputs vs. Output Truth table.
Single-Ended PWM Input on Side A (E Version). Has a weak
- 2 IN internal pulldown. Refer to Table 3 for Inputs vs. Output Truth GNDA
table.
Active-Low Enable on Side A (E Version). Has a weak internal
- 3 EN GNDA
pullup to VDDA.
INPUT/OUTPUT
Active Miller Clamp Input/Output on Side B. Prevents false turn-on
7 7 CLAMP VSSB
of the power transistor.
OUTPUT
6 6 OUT Gate Driver Output on Side B. VSSB

Pin Configurations - MAX22702

TOP VIEW

+ +
VDDA 1 8 VSSB VDDA 1 8 VSSB
MAX22702D MAX22702E

INP 2 7 ADJ IN 2 7 ADJ

INN 3 6 OUT EN 3 6 OUT

GNDA 4 5 VDDB GNDA 4 5 VDDB

NARROW AND WIDE SOIC NARROW AND WIDE SOIC

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Pin Description - MAX22702

PIN REF
NAME FUNCTION
MAX22702D MAX22702E SUPPLY
POWER
Power Supply Input for Side A (Transmitter Side). Bypass VDDA
1 1 VDDA to GNDA with 1nF || 0.1μF || 1μF ceramic capacitors as close as GNDA
possible to the pin.
4 4 GNDA Ground Reference for Side A (Transmitter Side). GNDA
Positive Power Supply Input for Side B (Driver Side). Bypass
VDDB to VSSB with 1nF || 0.1μF || 1μF ceramic capacitors as
5 5 VDDB VSSB
close as possible to the pin. Place an additional 22μF capacitor
between VDDB and VSSB.
8 8 VSSB Negative Power Supply Input for Side B (Driver Side). VSSB
INPUTS
Non-Inverting PWM Input on Side A (D Version). Has a weak
2 - INP internal pulldown. Connect the differential PWM control inputs to GNDA
INP and INN. Refer to Table 2 for Inputs vs. Output Truth table.
Inverting PWM Input on Side A (D Version). Has a weak internal
3 - INN pullup to VDDA. Connect the differential PWM control inputs to GNDA
INP and INN. Refer to Table 2 for Inputs vs. Output Truth table.
Single-Ended PWM Input on Side A (E Version). Has a weak
- 2 IN internal pulldown. Refer to Table 3 for Inputs vs. Output Truth GNDA
table.
Active-Low Enable on Side A (E Version). Has a weak internal
- 3 EN GNDA
pullup to VDDA.
Adjustable UVLO Input on Side B. Connect external resistors
7 7 ADJ between VDDB and ADJ and between ADJ and the power VSSB
transistor's source pin to adjust the B-side UVLO.
OUTPUT
6 6 OUT Gate Driver Output on Side B. VSSB

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Detailed Description
The MAX22700–MAX22702 are a family of single-channel isolated gate drivers with an ultra-high CMTI of 300kV/μs
(typ). All devices have integrated digital galvanic isolation with an isolation rating of 3kVRMS in an 8-pin narrow-body
SOIC package, or 5kVRMS in an 8-pin wide-body SOIC package. This family of devices offers high common-mode
transient immunity, high electromagnetic interference (EMI) immunity, and stable temperature performance through
Maxim’s proprietary process technology. The devices feature variants with output options for gate driver common pin
GNDB (MAX22700), Miller clamp (MAX22701), and adjustable UVLO (MAX22702). In addition, variants are offered as
differential inputs INP and INN (D versions) or single-ended input IN with enable EN (E versions). Refer to the Ordering
Information for details.
The MAX22700 has a gate driver common pin (GNDB) that is a reference ground for VDDB and VSSB. VSSB has a
voltage range between -16V and 0V with reference to GNDB. The MAX22701 has an active Miller clamp pin, CLAMP,
which prevents false turn-on of the external power transistor caused by the Miller current. The MAX22702 provides an
adjustable B-side UVLO, offering design flexibility with different types of external power transistors.
All devices support a minimum pulse width of 20ns with maximum pulse-width distortion of 2ns. The part-to-part
propagation delay is matched within 2ns maximum at +25°C ambient temperature, and is guaranteed to be within 5ns
maximum over the temperature range of -40°C to +125°C.
All MAX22700–MAX22702 have a default-low output. The default is the state the output assumes when the input is either
not powered or is open-circuit. The output is set to logic-low when side A or side B supply is in UVLO, the device is in
thermal shutdown, or EN is high (E versions).

Output Driver Stage

The output driver stage of the MAX22700–MAX22702 features a pullup structure and a pulldown structure. The pullup
structure consists of a pMOS transistor and a nMOS transistor in parallel (see the Functional Diagrams). The pMOS
transistor has a maximum RDSON of 4.5Ω. The nMOS transistor only turns on for a short period of time during the output
low-to-high transition and provides a boost current to enable the fast turn-on of the device. The nMOS transistor has a
much lower on-resistance than the pMOS transistor; thus the parallel combination of the nMOS and the pMOS enables
a faster turn-on during the output low-to-high transition.
The pulldown structure of the MAX22700–MAX22702 consists of a nMOS transistor. The nMOS transistor in the
MAX22700 and the MAX22702 has a maximum RDSON of 1.25Ω, while the nMOS in the MAX22701 has an RDSON of
2.5Ω. For the MAX22701, when both OUT and CLAMP pins are connected to the gate of the external power transistor, an
additional nMOS is connected in parallel to the pulldown nMOS transistor to prevent false turn-on of the external power
transistor by providing an additional low-impedance path to VSSB. Refer to Active Miller Clamp (MAX22701 Only) section
and the Functional Diagrams for details.

Digital Isolation
The MAX22700–MAX22702 provide basic galvanic isolation for digital signals transmitted between two ground domains,
and block high-voltage/high-current transients. The devices in the narrow-body SOIC package withstand differences of
up to 3kVRMS for up to 60 seconds, and up to 848VPEAK of continuous isolation. The devices in the wide-body SOIC
package withstand differences of up to 5kVRMS for up to 60 seconds and up to 1200VPEAK of continuous isolation. Refer
to Table 1 for certification information.
The devices have two supply inputs (VDDA and VDDB) that independently set the logic levels on either side of the
device. VDDA and VDDB are referenced to GNDA and VSSB, respectively. Logic input and output levels match the supply
voltages used in the associated power domain. The difference in ground potential between the two power domains can
be as large as VIOWM for extended periods of time and withstand surge voltages up to 5kV. Data transfer integrity is
maintained for a differential ground potential change up to 300kV/μs (typ).

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Table 1. Safety Regulatory Approvals

UL
The MAX22700–MAX22702 are certified under UL1577. For more details, refer to file E351759.
Devices in narrow SOIC package are rated up to 3000VRMS isolation voltage for single protection.
Devices in wide SOIC package are rated up to 5000VRMS isolation voltage for single protection.
cUL (Equivalent to CSA notice 5A)
The MAX22700–MAX22702 are certified up to 3000VRMS (narrow SOIC package) or 5000VRMS (wide SOIC package) for single
protection. For more details, refer to file E351759.
VDE (Pending)
The MAX22700–MAX22702 in wide SOIC are certified to DIN VDE V 0884-11: 2017-1. Basic Insulation, Maximum Transient
Isolation Voltage 7000VPK, Maximum Repetitive Peak Isolation Voltage 1200VPK
Note: These couplers are suitable for “safe electrical insulation” only within the safety ratings. Compliance with the safety
ratings shall be ensured by means of suitable protective circuits.

Unidirectional Channel and Active Pulldown

The MAX22700–MAX22702 have an unidirectional channel that passes data in one direction, as indicated in the
Functional Diagrams. The two internal transistors in the output driver are configured for push-pull operation and feature
an active pulldown function to turn off the external power transistor when either side of the power supply is in UVLO. This
prevents the external power transistor from falsely turning on during startup or UVLO.

INN vs. EN Function

The MAX2270_D features differential PWM inputs (INP and INN). The differential inputs reject input glitches and prevent
false turn-on of the output. The output holds the previous value when a glitch is detected on either input (Figure 3). The
MAX2270_E features a single-ended input (IN) and an active-low input enable (EN). The EN pin allows the output (OUT)
to be quickly set to logic-low, turning off the external power transistor. The output remains at logic-low until the PWM
input (IN) receives a logic-high signal (Figure 4).

H
GLITCH
INP INN LOGIC OUTPUT INP INP L
GLITCH
L L HOLD H
INN L INN
L H L
H L H H FILTERED
OUT OUT L FILTERED
H H HOLD
(a) (b)

H
INP
S INP L
INP
LOGIC
GLITCH
OUTPUT H
INN
INN R INN L
GLITCH
H FILTERED
POR OUT L FILTERED
OUT
(d)
(c)

Figure 3. MAX2270_D Differential Inputs

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

H
GLITCH
IN EN LOGIC OUTPUT IN IN L
GLITCH
L L L H
EN L EN
L H L
H L H H
OUT OUT L FILTERED
H H L OUTPUT TURNS OFF
(a) (b)

H
IN LOGIC
EN OUTPUT IN L
IN
GLITCH
H
EN
EN L
GLITCH
H
OUT L FILTERED
OUT
OUTPUT TURNS OFF
(c) (d)

Figure 4. MAX2270_E Single-Ended Input with Enable

Current sources are used at both A-side inputs to prevent the output from falsely turning on by input glitches or noise.
The INN pin has a weak pullup and the INP has a weak pulldown in the MAX2270_D devices. The EN pin has a weak
pullup and the IN pin has a weak pulldown in the MAX2270_E devices. Refer to Table 2 and Table 3 for the Inputs vs.
Output Truth Tables.
Table 2. MAX2270_D Inputs vs. Output Truth Table
INP INN OUT
Low Low Hold
Low High Low
High Low High
High High Hold

Table 3. MAX2270_E Inputs vs. Output Truth Table

IN EN OUT
Low Low Low
Low High Low (Default)
High Low High
High High Low (Default)

Undervoltage Lockout (UVLO)

The VDDA and VDDB supplies are both internally monitored for undervoltage conditions. Undervoltage events can occur
during power-up, power-down, or during normal operation due to a sagging supply voltage. When an undervoltage
condition is detected on either supply, the output is set to logic-low (default state) to turn off the external power transistor,
regardless of the state of the MAX22700–MAX22702 inputs. The B-side UVLO has an internal filter to reject any VDDB
glitches less than 32μs (typ) (see Figure 9 and Figure 10). Figure 5 through Figure 8 show the behavior of the outputs
during power-up and power-down.

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Figure 5. VDDB Undervoltage Lockout Behavior (Input High) Figure 6. VDDA Undervoltage Lockout Behavior (Input High)

Figure 7. VDDB Undervoltage Lockout Behavior (Input Low) Figure 8. VDDA Undervoltage Lockout Behavior (Input Low)

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Figure 9. VDDB Undervoltage Lockout Glitch Filter, UVLO Not Figure 10. VDDB Undervoltage Lockout Glitch Filter, UVLO
Triggered Triggered

Thermal Shutdown
The MAX22700–MAX22702 operate at an ambient temperature up to +125°C on a properly designed multilayer PCB.
Operating at higher voltages or with heavy output loads increases the junction temperature and power dissipation, and
also reduce the maximum allowable operating temperature. See the Package Information, Absolute Maximum Ratings
and Safety Limits sections for details.
The MAX22700–MAX22702 is in thermal shutdown when the junction temperature of the device exceeds +160°C (typ).
During thermal shutdown, the output is set to logic-low to turn off the external power transistor regardless of the state of
the MAX22700–MAX22702 inputs.

Active Miller Clamp (MAX22701 Only)

The MAX22701 features an active Miller clamp to prevent false turn-on of the external power transistor caused by the
Miller current. When the external high-side transistor is turned on after the external low-side transistor is turned off, the
internal Miller clamp transistor starts to engage when the Miller clamp pin voltage drops below the 2V threshold, and it
provides a low-impedance path to direct the Miller current to VSSB. Refer to Figure 2 for a Miller clamp timing diagram.

Adjustable UVLO (MAX22702 Only)

The MAX22702 features an adjustable B-side UVLO to accommodate UVLO requirements of different types of external
power transistors. To set a user-defined B-side UVLO, connect external resistors between VDDB and ADJ, and between
ADJ and the external power transistor ground so that:
VADJ_UVLO = 2 × (1 + R2 ÷ R1)
where R1 is placed between VDDB and ADJ, and R2 is placed between ADJ and the external power transistor ground
(see Figure 11).
For example, to set the B-side UVLO to 13V, connect 20kΩ (R1) between VDDB and ADJ. R2 is:
(13 ÷ 2 - 1) × 20 = 110kΩ

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

VDDB
VDDA 1nF 68nF 0.1µF 22µF
1nF 0.1µF 1µF

HIGH VOLTAGE

VSSB VSSB VSSB VSSB

VDDA MAX22702 VDDB

INP/IN UVLO,
UVLO CONTROL
AND LOGIC, OUT
LOGIC AND
INN/EN INPUTS OUTPUT VDDB
DRIVER
VSSB
GNDA R1
VSSB
ADJ

R2

GNDB

NOTE: VDDB AND VSSB ARE REFERENCED TO GNDB. VDDB - VADJ < 5V (TYP)

Figure 11. Example Circuit for MAX22702 Adjustable UVLO

Safety Limits
Damage to the IC can result in a low-resistance path to ground or to the supply and, without current limiting, the
MAX22700–MAX22702 could dissipate excessive amounts of power. Excessive power dissipation can damage the die
and result in damage to the isolation barrier, potentially causing long-term reliability issues. Table 4 shows the safety
limits for the MAX22700–MAX22702.
The maximum safety temperature (TS) for the device is the +150°C maximum junction temperature specified in the
Absolute Maximum Ratings. The power dissipation (PD) and junction-to-ambient thermal impedance (θJA) determine the
junction temperature. Thermal impedance values (θJA and θJC) are available in the Package Information section of the
data sheet and power dissipation calculations are discussed in the Calculating Power Dissipation section. Calculate the
junction temperature (TJ) as:
TJ = TA + (PD × θJA)
Figure 12 to Figure 14 show the thermal derating curves for safety limiting the power and the current of the devices.
Ensure that the junction temperature does not exceed +150°C.
Table 4. Safety Limiting Values for the MAX22700–MAX22702
PARAMETER SYMBOL TEST CONDITIONS MAX UNIT
TJ = 150°C, TA = 25°C, VDDB = 28V 38 mA
Safety Operating Current on B- IN = Low, OUT = VDDB,
IOUT
Side Pins OUT = Low during thermal VDDB = 20V 53 mA
shutdown
Safety Current on Any Pins
IS TJ = 150°C, TA = 25°C 300 mA
(No Damage to Isolation Barrier)
8 Narrow SOIC 1173
Total Safety Power Dissipation PS TJ = 150°C, TA = 25°C mW
8 Wide SOIC 1064
Maximum Safety Temperature TS 150 °C

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Figure 12. Thermal Derating Curve for Safety Power Limiting (8 Figure 13. Thermal Derating Curve for Safety Power Limiting (8
Narrow SOIC) Wide SOIC)

Figure 14. Thermal Derating Curve for Safety Current Limiting

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Applications Information
Power-Supply Sequencing
The MAX22700–MAX22702 do not require special power-supply sequencing. The logic levels are set independently on
either side by VDDA and VDDB. Each supply can be present over the entire specified range regardless of the level or
presence of the other supply.

Power-Supply Decoupling
To reduce ripple and the chance of introducing data errors, bypass VDDA and VDDB with 1nF, 0.1μF, and 1μF low-ESR
and low-ESL ceramic capacitors with sufficient voltage rating in parallel to GNDA and VSSB, respectively. To ensure the
best performance, place the decoupling capacitors as close to the power-supply pins as possible.
On the B side, it is recommended to place the 1nF and 1μF capacitors close to the VSSB pin, and place the 0.1μF
capacitor close to the VDDB pin. To further reduce supply ripple while operating at higher supply voltage and data rates,
place a 68nF 1206 C0G/NP0 capacitor across the VDDB pin and VSSB pin as close to the pins as possible. It is also
recommended to include a 22μF reservoir capacitor (tantalum or electrolytic type) between VDDB and VSSB in case the
VDDB power supply is located far away from the VDDB pin. All bypass capacitors on VDDB are required to have at least
a 50V voltage rating.

Layout Considerations
The PCB designer should follow some critical recommendations in order to get the best performance from the design.
● Keep the input/output traces as short as possible. To maintain low signal-path inductance, avoid using vias.
● Place the gate driver as close to the external power transistor as possible to decrease the trace inductance and avoid
output ringing.
● Have a solid ground plane underneath the high-speed signal layer.
● Keep the area underneath the MAX22700–MAX22702 free from ground and signal planes. Any galvanic or metallic
connection between side A and side B defeats the isolation.
● Have a solid ground plane next to VSSB pin with multiple VSSB vias to reduce the parasitic inductance and minimize
the ringing on the output signal.
● Place a 68nF 1206 C0G/NP0 bypass capacitor across pin 5 and pin 8 as close as possible to the pins to mitigate
B-side supply ripple.

Calculating Power Dissipation

The required current for the A side of the MAX22700–MAX22702 depends on the VDDA supply voltage and the data rate.
The required current for the B side of the MAX22700–MAX22702 depends on the VDDB supply voltage, the data rate,
and the load condition. The typical current for different VDDA and VDDB supply voltages at any data rate without external
load can be estimated from the graphs in Figure 15 and Figure 16. Please note that the data in Figure 15 and Figure 16
are extrapolated from supply current measurements in a typical operating condition.
The total current for the B side is the sum of the “no load” current (shown in Figure 16) which is a function of the voltage
and the data rate, and the “load current”, which depends on the load impedance. Current into a capacitive load is a
function of the load capacitance, the switching frequency, and the supply voltage.
ICL = CL × fSW × VDDB
where:
ICL = Current required to drive the capacitive load.
CL = Load capacitance on the output pin.
fSW = Switching frequency in Hz.
VDDB = B-side supply voltage.
The total power dissipation (PD) can be calculated as:
PD = VDDA × IDDA + VDDB × IDDB

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

where IDDA is the A-side supply current and IDDB is the B-side supply current.
Example: A MAX22701 is operating with VDDA = 5V, VDDB = 20V. The output is operating at 10kHz with 1nF capacitive
load. VDDA must supply about 4.56mA with a 10kHz data rate and a 5V supply voltage according to Figure 15. VDDB
must supply the sum of the no load current and the load current. The no load current is about 3.77mA with a 10kHz data
rate and a 20V supply voltage according to Figure 16. The load current is equal to 1nF × 10kHz × 20V = 0.2mA. VDDB
must therefore supply about 3.97mA. The total power dissipation is 5V × 4.56mA + 20V × 3.97mA = 102.2mW.

Figure 15. VDDA Supply Current vs. Data Rate (typ) Figure 16. VDDB Supply Current vs. Data Rate (typ)

Gate Driver Output Resistors

External series resistors (RON and ROFF) between the MAX22700–MAX22702 output and the gate of the power
transistor are required in gate driver applications. These resistors control the turn-on and turn-off time of the power
transistor to optimize switching efficiency and EMI performance.
The RON resistance and external FET’s gate capacitance determine the turn-on time. The parallel combination of
both RON and ROFF resistance and the external FET’s gate capacitance determine the turn-off time. Turn-off time is
usually much faster than turn-on time to avoid shoot-through. Figure 17 shows a typical RON and ROFF network for the
MAX22700–MAX22702. RON and ROFF values should be adjusted based on the required slew rate and the external
FET’s gate capacitance.
The gate driver output resistors also help limit ringing caused by parasitic inductances and capacitances due to PCB
layout and device package leads. Output ringing can happen during high voltage dV/dt and high current di/dt switching.
Increasing RON and ROFF can help reduce the ringing.

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

VDDA VDDB
1nF 0.1µF 1µF 1nF 68nF 0.1µF 22µF

HIGH VOLTAGE

MAX22700–MAX22702 VSSB VSSB VSSB VSSB

VDDA VDDB

INP/IN UVLO,
RON
UVLO CONTROL
AND LOGIC, OUT
LOGIC AND
INN/EN INPUTS OUTPUT
DRIVER ROFF
VSSB
GNDA
VSSB
GNDB/CLAMP/ADJ

GNDB

Figure 17. Typical Gate Driver Output Network with RON and ROFF

Driving GaN Transistors

The high CMTI rating of 300kV/μs (typ) and the propagation delay matching of 5ns (max) between the high-side and low-
side drivers make the MAX22701 and MAX22702 ideal to drive GaN devices. The MAX22702 also features an adjustable
B-side UVLO to accommodate the low gate drive voltage of GaN devices.
As shown in the Typical Application Circuits, a positive supply (VDDB) and a negative supply (VSSB) with reference to
GNDB are required to meet the gate voltage requirement of GaN devices when using the MAX22701 and MAX22702
as GaN gate drivers. A boost current is required during the GaN device’s turn-on period; hence a capacitor is placed in
series with one of the resistors at the output. This capacitor needs to be discharged during the turn-off period. Therefore,
a diode is placed in parallel to the resistor to provide a discharge path. On the layout, it is recommended to place the gate
driver very close to the GaN device to minimize series inductance and reduce gate drive loop area. To prevent ringing
and support high peak currents when turning on GaN devices, good decoupling is required on the VDDB and VSSB pins.

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Application Circuits

MAX22700D

HIGH-SIDE POSITIVE SUPPLY

5V VDDB1
1nF 0.1µF 1µF 1nF 68nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1 VSSB1
VDDA MAX22700D VDDB
VDDA

INP UVLO,
PWMH
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
INN INPUTS OUTPUT
PWMH DRIVER

VSSB HIGH-SIDE
GNDA
GNDA VSSB1 NEGATIVE SUPPLY
GNDB

HIGH-SIDE SUPPLY GROUND OUTPUT

1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 68nF 0.1µF 22µF

VDDA MAX22700D VDDB

VSSB2 VSSB2 VSSB2 VSSB2

INP UVLO,
PWML
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
INN INPUTS OUTPUT
PWML DRIVER
VSSB
LOW-SIDE
GNDA
VSSB2 NEGATIVE SUPPLY
GNDB
LOW-SIDE SUPPLY GROUND
GNDA

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Application Circuits (continued)

MAX22700E

HIGH-SIDE POSITIVE SUPPLY

5V VDDB1
1nF 0.1µF 1µF 1nF 68nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1 VSSB1
VDDA MAX22700E VDDB
VDDA

IN UVLO,
PWMH
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
EN INPUTS OUTPUT
PWML DRIVER

VSSB HIGH-SIDE
GNDA
GNDA VSSB1 NEGATIVE SUPPLY
GNDB

HIGH-SIDE SUPPLY GROUND OUTPUT

1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 68nF 0.1µF 22µF

VDDA MAX22700E VDDB

VSSB2 VSSB2 VSSB2 VSSB2

IN UVLO,
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
EN INPUTS OUTPUT
DRIVER
VSSB
LOW-SIDE
GNDA
VSSB2 NEGATIVE SUPPLY
GNDB
LOW-SIDE SUPPLY GROUND

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Application Circuits (continued)

MAX22701D

HIGH-SIDE POSITIVE SUPPLY

5V VDDB1
1nF 0.1µF 1µF 1nF 68nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1 VSSB1
VDDA MAX22701D VDDB
VDDA

INP UVLO,
PWMH
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
INN INPUTS OUTPUT
PWMH DRIVER
VSSB
GNDA
GNDA
CLAMP
2V

VSSB
HIGH-SIDE
VSSB1 NEGATIVE SUPPLY OUTPUT
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 68nF 0.1µF 22µF

VDDA MAX22701D VDDB

VSSB2 VSSB2 VSSB2 VSSB2

INP UVLO,
PWML
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
INN INPUTS OUTPUT
PWML DRIVER
VSSB
GNDA
CLAMP
2V
GNDA
VSSB
LOW-SIDE
VSSB2 NEGATIVE SUPPLY

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Application Circuits (continued)

MAX22701E

HIGH-SIDE POSITIVE SUPPLY

5V VDDB1
1nF 0.1µF 1µF 1nF 68nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1 VSSB1
VDDA MAX22701E VDDB
VDDA

IN UVLO,
PWMH
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
EN INPUTS OUTPUT
PWML DRIVER
VSSB
GNDA
GNDA
CLAMP
2V

VSSB
HIGH-SIDE
VSSB1 NEGATIVE SUPPLY OUTPUT
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 68nF 0.1µF 22µF

VDDA MAX22701E VDDB

VSSB2 VSSB2 VSSB2 VSSB2

IN UVLO,
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
EN INPUTS OUTPUT
DRIVER
VSSB
GNDA
CLAMP
2V
GNDA
VSSB
LOW-SIDE
VSSB2 NEGATIVE SUPPLY

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Application Circuits (continued)

MAX22702D

HIGH-SIDE POSITIVE SUPPLY

5V VDDB1
1nF 0.1µF 1µF 1nF 68nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1 VSSB1
VDDA MAX22702D VDDB
VDDA

INP UVLO,
PWMH
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
INN INPUTS OUTPUT VDDB1
PWMH DRIVER
VSSB HIGH-SIDE
NEGATIVE
GNDA R1
GNDA VSSB1 SUPPLY
ADJ

R2
1nF 0.1µF 1µF OUTPUT
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 68nF 0.1µF 22µF GNDB1

VDDA MAX22702D VDDB

VSSB2 VSSB2 VSSB2 VSSB2

INP UVLO,
PWML
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
INN INPUTS OUTPUT VDDB2
PWML DRIVER
VSSB LOW-SIDE
NEGATIVE
GNDA R1
VSSB2 SUPPLY
ADJ

GNDA R2

GNDB2

NOTE: VDDB AND VSSB ARE REFERENCED TO GNDB. VDDB - VADJ < 5V (TYP)

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MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Application Circuits (continued)

MAX22702E

HIGH-SIDE POSITIVE SUPPLY

5V VDDB1
1nF 0.1µF 1µF 1nF 68nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1 VSSB1
VDDA MAX22702E VDDB
VDDA

IN UVLO,
PWMH
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
EN INPUTS OUTPUT VDDB1
PWML DRIVER
VSSB HIGH-SIDE
NEGATIVE
GNDA R1
GNDA VSSB1 SUPPLY
ADJ

R2
1nF 0.1µF 1µF LOW-SIDE POSITIVE SUPPLY OUTPUT
VDDB2
1nF 68nF 0.1µF 22µF GNDB1

VDDA MAX22702E VDDB

VSSB2 VSSB2 VSSB2 VSSB2

IN UVLO,
UVLO CONTROL
AND LOGIC, OUT
SiC
LOGIC AND
EN INPUTS OUTPUT VDDB2
DRIVER
VSSB LOW-SIDE
NEGATIVE
GNDA R1
VSSB2 SUPPLY
ADJ

GNDA R2

GNDB2

NOTE: VDDB AND VSSB ARE REFERENCED TO GNDB. VDDB - VADJ < 5V (TYP)

www.analog.com Analog Devices | 31

MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Application Circuits (continued)

MAX22701D as GaN Gate Driver

HIGH-SIDE POSITIVE SUPPLY

5V VDDB1
1nF 0.1µF 1µF 1nF 68nF 0.1µF 22µF

HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1 VSSB1
VDDA MAX22701D VDDB
VDDA

INP UVLO,
PWMH
UVLO CONTROL
AND LOGIC, OUT GaN
LOGIC AND (PANASONIC)
INN INPUTS OUTPUT
PWMH DRIVER
GNDB1
VSSB HIGH-SIDE
GNDA
GNDA COMMON
CLAMP
2V GROUND

VSSB
HIGH-SIDE
VSSB1 NEGATIVE SUPPLY OUTPUT
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 68nF 0.1µF 22µF

VDDA MAX22701D VDDB

VSSB2 VSSB2 VSSB2 VSSB2

INP UVLO,
PWML
UVLO CONTROL
AND LOGIC, OUT GaN
LOGIC AND (PANASONIC)
INN INPUTS OUTPUT
PWML DRIVER
GNDB2
VSSB LOW-SIDE
GNDA GNDA
COMMON
CLAMP
2V GROUND

VSSB
LOW-SIDE
VSSB2 NEGATIVE SUPPLY

www.analog.com Analog Devices | 32

MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Typical Application Circuits (continued)

MAX22702E as GaN Gate Driver

HIGH-SIDE POSITIVE SUPPLY

5V VDDB1
1nF 0.1µF 1µF 1nF 68nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1 VSSB1
VDDA MAX22702E VDDB
VDDA

IN UVLO,
PWMH
UVLO CONTROL
AND LOGIC, OUT
GaN
LOGIC AND
EN INPUTS OUTPUT
PWML DRIVER VDDB1
VSSB HIGH-SIDE GNDB1
NEGATIVE HIGH-SIDE
GNDA
GNDA VSSB1 SUPPLY COMMON
ADJ
GROUND

LOW-SIDE POSITIVE SUPPLY OUTPUT

1nF 0.1µF 1µF
VDDB2
1nF 68nF 0.1µF 22µF GNDB1

VDDA MAX22702E VDDB

VSSB2 VSSB2 VSSB2 VSSB2

IN UVLO,
UVLO CONTROL
AND LOGIC, OUT
GaN
LOGIC AND
EN INPUTS OUTPUT
DRIVER VDDB2
VSSB GNDB2
LOW-SIDE
GNDA NEGATIVE LOW-SIDE
VSSB2 SUPPLY COMMON
ADJ
GROUND
GNDA

GNDB2

NOTE: VDDB AND VSSB ARE REFERENCED TO GNDB. VDDB - VADJ < 5V (TYP)

www.analog.com Analog Devices | 33

MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Ordering Information
LOW-
SIDE ISOLATION TEMP
PART NUMBER INPUTS PIN 7 UVLO PIN-PACKAGE
RDSON VOLTAGE (kVRMS) RANGE (°C)
(Ω)
Differential,
MAX22700DASA+ GNDB 13V to GNDB 1.25 3 -40 to +125 8 Narrow SOIC
INP and INN
Differential,
MAX22700DAWA+* GNDB 13V to GNDB 1.25 5 -40 to +125 8 Wide SOIC
INP and INN
Single-Ended,
MAX22700EASA+ GNDB 13V to GNDB 1.25 3 -40 to +125 8 Narrow SOIC
IN and EN
Single-Ended,
MAX22700EAWA+* GNDB 13V to GNDB 1.25 5 -40 to +125 8 Wide SOIC
IN and EN
Differential,
MAX22701DASA+ CLAMP 13V to VSSB 2.5 3 -40 to +125 8 Narrow SOIC
INP and INN
Differential,
MAX22701DAWA+ CLAMP 13V to VSSB 2.5 5 -40 to +125 8 Wide SOIC
INP and INN
Single-Ended,
MAX22701EASA+ CLAMP 13V to VSSB 2.5 3 -40 to +125 8 Narrow SOIC
IN and EN
Single-Ended,
MAX22701EAWA+ CLAMP 13V to VSSB 2.5 5 -40 to +125 8 Wide SOIC
IN and EN
Differential,
MAX22702DASA+ ADJ Adjustable 1.25 3 -40 to +125 8 Narrow SOIC
INP and INN
Differential,
MAX22702DAWA+ ADJ Adjustable 1.25 5 -40 to +125 8 Wide SOIC
INP and INN
Single-Ended,
MAX22702EASA+ ADJ Adjustable 1.25 3 -40 to +125 8 Narrow SOIC
IN and EN
Single-Ended,
MAX22702EAWA+* ADJ Adjustable 1.25 5 -40 to +125 8 Wide SOIC
IN and EN
+Denotes a lead (Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.

www.analog.com Analog Devices | 34

MAX22700D–MAX22702D Ultra-High CMTI Isolated Gate Drivers
MAX22700E–MAX22702E

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 7/19 Initial release —
Updated the Absolute Maximum Ratings and Package Information sections, Table 2, and
1 8/19 2, 7
Figure 1
Updated the General Description, Benefits and Features, DC Electrical Characteristics, and
2 9/19 1, 4
Dynamic Characteristics sections
Removed future product designation from MAX22702EASA+ in the Ordering Information
3 1/20 29
section
Removed future product designation from MAX22700DASA+ and MAX22701DASA+ in the
4 5/20 29
Ordering Information section
5 7/20 Updated the Benefits and Features and Digital Isolation sections; updated Table 1 1, 6, 15
Removed future product designation from MAX22700EASA+ and MAX22702DASA+ in the
6 10/20 29
Ordering Information section
Updated the General Description, Benefit and Features, Safety Regulatory Approvals
(Pending), Absolute Maximum Ratings, Package Information, Electrical Characteristics, Pin
Configurations, Pin Description, Detailed Description, Digital Isolation, and Safety Limits 1–3, 8–9,
sections; added the Insulation Characteristics—8 Wide SOIC table and new Figure 1–2 and 13–16,
7 10/20
renumbered remaining figures; moved the Functional Diagrams to the second page;
updated Figures 12–13, Table 1, and Table 4; added MAX22700DAWA+, 17–24, 36
MAX22700EAWA+, MAX22701DAWA+, MAX22701EAWA+, MAX22702DAWA+, and
MAX22702EAWA+ as future products to the Ordering Information table
Updated the General Description, Safety Regulatory Approvals, Electrical Characteristics,
1, 4, 7–8,
Insulation Characteristics—8 Narrow SOIC, Insulation Characteristics—8 Wide SOIC,
10–12, 17,
8 4/21 Typical Operating Characteristics, Power-Supply Decoupling, Layout Considerations, and
19, 21,
Typical Application Circuit sections; updated Table 1, Table 4, Figures 5–6, 8, 11, 16–17,
24–34
and TOC01–TOC08, TOC15–TOC16, and TOC 18
Removed future product designation from MAX22701EAWA+ in the Ordering Information
9 6/21 34
section
Removed future product designation from MAX22701DAWA+ in the Ordering Information
10 4/22 34
section
Removed future product designation from MAX22702DAWA+ in the Ordering Information
11 7/22 34
section

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