EC15-1503

EMBEDDED SYSTEM

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• Syllabus

• Reference
Shibu K V , Introduction to embedded systems, Tata Mcgraw Hill,
(2009)

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EMBEDDED SYSTEM?
• An embedded system is an electro-mechanical system designed to perform a
specific function and is a combination of both hardware and firmware.
(software).

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Examples : In household
appliances,
telecommunications,
medical equipment,
industrial control ,
consumer products etc.

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Classification of Embedded Systems
• Based on generation

• Complexity and performance requirements

• Based on deterministic behaviour

• Based on triggering

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Core of the Embedded System
• General Purpose and domain specific processors
• Microprocessors
• Microcontrollers
• Digital Signal Processors
• Application Specific Integrated Circuits (ASICs)
• Programmable Logic devices (PLDs)
• Commercial off-the-shelf Components (COTS)

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Microprocessor
• First microprocessor Intel 4004.

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Digital Signal Processors
• A DSP takes real world signals and manipulate them.
• 2-3 times faster than microprocessors.
• Contains the following units:-

• Program memory
• Data Memory
• Computational Engine
• I/O Unit

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 EC 15-1503
EMBEDDED SYSTEMS

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Reference

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Oversimplified architectural overview of the
8051 family

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Block
diagram of
the 8051
family

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Notes of
8051 block
diagram

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Pin
diagram
of 8051

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 EC 15-1503
EMBEDDED SYSTEMS (Lecture 4)
Reference

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 Overview

• Internal and External Memories

• Internal program memory
• Internal data memory
• Internal memory for registers and bits
• External program memory
• External data memory

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Internal program
memory
• When the EA is 1 at the
reset , the PC starts from
0x0000 and accesses the
internal addresses from the
memory.
• Memory addresses are
between 0x0000 and
0x0FFF for 4kB of codes.
• Code memory area can be
considered as consisting of
32 banks, each of 2kB in
the classical 8051.

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External Program Memory

• Memory addresses are

between 0x0000 and 0xFFFF
for 64 kB of codes.
• When the EA is 0, at RESET ,
the PC starts from 0x0000 and
accesses the external addresses
from the memory.
• When the EA is 1, at RESET ,
the PC starts from 0x0000 and
accesses the internal addresses
and the 0x1000 onwards from
the external addresses from
the memory.

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Internal Data Memory
(Internal RAM)

• SFRs are between 0x80 and

0xFF. Several SFR bytes
(ports) are also used for bit
operations with Boolean
processor.
• Internal RAM data is between
0x00-0x7F ,has 128 bytes that
is accessible by the address
indirectly pointed by R0 and
R1 in an instruction or directly
pointed address in an
instruction.

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Internal Data Memory
(Internal RAM)
• 0x00- 0x1F – 32 bytes ,4 register sets. They are not used for bit
operations.
• 0x20-0x2F – 16 bytes, 128 bits which are also used for bit operations.
• 0x30-0x7F – 80 bytes, only byte addressable

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 Internal IDATA RAM.
• IDATA – Indirectly
addressed data
• Almost all
modern variants
of 8051 has 256
bytes of internal
RAM.

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External Data Memory
(RAM)

• Figure shows layout of

the external data
(abbreviated as X-data)
memory addresses in
the 8051 architecture.
• It can be accessed
through the indirect
addressing mode used (
for example , when the
DPTR is used) in an
instruction.
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Interfacing of the external memories in Intel
8051
• External Memories are interfaced using four control pins ( PSEN,
ALE, RD, and WR) and AD-AD7 at P0 and A8-A15 at P2.
• ALE signal separates A0-A7 bus for the program and data memories.
A latch of 8 bits is used for this purpose.
• PSEN signal when 0 uses the program memory code bank 2 to 31 for
the code reading operation.

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Interfacing of the external memories in Intel
8051
• The RD when 0, uses data memory for the data-read operation.
• The WR when 0, uses data memory for the data-write operation.
• When PSEN and RD are short-circuited , the program memory and
data memory areas overlap. We can place both code and data in the
unified space.

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Interfacing circuit and
the clock states

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To conclude ,
• 8051 has a internal program memory (ROM) of 4KB.
• External program memory of 64KB.
• Almost all modern variants of 8051 has 256 bytes of internal data
Memory (RAM).
• External data memory of 64KB.
• External Memories are interfaced using four control pins ( PSEN,
ALE, RD, and WR) and AD-AD7 at P0 and A8-A15 at P2.

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INSTRUCTION SYNTAX.
General syntax for 8051 assembly language is as follows.
LABEL: OPCODE OPERAND; COMMENT

LABEL: (THIS IS NOT NECESSARY UNLESS THAT SPECIFIC LINE HAS TO BE

ADDRESSED). The label is a symbolic address for the instruction. When the program is
assembled, the label will be given specific address in which that instruction is stored. Unless
that specific line of instruction is needed by a branching instruction in the program, it is not
necessary to label that line.
OPCODE: Opcode is the symbolic representation of the operation. The assembler converts
the opcode to a unique binary code (machine language).
OPERAND: While opcode specifies what operation to perform, operand specifies where to
perform that action. The operand field generally contains the source and destination of the
data. In some cases, only source or destination will be available instead of both. The operand
will be either address of the data, or data itself.
COMMENT: Always comment will begin with; or // symbol. To improve the program
quality, programmer may always use comments in the program.
Eg: ADD A, #83 // # Symbol indicates the data is immediate.

1. Write a program to add the values of locations 50H and 51H and store the result in
locations in 52h and 53H.

ORG 0000H; Set program counter 0000H

MOV A,50H; Load the contents of Memory location 50H into A
ADD A,51H; Add the contents of memory 51H with CONTENTS A
MOV 52H, A; Save the LS byte of the result in 52H
MOV A, #00; Load 00H into A
ADDC A, #00; Add the immediate data and carry to A
MOV 53H, A; Save the MS byte of the result in location 53h END

ADDRESSING MODES
Various methods of accessing the data are called addressing modes.
8051 addressing modes are classified as follows.
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Long addressing.
8. Indexed addressing.
9. Bit inherent addressing.
10. Bit direct addressing.

1. Immediate addressing. In this addressing mode the data is provided as a part of

instruction itself. In other words, data immediately follows the instruction.
Eg. MOV A, #30H
ADD A, #83 # Symbol indicates the data is immediate.
2. Register addressing.
In this addressing mode the register will hold the data. One of the eight general registers (R0
to R7) can be used and specified as the operand.
Eg. MOV A,R0
ADD A,R6
R0 – R7 will be selected from the current selection of register bank. The default register bank
will be bank 0.
3. Direct addressing
There are two ways to access the internal memory. Using direct address and indirect address.
Using direct addressing mode we can not only address the internal memory but SFRs also. In
direct addressing, an 8 bit internal data memory address is specified as part of the instruction
and hence, it can specify the address only in the range of 00H to FFH. In this addressing
mode, data is obtained directly from the memory.
Eg. MOV A,60h
ADD A,30h
4. Indirect addressing
The indirect addressing mode uses a register to hold the actual address that will be used in
data movement. Registers R0 and R1 and DPTR are the only registers that can be used as
data pointers. Indirect addressing cannot be used to refer to SFR registers. Both R0 and R1
can hold 8-bit address and DPTR can hold 16-bit address.
Eg. MOV A, @R0
ADD A, @R1
MOVX A, @DPTR
5. Indexed addressing.
In indexed addressing, either the program counter (PC), or the data pointer (DTPR)—is used
to hold the base address, and the A is used to hold the offset address. Adding the value of the
base address to the value of the offset address forms the effective address. Indexed addressing
is used with JMP or MOVC instructions. Look up tables are easily implemented with the help
of index addressing.
Eg. MOVC A, @A+DPTR // copies the contents of memory location pointed by the sum of
the accumulator A and the DPTR into accumulator A.
MOVC A, @A+PC // copies the contents of memory location pointed by the sum of the
accumulator A and the program counter into accumulator A.

6. Relative Addressing.
Relative addressing is used only with conditional jump instructions. The relative address,
(offset), is an 8 bit signed number, which is automatically added to the PC to make the
address of the next instruction. The 8 bit signed offset value gives an address range of +127
to —128 locations. The jump destination is usually specified using a label and the assembler
calculates the jump offset accordingly. The advantage of relative addressing is that the
program code is easy to relocate and the address is relative to position in the memory.
Eg. SJMP LOOP1
JC BACK
7. Absolute addressing
Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute Call)
instructions. These are 2 bytes instructions. The absolute addressing mode specifies the
lowest 11 bit of the memory address as part of the instruction. The upper 5 bit of the
destination address are within the current 2 Kbyte page of the program memory.
Eg. AJMP LOOP1
ACALL LOOP2
8. Long Addressing
The long addressing mode is used with the instructions LJMP and LCALL. These are 3-byte
instructions. The address specifies a full 16-bit destination address so that a jump or a call can
be made to a location within a 64 Kbyte code memory space.
Eg. LJMP FINISH
LCALL DELAY
9. Bit Inherent Addressing
In this addressing, the address of the flag which contains the operand, is implied in the
opcode of the instruction.
Eg. CLR C; Clears the carry flag to 0
10. Bit Direct Addressing
In this addressing mode the direct address of the bit is specified in the instruction. The RAM
space 20H to 2FH and most of the special function registers are bit addressable. Bit address
values are between 00H to 7FH.
Eg. CLR 07h; Clears the bit 7 of 20h RAM space
SETB 07H; Sets the bit 7 of 20H RAM space.
INSTRUCTION SET.
The 8051 internal operations and external read/write operations are controlled by the
oscillator clock. T-state, Machine cycle and Instruction cycle are terms used in instruction
timings.

T-state is defined as one subdivision of the operation performed in one clock period.
The terms 'Tstate' and 'clock period' are often used synonymously.
Machine cycle is defined as 12 oscillator periods. A machine cycle consists of six
states and each state lasts for two oscillator periods. An instruction takes one to four
machine cycles to execute an instruction.
Instruction cycle is defined as the time required for completing the execution of an
instruction. The 8051-instruction cycle consists of one to four machine cycles.
Eg. If 8051 microcontrollers are operated with 12 MHz oscillator, find the execution
time for the following four instructions.
1. ADD A, 45H.
2. SUBB A, #55H
3. MOV DPTR, #2000H
4. MUL AB
Since the oscillator frequency is 12 MHz, the clock period is, Clock period = 1/12
MHz = 0.08333 µS. Time for 1 machine cycle = 0.08333 µS x 12 =1 µS.
8051 Instructions
The instructions of 8051 can be broadly classified under the following headings.
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Subroutine instructions
6. Bit manipulation instructions
Data transfer instructions.
In this group, the instructions perform data transfer operations of the following types.
a. Move the contents of a register Rn to A
i. MOV A, R
ii. MOV A, R7
b. Move the contents of a register A to Rn
i. MOV R4,A
ii. MOV R1,A
c. Move an immediate 8 bit data to register A or to Rn or to a memory location(direct or
indirect)
i. MOV A, #45H
ii. MOV R6, #51H
iii. MOV 30H, #44H
iv. MOV @R0, #0E8H
v. MOV DPTR, #0F5A2H
vi. MOV DPTR, #5467H
d. Move the contents of a memory location to A or A to a memory location using direct
and indirect addressing
i. MOV A, 65H
ii. MOV A, @R0
iii. MOV 45H, A
iv. MOV @R1, A
e. Move the contents of a memory location to Rn or Rn to a memory location using
direct addressing
i. MOV R3, 65H
ii. MOV 45H, R2
f. Move the contents of memory location to another memory location using direct and
indirect addressing
i. MOV 47H, 65H
ii. MOV 45H, @R0
g. Move the contents of an external memory to A or A to an external memory
i. MOVX A, @R1
ii. MOVX @R0, A
iii. MOVX A, @DPTR
iv. MOVX @DPTR, A
h. Move the contents of program memory to A
i. MOVC A, @A+PC
ii. MOVC A, @A+DPTR

i. Push and Pop instructions

[SP]=07 //CONTENT OF SP IS 07 (DEFAULT VALUE)
MOV R6, #25H [R6] =25H //CONTENT OF R6 IS 25H
MOV R1, #12H [R1] =12H //CONTENT OF R1 IS 12H
MOV R4, #0F3H [R4] =F3H //CONTENT OF R4 IS F3H
PUSH 6 [SP]=08 [08]=[06]=25H//CONTENT OF 08 IS 25H
PUSH 1 [SP]=09 [09]=[01]=12H //CONTENT OF 09 IS 12H
PUSH 4 [SP]=0A [0A]=[04]=F3H //CONTENT OF 0A IS F3H
POP 6 [06]=[0A]=F3H [SP]=09 //CONTENT OF 06 IS F3H
POP 1 [01]=[09]=12H [SP]=08 //CONTENT OF 01 IS 12H
POP 4 [04]=[08]=25H [SP]=07 //CONTENT OF 04 IS 25H

j. Exchange instructions
The content of source ie., register, direct memory or indirect memory will be exchanged with
the contents of destination ie., accumulator.
i. XCH A,R3
ii. XCH A,@R1
iii. XCH A,54h
k. Exchange digit. Exchange the lower order nibble of Accumulator (A0-A3) with lower
order nibble of the internal RAM location which is indirectly addressed by the register.
i. XCHD A,@R1
ii. XCHD A,@R0

Examples
1. Load the external memory address pointer DPTR with 0x1000. Show an
alternate solution in which 8 bit operands are used.

2. How can a byte be transferred from the address pointed by R0 to the register
R2? There is no MOV @Ri, Rn instruction available.

3. Assuming PC to be 1000H, transfer the code at 1000H to the internal RAM

at 70H.

4. Using DPTR, transfer the codes from 1000H and 10001H to addresses 7EH
and 7FH in RAM.
5. Using DPTR, transfer the codes from 1000H and 10001H to external data
memory addresses 1000H and 1001H.

6. Assume that R0 to R7 have the array values in the ascending order.

Rearrange these in the descending order.
INSTRUCTION SYNTAX.
General syntax for 8051 assembly language is as follows.
LABEL: OPCODE OPERAND; COMMENT

LABEL: (THIS IS NOT NECESSARY UNLESS THAT SPECIFIC LINE HAS TO BE

ADDRESSED). The label is a symbolic address for the instruction. When the program is
assembled, the label will be given specific address in which that instruction is stored. Unless
that specific line of instruction is needed by a branching instruction in the program, it is not
necessary to label that line.
OPCODE: Opcode is the symbolic representation of the operation. The assembler converts
the opcode to a unique binary code (machine language).
OPERAND: While opcode specifies what operation to perform, operand specifies where to
perform that action. The operand field generally contains the source and destination of the
data. In some cases, only source or destination will be available instead of both. The operand
will be either address of the data, or data itself.
COMMENT: Always comment will begin with; or // symbol. To improve the program
quality, programmer may always use comments in the program.
Eg: ADD A, #83 // # Symbol indicates the data is immediate.

1. Write a program to add the values of locations 50H and 51H and store the result in
locations in 52h and 53H.

ORG 0000H; Set program counter 0000H

MOV A,50H; Load the contents of Memory location 50H into A
ADD A,51H; Add the contents of memory 51H with CONTENTS A
MOV 52H, A; Save the LS byte of the result in 52H
MOV A, #00; Load 00H into A
ADDC A, #00; Add the immediate data and carry to A
MOV 53H, A; Save the MS byte of the result in location 53h END

ADDRESSING MODES
Various methods of accessing the data are called addressing modes.
8051 addressing modes are classified as follows.
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Long addressing.
8. Indexed addressing.
9. Bit inherent addressing.
10. Bit direct addressing.

1. Immediate addressing. In this addressing mode the data is provided as a part of

instruction itself. In other words, data immediately follows the instruction.
Eg. MOV A, #30H
ADD A, #83 # Symbol indicates the data is immediate.
2. Register addressing.
In this addressing mode the register will hold the data. One of the eight general registers (R0
to R7) can be used and specified as the operand.
Eg. MOV A,R0
ADD A,R6
R0 – R7 will be selected from the current selection of register bank. The default register bank
will be bank 0.
3. Direct addressing
There are two ways to access the internal memory. Using direct address and indirect address.
Using direct addressing mode we can not only address the internal memory but SFRs also. In
direct addressing, an 8 bit internal data memory address is specified as part of the instruction
and hence, it can specify the address only in the range of 00H to FFH. In this addressing
mode, data is obtained directly from the memory.
Eg. MOV A,60h
ADD A,30h
4. Indirect addressing
The indirect addressing mode uses a register to hold the actual address that will be used in
data movement. Registers R0 and R1 and DPTR are the only registers that can be used as
data pointers. Indirect addressing cannot be used to refer to SFR registers. Both R0 and R1
can hold 8-bit address and DPTR can hold 16-bit address.
Eg. MOV A, @R0
ADD A, @R1
MOVX A, @DPTR
5. Indexed addressing.
In indexed addressing, either the program counter (PC), or the data pointer (DTPR)—is used
to hold the base address, and the A is used to hold the offset address. Adding the value of the
base address to the value of the offset address forms the effective address. Indexed addressing
is used with JMP or MOVC instructions. Look up tables are easily implemented with the help
of index addressing.
Eg. MOVC A, @A+DPTR // copies the contents of memory location pointed by the sum of
the accumulator A and the DPTR into accumulator A.
MOVC A, @A+PC // copies the contents of memory location pointed by the sum of the
accumulator A and the program counter into accumulator A.

6. Relative Addressing.
Relative addressing is used only with conditional jump instructions. The relative address,
(offset), is an 8 bit signed number, which is automatically added to the PC to make the
address of the next instruction. The 8 bit signed offset value gives an address range of +127
to —128 locations. The jump destination is usually specified using a label and the assembler
calculates the jump offset accordingly. The advantage of relative addressing is that the
program code is easy to relocate and the address is relative to position in the memory.
Eg. SJMP LOOP1
JC BACK
7. Absolute addressing
Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute Call)
instructions. These are 2 bytes instructions. The absolute addressing mode specifies the
lowest 11 bit of the memory address as part of the instruction. The upper 5 bit of the
destination address are within the current 2 Kbyte page of the program memory.
Eg. AJMP LOOP1
ACALL LOOP2
8. Long Addressing
The long addressing mode is used with the instructions LJMP and LCALL. These are 3-byte
instructions. The address specifies a full 16-bit destination address so that a jump or a call can
be made to a location within a 64 Kbyte code memory space.
Eg. LJMP FINISH
LCALL DELAY
9. Bit Inherent Addressing
In this addressing, the address of the flag which contains the operand, is implied in the
opcode of the instruction.
Eg. CLR C; Clears the carry flag to 0
10. Bit Direct Addressing
In this addressing mode the direct address of the bit is specified in the instruction. The RAM
space 20H to 2FH and most of the special function registers are bit addressable. Bit address
values are between 00H to 7FH.
Eg. CLR 07h; Clears the bit 7 of 20h RAM space
SETB 07H; Sets the bit 7 of 20H RAM space.
INSTRUCTION SET.
The 8051 internal operations and external read/write operations are controlled by the
oscillator clock. T-state, Machine cycle and Instruction cycle are terms used in instruction
timings.

T-state is defined as one subdivision of the operation performed in one clock period.
The terms 'Tstate' and 'clock period' are often used synonymously.
Machine cycle is defined as 12 oscillator periods. A machine cycle consists of six
states and each state lasts for two oscillator periods. An instruction takes one to four
machine cycles to execute an instruction.
Instruction cycle is defined as the time required for completing the execution of an
instruction. The 8051-instruction cycle consists of one to four machine cycles.
Eg. If 8051 microcontrollers are operated with 12 MHz oscillator, find the execution
time for the following four instructions.
1. ADD A, 45H.
2. SUBB A, #55H
3. MOV DPTR, #2000H
4. MUL AB
Since the oscillator frequency is 12 MHz, the clock period is, Clock period = 1/12
MHz = 0.08333 µS. Time for 1 machine cycle = 0.08333 µS x 12 =1 µS.
8051 Instructions
The instructions of 8051 can be broadly classified under the following headings.
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Subroutine instructions
6. Bit manipulation instructions
Data transfer instructions.
In this group, the instructions perform data transfer operations of the following types.
a. Move the contents of a register Rn to A
i. MOV A, R
ii. MOV A, R7
b. Move the contents of a register A to Rn
i. MOV R4,A
ii. MOV R1,A
c. Move an immediate 8 bit data to register A or to Rn or to a memory location(direct or
indirect)
i. MOV A, #45H
ii. MOV R6, #51H
iii. MOV 30H, #44H
iv. MOV @R0, #0E8H
v. MOV DPTR, #0F5A2H
vi. MOV DPTR, #5467H
d. Move the contents of a memory location to A or A to a memory location using direct
and indirect addressing
i. MOV A, 65H
ii. MOV A, @R0
iii. MOV 45H, A
iv. MOV @R1, A
e. Move the contents of a memory location to Rn or Rn to a memory location using
direct addressing
i. MOV R3, 65H
ii. MOV 45H, R2
f. Move the contents of memory location to another memory location using direct and
indirect addressing
i. MOV 47H, 65H
ii. MOV 45H, @R0
g. Move the contents of an external memory to A or A to an external memory
i. MOVX A, @R1
ii. MOVX @R0, A
iii. MOVX A, @DPTR
iv. MOVX @DPTR, A
h. Move the contents of program memory to A
i. MOVC A, @A+PC
ii. MOVC A, @A+DPTR

i. Push and Pop instructions

[SP]=07 //CONTENT OF SP IS 07 (DEFAULT VALUE)
MOV R6, #25H [R6] =25H //CONTENT OF R6 IS 25H
MOV R1, #12H [R1] =12H //CONTENT OF R1 IS 12H
MOV R4, #0F3H [R4] =F3H //CONTENT OF R4 IS F3H
PUSH 6 [SP]=08 [08]=[06]=25H//CONTENT OF 08 IS 25H
PUSH 1 [SP]=09 [09]=[01]=12H //CONTENT OF 09 IS 12H
PUSH 4 [SP]=0A [0A]=[04]=F3H //CONTENT OF 0A IS F3H
POP 6 [06]=[0A]=F3H [SP]=09 //CONTENT OF 06 IS F3H
POP 1 [01]=[09]=12H [SP]=08 //CONTENT OF 01 IS 12H
POP 4 [04]=[08]=25H [SP]=07 //CONTENT OF 04 IS 25H

j. Exchange instructions
The content of source ie., register, direct memory or indirect memory will be exchanged with
the contents of destination ie., accumulator.
i. XCH A,R3
ii. XCH A,@R1
iii. XCH A,54h
k. Exchange digit. Exchange the lower order nibble of Accumulator (A0-A3) with lower
order nibble of the internal RAM location which is indirectly addressed by the register.
i. XCHD A,@R1
ii. XCHD A,@R0

Examples
1. Load the external memory address pointer DPTR with 0x1000. Show an
alternate solution in which 8 bit operands are used.
MOV DPTR, #1000H
Alternate Solution
MOV DPH, #10H
MOV DPL, #00H

2. How can a byte be transferred from the address pointed by R0 to the register
R2? There is no MOV @Ri, Rn instruction available.
Byte pointed by R0 can be moved into A and then to R2.
MOV A, @R0
MOV R2, A
3. Assuming the PC to be 1000H, transfer the code at 1000H to the internal
RAM at 70H.
First , we load A with 00H. Then , we can use the MOVC instruction to get
the code into A. From A, we can load it into 70H.
MOV A, #00H;
MOVC A, @A+PC;
MOV 70H, A;

4. Using DPTR, transfer the codes from 1000H and 1001H to addresses 7EH
and 7FH in RAM.
MOV DPTR, 1000H;
 MOV A, #00H;
MOVC A, @A+DPTR;
MOV 7EH, A; // to read the code at 1000H into 7EH.
//With DPTR already loaded, move 01H into A and use MOVC instruction
again and move A to 7FH.
MOV A, #01H;
MOVC A, @A+DPTR;
MOV 7FH, A; // to read the code at 1001H into 7FH.

5. Using DPTR, transfer the codes from 1000H and 1001H to external data
memory addresses 1000H and 1001H.
MOV DPTR, 1000H;
MOV A, #00H;
MOVC A, @A+DPTR; //to read the code at 1000H into A.
//DPTR is already loaded. From A, we can store byte into external data
memory at 1000H because DPTR= 1000H and we can use
MOVX @DPTR, A;
//Now ,for next code save at the next address , we can perform the
operations as:
MOV DPTR, 1001H;
MOV A, #00H;
MOVC A, @A+DPTR;
MOVX @DPTR, A; //to read the code at 1001H and write into data
memory 1001H.
6. Assume that R0 to R7 have the array values in the ascending order.
Rearrange these in the descending order.
We can use the LIFO property of the push and pop stack operations as
follows:-
PUSH 00H;
PUSH 01H;
PUSH 02H;
PUSH 03H;
PUSH 04H;
PUSH 05H;
PUSH 06H;
PUSH 07H;
POP 00H; // The largest value is stored in R0
POP 01H;
POP 02H;
POP 03H;
POP 04H;
POP 05H;
POP 06H;
POP 07H;
Arithmetic instructions.
The 8051 can perform addition, subtraction. Multiplication and division operations on 8- bit
numbers.
Addition
In this group, we have instructions to
i. Add the contents of A with immediate data with or without carry.
i. ADD A, #45H
ii. ADDC A, #OB4H
i. Add the contents of A with register Rn with or without carry.
i. ADD A, R5
ii. ADDC A, R2
iii. Add the contents of A with contents of memory with or without carry using direct and
indirect addressing
i. ADD A, 51H
ii. ADDC A, 75H
iii. ADD A, @R1
iv. ADDC A, @R0
CY, AC and OV flags will be affected by this operation.
Subtraction
In this group, we have instructions to
i. Subtract the contents of A with immediate data with or without carry.
i. SUBB A, #45H
ii. SUBB A, #OB4H
ii. Subtract the contents of A with register Rn with or without carry.
i. SUBB A, R5
ii. SUBB A, R2
iii. Subtract the contents of A with contents of memory with or without carry using direct
and indirect addressing
i. SUBB A, 51H
ii. SUBB A, 75H
iii. SUBB A, @R1
iv. SUBB A, @R0
CY AC and OV flags will be affected by this operation.
Multiplication
MUL AB.
This instruction multiplies two 8 bit unsigned numbers which are stored in A and B register.
After multiplication the lower byte of the result will be stored in accumulator and higher byte
of result will be stored in B register.
Eg. MOV A,#45H ;[A]=45H
MOV B,#0F5H ;[B]=F5H
MUL AB ;[A] x [B] = 45 x F5 = 4209 ;[A]=09H, [B]=42H
Division
DIV AB.
This instruction divides the 8 bit unsigned number which is stored in A by the 8 bit unsigned
number which is stored in B register. After division the result will be stored in accumulator
and remainder will be stored in B register.
Eg. MOV A,#45H ;[A]=0E8H
MOV B,#0F5H ;[B]=1BH
DIV AB ;[A] / [B] = E8 /1B = 08 H with remainder 10H ;[A] = 08H, [B]=10H

DA A (Decimal Adjust After Addition).

When two BCD numbers are added, the answer is a non-BCD number. To get the result in
BCD, we use DA A instruction after the addition. DA A works as follows.
If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to lower nibble.
If upper nibble is greater than 9 or carry is 1, 6 is added to upper nibble.

Eg 1: MOV A, #23H
MOV R1,#55H
ADD A,R1 // [A]=78
DA A // [A]=78 no changes in the accumulator after da a

Eg 2: MOV A,#53H
MOV R1,#58H
ADD A,R1 // [A]=ABh
DA A // [A]=11, C=1 . ANSWER IS 111. Accumulator data is changed after DA A
Increment: increments the operand by one.
INC A INC Rn INC DIRECT
INC @Ri INC DPTR
INC increments the value of source by 1. If the initial value of register is FFh, incrementing
the value will cause it to reset to 0. The Carry Flag is not set when the value "rolls over"
from 255 to 0.
In the case of "INC DPTR", the value two-byte unsigned integer value of DPTR is
incremented. If the initial value of DPTR is FFFFh, incrementing the value will cause it to
reset to 0.
Decrement: decrements the operand by one.
DEC A DEC Rn
DEC DIRECT DEC @Ri
DEC decrements the value of source by 1. If the initial value of is 0, decrementing the value
will cause it to reset to FFh. The Carry Flag is not set when the value "rolls over" from 0 to
FFh.
Logical Instructions
Logical AND
ANL destination, source:
ANL does a bitwise "AND" operation between source and destination, leaving the resulting
value in destination. The value in source is not affected. "AND" instruction logically AND
the bits of source and destination.
ANL A,#DATA ANL A, Rn ANL A,DIRECT
ANL A,@Ri ANL DIRECT,A ANL DIRECT, #DATA
Logical OR
ORL destination, source:
ORL does a bitwise "OR" operation between source and destination,leaving the resulting
value in destination. The value in source is not affected. " OR " instruction logically OR the
bits of source and destination.
ORL A,#DATA ORL A, Rn
ORL A,DIRECT ORL A,@Ri
ORL DIRECT,A ORL DIRECT, #DATA
Logical Ex-OR
XRL destination, source:
XRL does a bitwise "EX-OR" operation between source and destination, leaving the
resulting value in destination. The value in source is not affected. " XRL " instruction
logically EX-OR the bits of source and destination.
XRL A, #DATA XRL A,Rn
 XRL A, DIRECT XRL A,@Ri
XRL DIRECT, A XRL DIRECT, #DATA
Logical NOT
CPL complements operand, leaving the result in operand. If operand is a single bit
then the state of the bit will be reversed. If operand is the Accumulator then all the bits in the
Accumulator will be reversed.
CPL A,
SWAP A – Swap the upper nibble and lower nibble of A.
Rotate Instructions
RR A
This instruction is rotate right the accumulator. Its operation is illustrated below. Each bit is
shifted one location to the right, with bit 0 going to bit 7.
RL A
Rotate left the accumulator. Each bit is shifted one location to the left, with bit 7 going to bit0
RRC A
Rotate right through the carry. Each bit is shifted one location to the right, with bit 0 going
into the carry bit in the PSW, while the carry was at goes into bit 7.
RLC A
Rotate left through the carry. Each bit is shifted one location to the left, with bit 7 going into
the carry bit in the PSW, while the carry goes into bit 0.

Examples
1. What will be the effect of RRC A, assuming A = 02H and C = 1?

2. Complement the Port P2 bits.

3. Clear bit 1 at the RAM.

4. Test whether Port P2 bit 5 is set.

5. Add 128 and 129 decimals.

6. Write a program to subtract a 16- bit number stored at locations 51H-52H from 55H-
56H and store the result in locations 40H and 41H. Assume that the least significant
byte of data or the result is stored in low address. If the result is positive, then store
00H, else store 01H in 42H.

7. Write a program to add two Binary Coded Decimal (BCD) numbers stored at
locations 60H and 61H and store the result in BCD at memory locations 52H and
53H. Assume that the least significant byte of the result is stored in low address.
Arithmetic instructions.
The 8051 can perform addition, subtraction. Multiplication and division operations on 8- bit
numbers.
Addition
In this group, we have instructions to
i. Add the contents of A with immediate data with or without carry.
i. ADD A, #45H
ii. ADDC A, #OB4H
i. Add the contents of A with register Rn with or without carry.
i. ADD A, R5
ii. ADDC A, R2
iii. Add the contents of A with contents of memory with or without carry using direct and
indirect addressing
i. ADD A, 51H
ii. ADDC A, 75H
iii. ADD A, @R1
iv. ADDC A, @R0
CY, AC and OV flags will be affected by this operation.
Subtraction
In this group, we have instructions to
i. Subtract the contents of A with immediate data with or without carry.
i. SUBB A, #45H
ii. SUBB A, #OB4H
ii. Subtract the contents of A with register Rn with or without carry.
i. SUBB A, R5
ii. SUBB A, R2
iii. Subtract the contents of A with contents of memory with or without carry using direct
and indirect addressing
i. SUBB A, 51H
ii. SUBB A, 75H
iii. SUBB A, @R1
iv. SUBB A, @R0
CY AC and OV flags will be affected by this operation.
Multiplication
MUL AB.
This instruction multiplies two 8 bit unsigned numbers which are stored in A and B register.
After multiplication the lower byte of the result will be stored in accumulator and higher byte
of result will be stored in B register.
Eg. MOV A,#45H ;[A]=45H
MOV B,#0F5H ;[B]=F5H
MUL AB ;[A] x [B] = 45 x F5 = 4209 ;[A]=09H, [B]=42H
Division
DIV AB.
This instruction divides the 8 bit unsigned number which is stored in A by the 8 bit unsigned
number which is stored in B register. After division the result will be stored in accumulator
and remainder will be stored in B register.
Eg. MOV A,#45H ;[A]=0E8H
MOV B,#0F5H ;[B]=1BH
DIV AB ;[A] / [B] = E8 /1B = 08 H with remainder 10H ;[A] = 08H, [B]=10H

DA A (Decimal Adjust After Addition).

When two BCD numbers are added, the answer is a non-BCD number. To get the result in
BCD, we use DA A instruction after the addition. DA A works as follows.
If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to lower nibble.
If upper nibble is greater than 9 or carry is 1, 6 is added to upper nibble.

Eg 1: MOV A, #23H
MOV R1,#55H
ADD A,R1 // [A]=78
DA A // [A]=78 no changes in the accumulator after da a

Eg 2: MOV A,#53H
MOV R1,#58H
ADD A,R1 // [A]=ABh
DA A // [A]=11, C=1 . ANSWER IS 111. Accumulator data is changed after DA A
Increment: increments the operand by one.
INC A INC Rn INC DIRECT
INC @Ri INC DPTR
INC increments the value of source by 1. If the initial value of register is FFh, incrementing
the value will cause it to reset to 0. The Carry Flag is not set when the value "rolls over"
from 255 to 0.
In the case of "INC DPTR", the value two-byte unsigned integer value of DPTR is
incremented. If the initial value of DPTR is FFFFh, incrementing the value will cause it to
reset to 0.
Decrement: decrements the operand by one.
DEC A DEC Rn
DEC DIRECT DEC @Ri
DEC decrements the value of source by 1. If the initial value of is 0, decrementing the value
will cause it to reset to FFh. The Carry Flag is not set when the value "rolls over" from 0 to
FFh.
Logical Instructions
Logical AND
ANL destination, source:
ANL does a bitwise "AND" operation between source and destination, leaving the resulting
value in destination. The value in source is not affected. "AND" instruction logically AND
the bits of source and destination.
ANL A,#DATA ANL A, Rn ANL A,DIRECT
ANL A,@Ri ANL DIRECT,A ANL DIRECT, #DATA
Logical OR
ORL destination, source:
ORL does a bitwise "OR" operation between source and destination,leaving the resulting
value in destination. The value in source is not affected. " OR " instruction logically OR the
bits of source and destination.
ORL A,#DATA ORL A, Rn
ORL A,DIRECT ORL A,@Ri
ORL DIRECT,A ORL DIRECT, #DATA
Logical Ex-OR
XRL destination, source:
XRL does a bitwise "EX-OR" operation between source and destination, leaving the
resulting value in destination. The value in source is not affected. " XRL " instruction
logically EX-OR the bits of source and destination.
XRL A, #DATA XRL A,Rn
 XRL A, DIRECT XRL A,@Ri
XRL DIRECT, A XRL DIRECT, #DATA
Logical NOT
CPL complements operand, leaving the result in operand. If operand is a single bit
then the state of the bit will be reversed. If operand is the Accumulator then all the bits in the
Accumulator will be reversed.
CPL A,
SWAP A – Swap the upper nibble and lower nibble of A.
Rotate Instructions
RR A
This instruction is rotate right the accumulator. Its operation is illustrated below. Each bit is
shifted one location to the right, with bit 0 going to bit 7.
RL A
Rotate left the accumulator. Each bit is shifted one location to the left, with bit 7 going to bit0
RRC A
Rotate right through the carry. Each bit is shifted one location to the right, with bit 0 going
into the carry bit in the PSW, while the carry was at goes into bit 7.
RLC A
Rotate left through the carry. Each bit is shifted one location to the left, with bit 7 going into
the carry bit in the PSW, while the carry goes into bit 0.
Examples
1. What will be the effect of RRC A, assuming A = 02H and C = 1?

C=1 A= 0000 0010

After RRC A
C=0, A= 1000 0001
That is, A = 81 H

2. Complement the Port P2 bits.

There is no complement direct instruction. Port P2 bits can be complemented through

the use of A.
XCH A, P2
CPL A
XCH A, P2

3. Clear bit 1 at the RAM.

 It means that make the bit at bit address 01H = 0.

4. Test whether Port P2 bit 5 is set.

Address for the byte of P2 is A0H.

ANL C, A5H.

5. Add 128 and 129 decimals.

128 in hexadecimal is 80H.

129 is 81H.
So, the instructions are
MOV A, #80H
ADD A, #81H

6. Write a program to subtract a 16- bit number stored at locations 51H-52H from 55H-
56H and store the result in locations 40H and 41H. Assume that the least significant
byte of data or the result is stored in low address. If the result is positive, then store
00H, else store 01H in 42H.

ORG 0000H;
MOV A, 55H;
CLR C;
SUBB A, 51H;
MOV 40H, A;
MOV A, 56H;
SUBB A, 52H;
MOV 41H, A;
MOV A, #00;
ADDC A, #00;
MOV 42H, A;
END

7. Write a program to add two Binary Coded Decimal (BCD) numbers stored at
locations 60H and 61H and store the result in BCD at memory locations 52H and
53H. Assume that the least significant byte of the result is stored in low address.
ORG 0000H;
MOV A, 60H;
ADD A, 61H;
DA A;
MOV 52H, A;
MOV A, #00;
ADDC A,#00H;
MOV 53H,A;
END
Branch (JUMP) Instructions
Jump and Call Program Range There are 3 types of jump instructions.
1. Relative Jump
2. Short Absolute Jump
3. Long Absolute Jump

Long, absolute and short jump instructions in 8051.

Examples
1. Jump to a program memory location after 8kB locations (2000H
addresses) from the location of the next instruction, which is 1000H.

2. Jump to a program location after 16 locations backwards from the

location of the next instruction, which is 1000H.
Examples
1. Call to a program memory location after 3kB locations (after 0C00 addresses) from
the location of the next instruction, which is 1000H.

2. Call to a program memory location after 1026 kB locations from the current
instruction.

Conditional short-relative jump instructions in 8051.

Instruction for decrement and then jump in program-loops in 8051.
1. DJNZ Rn, Rel
Decrement Rn , and jump if Rn is still not zero.
2. DJNZ direct, Rel
Decrement byte at the direct and jump if byte is still not zero.
Examples
1. MOV R1, #FA;
NOP;
DJNZ R1, -3;

Loop will execute 250 times and time taken will be 250 ( 1+2) µs when the delay loop
is using DJNZ instruction as it takes 2 cycles of 2 µs and NOP one cycle of 1µs.
Delay = 750 µs within loop.

2. How can we toggle bits at Port 2 after a delay of 4000 µs? Make the bits = 1s as 0s
and 0s as 1s.

3. Write a program to store data FFH into RAM memory locations 50H to 58H using
indirect addressing mode.
 Compare and then conditional jump after comparison in 8051.
1. CJNE A, #data, rel
Compare A and immediate data and jump if both not equal.
2. CJNE Rn, #data, rel
3. CJNE A, direct, rel
4. CJNE @Rn, data, rel

4. Write a program to compute 1 + 2 + 3 + N (say N=15) and save the sum at70H.
Branch (JUMP) Instructions
Jump and Call Program Range There are 3 types of jump instructions.
1. Relative Jump
2. Short Absolute Jump
3. Long Absolute Jump

Long, absolute and short jump instructions in 8051.

Examples
1. Jump to a program memory location after 8kB locations (2000H addresses) from the
location of the next instruction, which is 1000H.
Jump is above 2kB code space. So we can use the jump short.
The memory location to jump is 1000 + 2000 = 3000H.
LJMP 3000H

2. Jump to a program location after 16 locations backwards from the location of the next
instruction, which is 1000H.
Jump is below 256 locations and so we can use short jump.
-16 decimal = F0H as two’s complement number.
SJMP F0H
Examples
1. Call to a program memory location after 3kB locations (after 0C00 addresses) from
the location of the next instruction, which is 1000H.
Jump is above 2kB code space. We can use jump long.
1000H + 0C00H = 1C00H.
LCALL 1C00H;
Conditional short-relative jump instructions in 8051.
Instruction for decrement and then jump in program-loops in 8051.
1. DJNZ Rn, Rel
Decrement Rn , and jump if Rn is still not zero.
2. DJNZ direct, Rel
Decrement byte at the direct and jump if byte is still not zero.
Examples
1. MOV R1, #FA;
NOP;
DJNZ R1, -3;
Loop will execute 250 times and time taken will be 250 ( 1+2) µs when the delay loop
is using DJNZ instruction as it takes 2 cycles of 2 µs and NOP one cycle of 1µs.
Delay = 750 µs within loop.

2. How can we toggle bits at Port 2 after a delay of 4000 µs? Make the bits = 1s as 0s
and 0s as 1s.

MOV A, #FFH;
MOV R0, #04H;
MOV R1, #FAH;
NOP;
DJNZ R1, -5;
DJNZ R0, -7;
XRL A, P2;
MOV P2, A

3. Write a program to store data FFH into RAM memory locations 50H to 58H using
indirect addressing mode.

ORG 0000H ;
MOV A, #0FFH ;
MOV RO, #50H ;
MOV R5, #08H ;
Start: MOV @RO, A ;
INC RO ;
DJNZ R5, start ;
END
Compare and then conditional jump after comparison in 8051.
1. CJNE A, #data, rel
Compare A and immediate data and jump if both not equal.
2. CJNE Rn, #data, rel
3. CJNE A, direct, rel
4. CJNE @Rn, data, rel

5. Write a program to compute 1 + 2 + 3 + N (say N=15) and save the sum at70H.

ORG 0000H;
N EQU 15;
MOV R0, #00;
CLR A;
start: INC R0;
ADD A, R0;
CJNE R0, #N, start;
MOV 70H, A;
ASSEMBLER DIRECTIVES.
Assembler directives tell the assembler to do something other than creating the machine code
for an instruction. In assembly language programming, the assembler directives instruct the
assembler to
1. Process subsequent assembly language instructions
2. Define program constants
3. Reserve space for variables
The following are the widely used 8051 assembler directives.
ORG (origin)
The ORG directive is used to indicate the starting address. It can be used only when the program
counter needs to be changed. The number that comes after ORG can be either in hex or in
decimal. Eg: ORG 0000H ; Set PC to 0000.
EQU and SET
EQU and SET directives assign numerical value or register name to the specified symbol name.
EQU is used to define a constant without storing information in the memory. The symbol
defined with EQU should not be redefined. SET directive allows redefinition of symbols at a
later stage.
DB (DEFINE BYTE)
The DB directive is used to define an 8 bit data. DB directive initializes memory with 8 bit
values. The numbers can be in decimal, binary, hex or in ASCII formats. For decimal, the 'D'
after the decimal number is optional, but for binary and hexadecimal, 'B' and ‘H’ are required.
For ASCII, the number is written in quotation marks (‘LIKE This).
DATA1: : DB 40H ; hex
DATA2: DB 01011100B ; binary
DATA3: DB 48 ; decimal
DATA4: DB 'HELLOW’ ; ASCII

END
The END directive signals the end of the assembly module. It indicates the end of the program
to the assembler. Any text in the assembly file that appears after the END directive is ignored.
If the END statement is missing, the assembler will generate an error message.
BASICS OF INTERRUPTS.
During program execution if peripheral devices needs service from microcontroller, device will
generate interrupt and gets the service from microcontroller. When peripheral device activates
the interrupt signal, the processor branches to a program called interrupt service routine. After
executing the interrupt service routine, the processor returns to the main program.
Steps taken by processor while processing an interrupt:
1. It completes the execution of the current instruction.
2. PSW is pushed to stack.
3. PC content is pushed to stack.
4. Interrupt flag is reset.
5. PC is loaded with ISR address.
ISR will always ends with RETI instruction. The execution of RETI instruction results in the
following.
1. POP the current stack top to the PC.
2. POP the current stack top to PSW.
Actions on an interrupt of a program by a source.
Interrupt Check if
interrupts
Check which
enabled (IE.7
Instructions source priority
= 1) and other
highest from
IE bit
IP register

Save next Check default

instruction PC priority if IP
Find interrupt
on stack and shows equal
vector address
disable priority
interrupt

Run ISR and Restore PC Execute next

reset source and Return to instruction if
flag if auto- interrupted no interrupt
reset program pending
provision
exits
Classification of interrupts.
1. External and internal interrupts.
External interrupts are those initiated by peripheral devices through the external pins of
the microcontroller. Internal interrupts are those activated by the internal peripherals of
the microcontroller like timers, serial controller etc.)

2. Maskable and non-maskable interrupts.

The category of interrupts which can be disabled by the processor using program is
called maskable interrupts. Non-maskable interrupts are those categories by which the
programmer cannot disable it using program.

3. Vectored and non-vectored interrupt.

Starting address of the ISR is called interrupt vector. In vectored interrupts the starting
address is predefined. In non-vectored interrupts, the starting address is provided by the
peripheral as follows.
Microcontroller receives an interrupt request from external device.
Controller sends an acknowledgement (INTA) after completing the execution of
current instruction.
The peripheral device sends the interrupt vector to the microcontroller.
8051 INTERRUPT STRUCTURE.
8051 has five interrupts. They are maskable and vectored interrupts. Out of these five,
two are external interrupt and three are internal interrupts.

Interrupt source Type Vector address Priority

External interrupt 0 External 0003 Highest
Timer 0 interrupt Internal 000B
External interrupt 1 External 0013
Timer 1 interrupt Internal 001B
Serial interrupt Internal 0023 Lowest

8051 makes use of two registers to deal with interrupts.

1. IE Register
This is an 8 bit register used for enabling or disabling the interrupts.
IE : Interrupt Enable Register (Bit Addressable)
If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding
interrupt is enabled.

EA - - ES ET1 EX1 ET0 EX0

EA IE.7 Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If

EA = 1, interrupt source is individually enabled or disabled by setting or
clearing its enable bit.
IE.6 Not implemented. Reserved for future use.
 IE.5 Not implemented. Reserved for future use.
ES IE.4 Enable or disable the serial port interrupt.
ET1 IE.3 Enable or disable the Timer 1 overflow interrupt.
EX1 IE.2 Enable or disable External interrupt 1.
ET0 IE.1 Enable or disable the Timer 0 overflow interrupt.
EX0 IE.0 Enable or disable External interrupt 0.

2. IP Register
This is an 8 bit register used for setting the priority of the interrupts.
If the bit is 0, the corresponding interrupt has a lower priority. If bit is 1, the
corresponding interrupt has a higher priority.
Interrupt Priority Register

- - - PS PT1 PX1 PT0 PX0

IP.7 Not Implemented, reserved for future use.

IP.6 Not Implemented, reserved for future use.
IP.5 Not Implemented, reserved for future use.
PS IP.4 Defines the Serial Port Interrupt Priority Level.
PT1 IP.3 Defines the Timer 1 Interrupt Priority Level.
PX1 IP.2 Defines External Interrupt 1 Priority Level.
PT0 IP.1 Defines the Timer 0 Interrupt Priority Level.
PX0 IP.0 Defines External Interrupt 0 Priority Level.
TIMERS / COUNTERS
Timers/Counters are used generally for
 Time reference
 Creating delay
 Wave form properties measurement
 Periodic interrupt generation
 Waveform generation
Timer in 8051 is used as timer, counter and baud rate generator. Timer always counts up
irrespective of whether it is used as timer, counter, or baud rate generator: Timer is always
incremented by the microcontroller. The time taken to count one digit up is based on master
clock frequency.
If Master CLK=12 MHz,
Timer Clock frequency = Master CLK/12 = 1 MHz
Timer Clock Period = 1micro second
This indicates that one increment in count will take 1 micro second.
1. There are two timers, T0 and T1.
2. Two SFRs, which correspond to timer-0 count variable(s) , are TH0 and TL0.
3. Two SFRs, which correspond to timer-1 count variable(s) , are TH1 and TL1.
4. Two SFRs, which control the timer T0 and T1 functions, are TCON and TMOD.
Programming a timer means programming the TCON and TMOD bits and loading the
appropriate count variable as per the intervals of the clock inputs to the timer/counter.
The following are timer related SFRs in 8051.
SFR Name Description SFR
Address
TH0 Timer 0 high byte 8Ch
TL0 Timer 0 low byte 8Ah
TH1 Timer 1 high byte 8Dh
TL1 Timer 1 low byte 8Bh
TCON Timer Control 88h
TMOD Timer Mode 89h

TMOD Register
TMOD: Timer/Counter Mode Control Register (Not Bit addressable)
GATE C/T M1 M0 GATE C/T M1 M0

Timer 1
Timer 0
GATE When TRx (in TCON) is set and GATE = 1 , TIMER / COUNTERx will run
only when
INTx pin is high (hardware control). When GATE = 0, TIMER / COUNTERx
will run only when TRx = 1 (software control).
C/T Timer or Counter selector. Cleared for timer operation (input from internal
system
clock. Set for counter operation. (input from Tx input pin).
M1 Mode Selector bit.
M2 Mode Selector bit.
M1 M0 OPERATING MODE
0 0 Mode 0 – 13 bit timer
0 1 Mode 1 – 16 bit timer
1 0 Mode 2 – 8 bit auto reload timer
1 1 Mode 3 – (Timer 0), TL0 is an 8-bit timer / counter controlled by the
standard Timer 0 control bits. THO is an 8-bit timer and is controlled
by Timer 1 control bits.
1 1 (Timer 1) Timer / Counter stops.

TCON: Timer /Counter Control Register (Bit Addressable)

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TF1 TCON. Timer 1 overflow flag. Set by hardware when the Timer / Counter 1
7 overflows. Cleared by hardware.
TR TCON. Timer 1 run control bit. Set / Cleared by software to turn Timer / Counter
1 6 1 ON/ OFF.
TF0 TCON. Timer 0 overflow flag. Set by hardware when the Timer / Counter 0
5 overflows. Cleared by hardware.
TR TCON. Timer 0 run control bit. Set / Cleared by software to turn Timer / Counter
0 4 0 ON/ OFF.
IE1 TCON. External interrupt 1 edge flag. Set by hardware when external interrupt
7 edge is detected. Cleared by hardware when interrupt is processed.
IT1 TCON. Interrupt 1 type control bit. Set/Cleared by software to specify falling
7 edge/flow level triggered External interrupt.
IE0 TCON. External interrupt 0 edge flag. Set by hardware when external interrupt
7 edge is detected. Cleared by hardware when interrupt is processed.
IT0 TCON. Interrupt 0 type control bit. Set/Cleared by software to specify falling
7 edge/flow level triggered External interrupt.

Examples
1. 8 LEDs are connected to port 0.Write a program to blink them with 1 sec
delay.
back: mov a,#0ffh
mov p0,a
acall delay
mov a,#00h
mov p0,a
acall delay
sjmp back
delay: mov r7,#64h
back1: mov tmod,#01h
mov th0,#0dbh
mov tl0,#0ffh
setb TR0
l1:jnb TF0,l1
clr TR0
clr TF0
djnz r7,back1
ret
End
2. 8 LEDs are connected to port 0. Write a program to blink them alternatively.
back: mov a,#0aah
mov p2,a
acall delay
mov a,#55h
mov p2,a
acall delay
sjmp back
delay:mov r7,#64h
back1: mov tmod,#01h
mov th0,#093h
mov tl0,#0ffh
setb TR0
l1: jnb TF0,l1
clr TR0
clr TF0
djnz r7,back1
ret
end
PROGRAMMING 8051 TIMERS IN ASSEMBLY

In order to program 8051 timers, it is important to know the calculation of initial count value to be
stored in the timer register. The calculations are as follows.

In any mode,

Timer Clock period = 1/Timer Clock Frequency. = 1/ (Master Clock Frequency/12), here 1 micro
second.

a. Mode 1 (16-bit timer/counter)

Value to be loaded in decimal = 65536 – (Delay Required/Timer clock period).

Convert the answer into hexadecimal and load onto THx and TLx register. (65536D = FFFFH+1) b.
b. Mode 0 (13 bit timer/counter)

Value to be loaded in decimal = 8192 – (Delay Required/Timer clock period).

Convert the answer into hexadecimal and load onto THx and TLx register. (8192D = 1FFFH+1) c.
c. Mode 2 (8 bit auto reload)

Value to be loaded in decimal = 256 – (Delay Required/Timer clock period).

Convert the answer into hexadecimal and load onto THx register. Upon starting the timer this
value from THx will be reloaded to TLx register. (256D = FFH+1).

Steps for programming timers in 8051

Mode 1:

 Load the TMOD value register indicating which timer (0 or 1) is to be used and which
timer mode is selected.
 Load registers TL and TH with initial count values.
 Start the timer by the instruction “SETB TR0” for timer 0 and “SETB TR1” for timer.
 Keep monitoring the timer flag (TF) with the “JNB TFx,target” instruction to see if it is
raised. Get out of the loop when TF becomes high.
 Stop the timer with the instructions “CLR TR0” or “CLR TR1”, for timer 0 and timer 1,
respectively.
 Clear the TF flag for the next round with the instruction “CLR TF0” or “CLR TF1”, for
timer 0 and timer 1, respectively.
 Go back to step 2 to load TH and TL again.

1. Write a program to continuously generate a square wave of 2 kHz frequency on pin P1.5
using timer 1. Assume the crystal oscillator frequency to be 12 MHz.

The period of the square wave is T = 1/(2 kHz) = 500 µs. Each half pulse = 250 µs.

The value n for 250 µs is: 250 µs /1 µs = 250

65536 - 250 = FF06H.

TL = 06H and TH = 0FFH.

 MOV TMOD, #10; //Timer 1, mode 1

AGAIN: MOV TL1, #06H; //TL0 = 06H

MOV TH1, #0FFH; //TH0 = FFH

SETB TR1; //Start timer 1

BACK: JNB TF1, BACK; //Stay until timer rolls over

CLR TR1; //Stop timer 1

CPL P1.5; //Complement P1.5 to get Hi, Lo

CLR TF1; //Clear timer flag 1

SJMP AGAIN; //Reload timer

SERIAL COMMUNICATION.

The 8051 microcontroller is parallel device that transfers eight bits of data simultaneously
over eight data lines to parallel I/O devices. Parallel data transfer over a long is very expensive.
Hence, a serial communication is widely used in long distance communication. In serial data
communication, 8-bit data is converted to serial bits using a parallel in serial out shift register and
then it is transmitted over a single data line. The data byte is always transmitted with least
significant bit first.

BASICS OF SERIAL DATA COMMUNICATION

1. Simplex communication link:

In simplex transmission, the line is dedicated for transmission. The transmitter sends and
the receiver receives the data.

Transmitter Receiver

2. Half duplex communication link:

In half duplex, the communication link can be used for either transmission or reception.
Data is transmitted in only one direction at a time.

Transmitter Receiver

3. Full duplex communication link:

If the data is transmitted in both ways at the same time, it is a full duplex i.e.
transmission and reception can proceed simultaneously. This communication link
requires two wires for data, one for transmission and one for reception.

Transmitter Receiver
 Transmitter Receiver

Types of Serial communication:

Serial data communication uses two types of communication.

1. Synchronous serial data communication:

In this transmitter and receiver are synchronized. It uses a common clock to synchronize
the receiver and the transmitter. First the synch character is sent and then the data is
transmitted. This format is generally used for high speed transmission. In Synchronous
serial data communication, a block of data is transmitted at a time.

2. Asynchronous Serial data transmission:

In this, different clock sources are used for transmitter and receiver. In this mode, data is
transmitted with start and stop bits. A transmission begins with start bit, followed by
data and then stop bit. For error checking purpose parity bit is included just prior to stop
bit. In Asynchronous serial data communication, a single byte is transmitted at a time.

Baud rate:

The rate at which the data is transmitted is called baud or transfer rate. The baud rate is the
reciprocal of the time to send one bit. In asynchronous transmission, baud rate is not equal to
number of bits per second. This is because; each byte is preceded by a start bit and followed by
parity and stop bit. For example, in synchronous transmission, if data is transmitted with 9600 baud,
it means that 9600 bits are transmitted in one second. For bit transmission time = 1 second/ 9600 =
0.104 ms.

8051 SERIAL COMMUNICATION

The 8051 supports a full duplex serial port. Three special function registers support serial
communication.

1. SBUF Register: Serial Buffer (SBUF) register is an 8-bit register. It has separate SBUF registers for
data transmission and for data reception. For a byte of data to be transferred via the TXD line, it
must be placed in SBUF register. Similarly, SBUF holds the 8-bit data received by the RXD pin and
read to accept the received data.

2. SCON register: The contents of the Serial Port Control (SCON) register are shown below. This
register contains mode selection bits, serial port interrupt bit (TI and RI) and also the ninth data bit
for transmission and reception (TB8 and RB8).

D7 D6 D5 D4 D3 D2 D1 D0
SM0 SM1 SM2 REN TB8 RB8 TI RI
SM0: SCON.7 – Serial Communication mode selection bit

SM1: SCON.6 - Serial Communication mode selection bit

SM SM MODE DESCRIPTION Baud Rate

0 1
0 0 Mode 0 8-bit shift register mode Fosc / 12
0 1 Mode 1 8-bit UART Variable (set by timer 1)
1 0 Mode 2 9-bit UART Fosc / 32 or Fosc / 64
1 1 Mode 3 9-bit UART Variable (set by timer 1)

SM2: SCON.5 – Multiprocessor communication bit. In modes 2 and 3, if set this will enable
multiprocessor communication.

REN: SCON.4 – Enable serial reception.

TB8: SCON.3 – This is the 9th bit that is transmitted in mode 2 and 3.

RB8: SCON.2 - This is the 9th bit that is transmitted in mode 2 and 3.

TI: SCON.1 – Transmit Interrupt flag. Set by hardware must be cleared by software.

RI: SCON.0 – Receive Interrupt flag. Set by hardware must be cleared by software.

3. PCON register: Power Mode Control Register

The SMOD bit (bit 7) of PCON register controls the baud rate in asynchronous mode transmission.

D7 D6 D5 D4 D3 D2 D1 D0
SMOD - - - GF1 GF0 PD IDL

SMOD: PCON.7 – Serial rate modify bit. Set to 1 by program to double baud rate using timer 1 for
modes 1 ,2 and 3. Cleared by program to use timer 1 baud rate.

GF1: PCON.3 – General purpose user flag bit.

GF0: PCON.2 - General purpose user flag bit.

PD: PCON.1 – Power down bit. Set to 1 by program to enter power down configuration for CHMOS
processors.

IDL: PCON.0 – Idle mode bit. Set to 1 by program to enter idle mode configuration for CHMOS
processors.
SERIAL COMMUNICATION MODES

4. Mode 3
Similar to mode 2 except baud rate is calculated as in mode 1.

1. Write a program for the 8051 to transfer letter ‘A’ serially at 4800- baud rate, 8- bit data, 1
stop bit continuously.

ORG 0000H

LJMP START

ORG 0030H

START: MOV TMOD, #20H; //select timer 1 mode 2

MOV TH1, #0FAH; //load count to get baud rate of 4800

MOV SCON, #50H; //initialize UART in mode 2 ; 8 bit data and 1 stop bit

SETB TR1; //start timer

AGAIN: MOV SBUF, #'A’; //load char ‘A’ in SBUF

BACK: JNB TI, BACK; //Check for transmit interrupt flag

CLR TI; //Clear transmit interrupt flag

SJMP AGAIN

END