Some Important Previous Year Question Solutions

(Part-1)
(Computer Architecture)
Bootstrap loader
Alternatively referred to as bootstrapping, boot loader, or boot program, a bootstrap loader
is a program that resides in the computers EPROM, ROM, or other non-volatile memory that
automatically executed by the processor when turning on the computer. The bootstrap
loader reads the hard drives boot sector to continue the process of loading the computers
operating system. The term boostrap comes from the old phrase "Pull yourself up by your
bootstraps."
The boot loader has been replaced in computers that have an Extensible Firmware Interface
(EFI). The boot loader is now part of the EFI BIOS.

Distinguish between memory mapped I/O &

I/O mapped I/O scheme:
Memory mapped I/O scheme I/O Mapped I/o Scheme
In this case I/O devices are treated as memory
device I/O devices are treated as I/O devices.
Memory and I/o has 16 bit addresses Memory and I/o Devices have 8 bit addresses
Possible addresses i.e. memory space is 64 K bytes Possible address i.e. memory space is 256 bytes
and range is 0000H to FFFFH and range is 00H to FFH
Some of the available addresses are assigned to
the memory devices and the remaining are In this case addresses assigned to the memory
assigned to the I/O devices. devices can be assigned to the I/O devices.
No special instructions are required. Instructions
used for the data transfer between a memory and
accumulator are same that are used for data
transfer between an I/O device and accumulator.
E.g. instruction Mov A, M is applicable in both the For the transfer of Data Between microprocessor
cases. Other instructions used are LDA, STA, ADD and I/O device. It requires special instructions such
M etc. as IN and OUT.
More hardware is required to decode 16 bit Less Hardware is required to decode 16 bit
address. addresses.
Less memory space is available because of the
partition of memory between memory and I/O It is not so in this case. Complete address space is
devices. available
Speed is low because length of instructions LDA, Speed is high, because length of IN and OUT
MOV A , M etc is high. instructions is less.
Data Transfer can take place between any register In this case data transfer takes place between
and I/O device. accumulator and I/O only

Notes By: Prof. Amitav Biswas, Behala College Page 1

The functionality of IAS Computer:
 The IAS computer was the first to store the program in the same memory as the
data.
 The logic of the IAS machine was implemented with vacuum tubes.
 The memory of the IAS machine was implemented with cathode ray tubes.
 The word size is 40 bits.
 Memory is word addressed (not byte addressed.)
 Numbers were stored as fractions, not as integers.


S Fraction

 The distinction between fractions and integers only affects multiplication and
division.
 Instructions are fixed size (20 bits), with a single address, stored 2 per word.
 8 bits are allocated for the opcode, allowing 256 different operations; only 21 were
implemented.
 12 bits are allocated for the address, allowing a memory space of 4096 words; IAS
was built with only 1024 words of memory.


Opcode Address Opcode Address

 Two instructions are fetched at once.

 The IAS has 5 separate parts:
o CA, the Central Arithmetic part
o CC, the Central Control part
o M, the primary Memory part
o I, the Input part
o O, the Output part

Notes By: Prof. Amitav Biswas, Behala College Page 2

Zero Address Instructions:
An instruction that contains no address fields; operand sources and destination are both
implicit. It may for example enable stack processing: a zero-address instruction implies that
the absolute address of the operand is held in a special register that is automatically
incremented (or decremented) to point to the location of the top of the stack.

Example: ADD

The above instruction consists of an operation code only. It has no addrss field. The
operation has the effect of popping the two top numbers from the stack, adding the
numbers and pushing the sum into the stack. Here all operands are performed within stack.
To evaluate arithmetic expressions, they must be first converted into reverse polish
notation. The operand at address X is pushed on to the top of the stack. Automatically the
stack pointer is incremented.

Example:

X=(A + B) + (C + D)
PUSH A ; TOS <- A top of the stack
PUSH B ; T0S <- B
ADD ; TOS <- A + B
PUSH C ; TOS <- C
PUSH D ; TOS <- D
ADD ; TOS <- C + D
ADD ; TOS <- (C + D) + (A + B)
POP X ; M [X] <- TOS

Notes By: Prof. Amitav Biswas, Behala College Page 3

Overflow and Underflow:
Overflow is said to occur when the true result of an arithmetic operation is finite but larger
in magnitude than the largest floating point number which can be stored using the given
precision.Underflow is said to occur when the true result of an arithmetic operation is
smaller in magnitude (infinitesimal) than the smallest normalized floating point number
which can be stored. Overflow can’t be ignored in calculations whereas underflow can
effectively be replaced by zero.

Single Precision Format (Normalized and de-

normalized concepts):
As mentioned in Table 1 the single precision format has 23 bits for significand (1 represents
implied bit, details below), 8 bits for exponent and 1 bit for sign.

For example, the rational number 9÷2 can be converted to single precision float format as
following,

9(10) ÷ 2(10) = 4.5(10) = 100.1(2)

The result said to be normalized, if it is represented with leading 1 bit, i.e. 1.001(2) x 22.
(Similarly when the number 0.000000001101(2) x 23 is normalized, it appears as 1.101(2) x 2-
6
). Omitting this implied 1 on left extreme gives us the mantissa of float number. A
normalized number provides more accuracy than corresponding de-normalized number.
The implied most significant bit can be used to represent even more accurate significand (23
+ 1 = 24 bits) which is called subnormal representation. The floating point numbers are to be
represented in normalized form.

Difference between Instruction

cycle,machine cycle,clock cycle, T-state:
Clock cycle is the time required to complete one instruction by the controller.
Instruction cycle is the process by which a controller retrieves a program instruction from its
memory, determines what actions the instruction requires, and carries out those actions, ei,
the fetch-decode-execute cycle.
Machine cycle are the steps performed by the computer processor for each machine
language instruction received. The machine cycle is a 4 process cycle that includes reading
and interpreting the machine language, executing the code and then storing that code.
Which of the T-states are you referring to? One is the cycles that the machine cycles need,
the other being known as "tri-state" which is a high-impedance state which is neither high
nor low.

Notes By: Prof. Amitav Biswas, Behala College Page 4

Characteristic of the memory:
Speed
In order to measure the yield three parameters are used:

Access time (TA)

RAM: time that passes from the moment at which a direction of the memory appears until
the data either has been stored or is available for its use.

Memory cycle time (TC)

Time that passes since a read/write order operation occurs until another read/write order
can be given.

Cycle stealing:
Cycle stealing is a method of accessing RAM without interfering with the CPU. It is similar
to DMA for allowing I/O controllers to read or write RAM without CPU intervention. Clever
exploitation of specific CPU or bus timings could permit the CPU to run at full speed without
any delay if external devices may sneak in one RAM access to memory not actively
participating in the CPU's current activity and complete the operations before any possible
CPU conflict. Such systems are nearly dual-port RAM without the expense of high speed
RAM. Most systems halt the CPU during the steal, essentially making it DMA by any other
name.

Instruction cycle:
We have seen that each phase of the instruction cycle can be decomposed into a sequence
of elementary micro-operations. In our example, there is one sequence each for the fetch,
indirect, and interrupt cycles, and, for the execute cycle, there is one sequence of micro-
operations for each opcode.
To complete the picture, we need to tie sequences of micro-operations together, and this is
done in Figure 2. We assume a new 2-bit register called the instruction cycle code (ICC). The
ICC designates the state of the processor in terms of which portion of the cycle it is in:
00: Fetch
01: Indirect
10: Execute
11: Interrupt

Notes By: Prof. Amitav Biswas, Behala College Page 5

Program Status Word
The program status word (PSW) is 32 bits in length and contains the information
required for proper program execution. The PSW includes the instruction address,
condition code, and other fields. In general, the PSW is used to control instruction
sequencing and to hold and indicate the status of the system in relation to the
program currently being executed. The active or controlling PSW is called the
current PSW. By storing the current PSW during an interruption, the status of the
CPU can be preserved for subsequent inspection. By loading a new PSW or part of
a PSW, the state of the CPU can be initialized or changed.

Bus arbitration:
It is a way of sharing the computer's data transferring channels (buses) in an optimal way so
the faster devices won't have to wait to be able to transfer and the slower devices (like
peripherals) will have a chance to transfer as well. Different methods exist but two main
types are the serial and parallel arbitrations. Serials include the daisy chain arbitration and
hardware polling. The parallel ones are software polling and independent requesting .
Centralized bus arbitration requires hardware that will grant the bus to one of the
requesting devices.

Notes By: Prof. Amitav Biswas, Behala College Page 6

SCSI:
Small Computer System Interface (SCSI) is a set of standards for physically connecting and
transferring data between computers and peripheral devices. The SCSI standards
define commands, protocols and electrical and optical interfaces. SCSI is most commonly
used for hard disks and tape drives, but it can connect a wide range of other devices,
including scanners and CD drives, although not all controllers can handle all devices. The
SCSI standard defines command sets for specific peripheral device types; the presence of
"unknown" as one of these types means that in theory it can be used as an interface to
almost any device, but the standard is highly pragmatic and addressed toward commercial
requirements.

SCSI connectors

The below illustrations are examples of some of the most commonly found and used SCSI
connectors on computers and devices and illustrations of each of these connections.

USB:
Universal Serial Bus (USB) is an industry standard developed in the mid-1990s that defines
the cables, connectors and communications protocolsused in a bus for connection,
communication, and power supply between computers and electronic devices.
USB was designed to standardize the connection of computer peripherals (including
keyboards, pointing devices, digital cameras, printers, portable media players, disk
drives and network adapters) to personal computers, both to communicate and to
supply electric power. It has become commonplace on other devices, such
as smartphones, PDAs and video game consoles. USB has effectively replaced a variety of
earlier interfaces, such as serial and parallel ports, as well as separate power chargers for
portable devices.

Notes By: Prof. Amitav Biswas, Behala College Page 7

Open Collector Input:
An open collector is a common type of output found on many integrated circuits (IC).
Instead of outputting a signal of a specific voltage or current, the output signal is applied to
the base of an internal NPN transistor whose collector is externalized (open) on a pin of the
IC. The emitter of the transistor is connected internally to the ground pin. If the output
device is a MOSFET the output is called open drain and it functions in a similar way.

What Is a 16 Bit Processor?

A 16 bit processor is a processor that can process data and memory addresses that are
represented by sixteen bits. The 16 bit part represents the number of bits that can be
transmitted in parallel or processed, or the number of bits used for only one element in a
data format.

Notes By: Prof. Amitav Biswas, Behala College Page 8

Role of Stack in Microprocessor:
Stack is used largely during a function call but depending on the language and level of
programming it may be used to temporarily store processor register data or other variables.

Further, the stack may also be used for short-term large-scale storage of data when
using recursive functions that store partial data in the stack and call themselves again.
The generic use of stack is for,
1. Return address
2. return value
3. parameters to called function
4. local variables in the called function
5. processor registers that will be reused in the called function

A computer uses a memory unit 256k words of 32 bits each. A binary

instruction code is stored in one word of memory. The instruction has four
parts : indirect bit , an operation code , a register code part to specify one of
64 registers, and an address part.

a. How many bits are there in the operation code , the register code part ,
and the address part?
b. Draw the instruction word format and indicate the number of bits in
each part.
c. How many bits are there in the data and address inputs of the memory?

Ans:

Notes By: Prof. Amitav Biswas, Behala College Page 9

Difference between direct & indirect
addressing:
Direct addressing has the address of a memory location as the operand in an instruction. For
instance the instruction MOV R0 00H,
R0, when converted to machine language is the physical address of register R0. The
instruction moves 0 to R0.

Indirect addressing has a pointer to the memory location as the operand in an instruction.
For instance the instruction MOV @R0 00H, when converted to machine language, @R0
becomes whatever is stored in R0, and that is the address used to move 0 to. It can be
whatever is stored in R0.

A computer has 32-bit instructions and 12-bit addresses. If there are 250 two
address instructions, how many one – address instruction can be formulated?

Notes By: Prof. Amitav Biswas, Behala College Page 10