EC3561 VLSI LABORATORY LT PC

0 04 2
COURSE OBJECTIVES:
● To learn Hardware Descriptive Language (Verilog/VHDL).
● To learn the fundamental principles of Digital System Desing using HDL and FPGA.
● To learn the fundamental principles of VLSI circuit design in digital domain
● To learn the fundamental principles of VLSI circuit design in analog domain
● To provide hands on design experience with EDA platforms.

LIST OF EXPERIMENTS:
1. Design of basic combinational and sequential (Flip-flops) circuits using HDL. Simulate it
using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
2. Design an Adder ; Multiplier (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
3. Design and implement Universal Shift Register using HDL. Simulate it using Xilinx/Altera
Software
4. Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
5. Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera
Software and implement by Xilinx/Altera FPGA
6. Design 3-bit synchronous up/down counter using HDL. Simulate it using Xilinx/Altera
Software and implement by Xilinx/Altera FPGA
7. Design 4-bit Asynchronous up/down counter using HDL. Simulate it using Xilinx/Altera
Software and implement by Xilinx/Altera FPGA
8. Design and simulate a CMOS Basic Gates & Flip-Flops. Generate Manual/Automatic
Layout .
9. Design and simulate a 4-bit synchronous counter using a Flip-Flops. Generate
Manual/Automatic Layout
10. Design and Simulate a CMOS Inverting Amplifier.
11. Design and Simulate basic Common Source, Common Gate and Common Drain Amplifiers.
12. Design and simulate simple 5 transistor differential amplifier.

COURSE OUTCOMES:
On completion of the course, students will be able to:
CO1: Write HDL code for basic as well as advanced digital integrated circuit
CO2: Import the logic modules into FPGA Boards
CO3: Synthesize Place and Route the digital Ips
CO4: Design, Simulate and Extract the layouts of Digital & Analog IC Blocks using EDA
tools
CO5: Test and Verification of IC design
TOTAL: 60 PERIODS
CO’s-PO’s & PSO’s MAPPING
C PO PO PO PO PO PO PO PO PO PO1 PO1 PO1 PSO PSO PSO
1
O 1
2 2- 3- 4- 5- 6- 7- 8- 9- 0- 1- 2- 1
2 2
3 3
2
2 3 3 1 1 - - - - - - - - 2 1 2
3 1 2 2 2 - - - - - - 1 1 2 2 2
4 - 1 3 3 1 - - - - - 1 1 2 2 2
5 3 3 3 3 1 - - - - - 1 1 2 2 2
C 2.2 2.2 2.2 2.2 1 - - - - - 1 1 2 2 2
1O- low, 2 - medium, 3 - high, ‘-' - no correlation
93
Exp. No. 1
DESIGN AND IMPLEMETATION OF BASIC COMBINATIONAL
Date: AND SEQUENTIAL CIRCUITS

Aim:
i) To write a Verilog HDL program for Logic gates.

(ii) To generate *.ucf [user constraint file] by doing P&R [Placement and Routing]
simulation and implement the design in Nexys 3 – SPARTAN 6 FPGA kit. (iii)

Test the blocks generated by using chipscope pro analyzer.

Tools Required:
1. PC with Xilinx Vivado System Edition S Ver 14.6 and Chipscope pro analyzer.
2. Spartan 6 FPGA Trainer Kit (Nexys3™ Board)
Procedure:
(i) Analyse the design specification, draw the logic diagram and truth table for the
given design specification.
(ii) Write the Verilog-HDL code for the design specification given.
(iii) Follow the procedure given in appendix-A for simulation and
implementation.
(iv) Verify the simulation result with implementation result.

Theory:
A Logic Gate is an electronic circuit which makes logical decisions. To arrive at these
decisions, the most common logic gates used are AND, OR, NOT, NAND and NOR gates.
The NAND and NOR gates are called as the universal gates. EX-OR and EX- NOR gates are
another logic gates which can be constructed using basic gates such as AND, OR, NOT gates.

AND Gate:
The AND gate performs logical multiplication, commonly known as AND function.
The AND gate has two or more inputs and a single output. The output of an AND gate is
HIGH when all the inputs are HIGH. Even if any one of the input is low, the output will
be LOW.
If A and B are the input variables of an AND gate and Y is its output, then Y= A.B
 Symbol: Truth Table:

INPUT OUTPUT
i1 i2 out =
0 0
0 1
1 0
1 1
Verilog HDL Code for AND Gate:

module Andgate (i1, i2,out);

input i1, i2;
output out;
and (out, i1,i2);
end module

OR Gate:
The OR gate performs logical addition, commonly known as OR function. The OR
gate has two or more inputs and a single output. The output of an OR gate is HIGH when
anyone of the inputs are HIGH. The output will be LOW only when all the inputs are LOW.

If A and B are the input variables of an OR gate and Y is its output, then Y= A+B

Symbol: Truth Table:

INPUT OUTPUT
i1 i2 out =
0 0
0 1
1 0
1 1
Verilog HDL Code for OR Gate:

module Orgate (i1, i2,out);

input i1, i2;
output out;
or (out,i1,i2);
endmodule

NOT Gate: (Inverter)

The NOT Gate Performs the basic logical function called inversion or
complementation. The purpose of this gate is to convert one logic level into the opposite
logic level. It has one input and one output. When a HIGH level is applied to an
inverter, a LOW level appears at its output and vice versa.

If A is the input variable of a NOT gate and Y is its output, then Y= A’

Symbol: Truth Table:

INPUT OUTPUT
i1 out=
0
1

Verilog HDL Code for NOT Gate:

module Notgate (i1, out);

input i1;
output out;
not (out,i1);
endmodule
NAND GATE:

NAND is a combination of NOT-AND Gates. It has two or more inputs and only
one output. The output is HIGH when any one or both the inputs are LOW. When all
the inputs are HIGH, the output is LOW.
If A and B are the input variables of an OR gate and Y is its output, then Y=
(A.B)’

Symbol: Truth Table:

INPUT OUTPUT
i1 i2 out =
0 0
0 1
1 0
1 1
Verilog HDL Code for NAND Gate:

module Nandgate (i1, i2,out);

input i1, i2;
output out;
nand (out,i1,i2);
endmodule

NOR GATE:
NOR is a combination of NOT-OR Gates. It has two or more inputs and only one
output. The output is HIGH only when all the inputs are LOW. If any one or both the
inputs are HIGH, then the output is LOW.
If A and B are the input variables of an OR gate and Y is its output, then Y=
(A+B)’
Symbol: Truth Table:

INPUT OUTPUT
i1 i2 out =
0 0
0 1
1 0
Verilog HDL Code for NOR Gate: 1 1

Module Norgate (i1, i2,out);

input i1, i2;
output out;
nor (out,i1,i2);
endmodule

EX-OR Gate:
An Exclusive-OR gate is a gate with two inputs and one output. The output of
two input EX-OR gate is HIGH if either input A or input B is High exclusively, and
LOW when both are in logic HIGH or LOW.

If A and B are the input variables of an EX-OR gate and Y is its output, then
Y= ’+A’.B

Symbol: Truth Table:

INPUT OUTPUT
i1 i2 out =
0 0
Verilog HDL Code for EX-OR Gate: 0 1
1 0
module Xorgate (i1, i2,out); 1 1

input i1, i2;

output out;
xor (out,i1,i2);
endmodule
EX-NOR Gate:

An Exclusive-NOR gate is a gate with two inputs and one output. The output of
two input EX-NOR gate is HIGH when both are in logic HIGH or LOW, and LOW
when either input A or input B is High exclusively.

If A and B are the input variables of an EX-NOR gate and Y is its output, then
Y= A.B+A’.B’

Symbol: Truth Table:

INPUT OUTPUT
i1 i2 out =
0 0
0 1
1 0
Verilog HDL Code for EX-NOR Gate: 1 1

module Xnorgate (i1, i2,out);

input i1, i2;
output out;
xnor (out,i1,i2);
endmodule
Pre Lab work:
Q1. Fill the truth table and write the equations for gates wherever left
blank.
Q2. Why do we called NAND and NOR gates as universal gates?

Q3. Write the IC number for logic gates

Q4. What is meant by Nand & Nor Implementation?

Q5. What is K-Map?

Post Lab work:

Q1. Write a Verilog HDL program for the equation z= (a.b)+c. Also give its
truth table and draw the waveform. Generate *.ucf [user constraint file] by doing
P&R [Placement and Routing] simulation and implement in Nexys 3 – SPARTAN
6 FPGA kit.

Q2. What are the different types of Modeling?

 Q3. Write the Verilog Program for Ex-or and Ex-Nor using structural and
Behavioral Modeling.

Q4. Write Verilog program for Basic Flip-Flops and simulate using Xilinx.

MAX. MARKS
PARTICULARS
MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
COMPLETION 30
POSTLAB 30
RECORD 10
TOTAL 100

RESULT:
Exp. No. 2
DESIGN AND IMPLEMETATION OF ADDERS & MULTIPLIERS
Date:

Aim:
(i) To write a Verilog HDL program for
(a) Half Adder
(b) Full Adder
(c) Full Adder Using NAND Gate
(d) 8-bit Ripple carry adder using Full adder
(e) 8-bit Multiplier

(ii) To generate *.ucf [user constraint file] by doing P&R [Placement and Routing]
simulation and implement the design in Nexys 3 – SPARTAN 6 FPGA kit.

(iii) Test the blocks generated by using chipscope pro analyzer.

Tools Required:
1. PC with Xilinx Vivado System Edition S Ver 14.6
2. Spartan 6 FPGA Trainer Kit (Nexys3™ Board)

Procedure:
(i) Analyse the design specification, draw the logic diagram and truth table for the
given design specification.
(ii) Write the Verilog-HDL code for the design specification given.
(iii) Follow the procedure given in appendix-A for simulation and implementation.
(iv) Verify the simulation result with implementation result.

Theory:
Adder:
In electronics, an adder or summer is a digital circuit that performs addition of
numbers. In many computers and other kinds of processors, adders are used not only in
the arithmetic logic unit(s), but also in other parts of the processor, where they are used
to calculate addresses, table indices, and similar operations.
Half adder:

The half adder adds two single binary digits a and b. It has two outputs, sum and
carry. The carry signal represents an overflow into the next digit of a multi-digit
addition. Two half adders can be combined to make a full adder.
Half adder Circuit diagram: Truth table:

INPUT OUTPUT
i1 i2 sum c_out
0 0
0 1
Output Expression: 1 0

Sum= 1 1

Carry=

Verilog HDL Code for Half Adder

module HalfAddr(sum, c_out, i1, i2);

output sum, c_out;
input i1; input i2;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule

Full adder:

A full adder adds three one-bit numbers, often written as a, b, and cin; a and b
are the operands, and cin is a bit carried in from the previous less significant stage. The
full adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary
numbers. The circuit produces a two-bit output, output carry and sum.
Truth table:
INPUT OUTPUT
Circuit diagram: i2
i cin sum c_out
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
Output Expression:
1 1 1
Sum=

Carry=

Verilog HDL Code for Full Adder [Data flow model]:

[Note: use intermediate outputs x,y,z as wire]

module FullAddr(i1, i2, c_in, c_out, sum);

input i1,
i2, c_in;
output
c_out, sum;
wire
s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule
Ripple-carry adder:
It is possible to create a logical circuit using multiple full adders to add N-
bit numbers. Each full adder inputs a Cin, which is the Cout of the previous
adder. This kind of adder is called a ripple-carry adder, since each carry bit
"ripples" to the next full adder. Note that the first (and only the first) full adder
may be replaced by a half adder (under the assumption that Cin = 0).

The layout of a ripple-carry adder is simple, which allows for fast design time;
however, the ripple-carry adder is relatively slow, since each full adder must wait for
the carry bit to be calculated from the previous full adder.

Eight-bit Ripple carry adder using Full adder:

Verilog HDL code for 8 - bit Ripple carry adder using Full adder:
[Note: use array [6:0]c as wire, FA1 to FA8 as Full adder Name and also declare input and output
as array as shown in fig. i.e.,[7:0]a for 8-bit array of a]

module adder(s,cout,a,b,cin);
output[7:0]s;
output cout;
input[7:0]a,b;
input cin;
wire c1,c2,c3,c4,c5,c6,c7;
fulladd fa0(s[0],c1,a[0],b[0],cin);
fulladd
fa1(s[1],c2,a[1],b[1],c1);
fulladd
fa2(s[2],c3,a[2],b[2],c2);
fulladd
fa3(s[3],c4,a[3],b[3],c3);
fulladd
fa4(s[4],c5,a[4],b[4],c4);
fulladd
fa5(s[5],c6,a[5],b[5],c5);
fulladd
fa6(s[6],c7,a[6],b[6],c6);
fulladd
fa7(s[7],cout,a[7],b[7],c7);
endmodule

module fulladd(s,cout,a,b,cin);
output s,cout;
input a,b,cin;
xor (s,a,b,cin);
assign cout = ((a & b )|(b& cin)|( a & cin)) ;
endmodule
Simple 4-bit Multiplication:

Logic for Simple 4-bit Multiplication:

Theory:

A binary mult ip lier is an electronic circuit used in digital electronics, such

as a computer, to multiply two binary numbers. It is built using binary adders. A
variety of computer arithmetic techniques can be used to implement a digital
multiplier. Most techniques involve computing a set of partial products, and then
summing the partial products together. This process is similar to the method taught to
primary schoolchildren for conducting long multiplication on base-10 integers, but has
been modified here for application to a base-2 (binary) numeral system.
The method taught in school for multiplying decimal numbers is based on
calculating partial products, shifting them to the left and then adding them together.
The most difficult part is to obtain the partial products, as that involves multiplying a
long number by one digit (from 0 to 9):

123 x 456
=====
738 (this is 123 x 6)
615 (this is 123 x 5, shifted one position to the left)
+ 492 (this is 123 x 4, shifted two positions to the left)
=====
56088

Verilog Code for 4-bit Multiplication:

[Note: Ref. fig. for input, output and wire declaration]

Program:

module multi(m,a,b);
input [3:0]a;
input [3:0]b;
output [7:0]m;
wire [15:0]p;
wire [12:1]s;
wire [12:1]c;
and(p[0],a[0],b[0]);
and(p[1],a[1],b[0]);
and(p[2],a[0],b[1]);
and(p[3],a[2],b[0]);
and(p[4],a[1],b[1]);
and(p[5],a[0],b[2]);
and(p[6],a[3],b[0]);
 and(p[7],a[2],b[1]);
and(p[8],a[1],b[2]);
and(p[9],a[0],b[3]);
and(p[10],a[3],b[1]);
and(p[11],a[2],b[2]);
and(p[12],a[1],b[3]);
and(p[13],a[3],b[2]);
and(p[14],a[2],b[3]);
and(p[15],a[3],b[3]);
half ha1(s[1],c[1],p[1],p[2]);
half ha2(s[2],c[2],p[4],p[3]);
half ha3(s[3],c[3],p[7],p[6]);
full fa4(s[4],c[4],p[11],p[10]);
full fa5(s[5],c[5],p[14],p[13]);
full fa6(s[6],c[6],p[5],s[2]);
full fa7(s[7],c[7],p[8],s[3]);
full fa8(s[8],c[8],p[12],s[4]);
full fa9(s[9],c[9],p[9],s[7]);
half ha10(s[10],c[10],s[8]);
full fa11(s[11],c[11],s[5]);
full fa12(s[12],c[12],p[15]);
buf(m[0],p[0]);
buf(m[1],s[1]);
buf(m[2],s[6]);
buf(m[3],s[9]);
buf(m[4],s[10]);
buf(m[5],s[11]);
buf(m[6],s[12]);
buf(m[7],c[12]);
endmodule
 A binary computer does exactly the same, but with binary numbers. In binary
encoding each long number is multiplied by one digit (either 0 or 1), and that is
much easier than in decimal, as the product by 0 or 1 is just 0 or the same number.
Therefore, the multiplication of two binary numbers comes down to calculating partial
products (which are 0 or the first number), shifting them left, and
then adding them together (a binary addition, of course):

1011 (this is 11 in decimal)

x 1110 (this is 14 in decimal)
======
0000 (this is 1011 x 0)
1011 (this is 1011 x 1, shifted one position to the left)
1011 (this is 1011 x 1, shifted two positions to the left)
+ 1011 (this is 1011 x 1, shifted three positions to the left)
=========
10011010 (this is 154 in decimal)

Output Table:

a (Binary) b (Binary) p (Binary)

0000 0000
1011 1011
1011 1111
1111 1110
1100 1000
0100 1101

module half(s,co,x,y);
input x,y;
output s,co; xor (s,x,y);
and (co,x,y);
endmodule

module full(s,co,x,y,ci);
input x,y,ci;
output s,co;
wire s1,d1,d2;
half ha_1(s1,d1,x,y);
half ha_2(s,d2,s1,ci);
or or_gate(co,d2,d1);
endmodule
Pre Lab work:

Q1. Analyze the give logic and write the Verilog HDL code for 4-bit Multiplier [use
structural/ Gate level Modeling].

Q2. What is critical path?

Post Lab work:

Q1. How many Gates were used to design 4-bit multiplier?

Q2. How many half adders and full adders were used to design 4-bit multiplier?

Q3. What is the critical path of the design 4-bit multiplier?

Q3. Design 8-bit Multiplier using Verilog Module.

 MAX. MARKS
PARTICULARS
MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
30
COMPLETION
POSTLAB 30
RECORD 10
TOTAL 100

RESULT:
Exp. No. 3
DESIGN AND IMPLEMETATION OF UNIVERSAL SHIFT
Date: REGISTER

Aim:
To write a Verilog HDL program for Universal Shift Registers and implement it in
FPGA.

Tools Required:
1. PC with Xilinx Vivado System Edition S Ver 14.6
2. Spartan 6 FPGA Trainer Kit (Nexys3™ Board)

Procedure:
(i) Analyse the design specification, draw the logic diagram and truth table for the
given design specification.
(ii) Write the Verilog-HDL code for the design specification given.
(iii) Follow the procedure given in appendix-A for simulation and implementation.
(iv) Verify the simulation result with implementation result.

Theory:

Universal Shift Register is capable of converting input data into parallel or serial
which also does shifting of data bidirectional, unidirectional (SISO, SIPO, PISO,
PIPO) and also parallel load, this is called as Universal Shift Registers.
Shift registers are used as: Data Storage device, delay element, Communication lines,
digital electronic devices (Temporary data storage, data transfer, data manipulation,
counters,etc.
Logic Diagram for Universal Shift Register:

Truth table for Universal Shift Register:

MODE CONTROL
REGISTER OPERATION
S1 S0
0 0 NO CHANGE
0 1 SHIFT LEFT
1 0 SHIFT RIGHT
1 1 PARALLEL LOAD
Verilog HDL code for Universal Shift Register

Module USR (O, I, clk, reset, s, SINL, SINR)

Wire[3:0]w;
input[3:0]I;
input[3:0]s;
input clk;
input reset, SINL, SINR;
output [3:0]O;
reg [27:0] count = 0;
// MUX module calling
Mux_4_1 m1(w[0], s[1], s[0], I[0], SINL, O[1], O[0]);
Mux_4_1 m2(w[1], s[1], s[0], I[1], O[0], O[2], O[1]);
Mux_4_1 m3(w[0], s[2], s[0], I[2], O[1], O[3], O[2]);
Mux_4_1 m4(w[3], s[1], s[0], I[3], O[2], SINR, O[3]);
// DFF module calling
D_FF d1(O[0]), w[0], clk, reset);
D_FF d2(O[1]), w[1], clk, reset);
D_FF d3(O[2]), w[2], clk, reset);
D_FF d4(O[3]), w[3], clk, reset);
// Increment count on every clock endmodule
// sub module for D Flipflop
Module D_FF (q, d, clk, reset);
ouput reg q;
input d, clk, reset;
always@(posedge clk)
if (reset = = 1’b1) q<=1’b0;
else
q<=d;
endmodule
// sub module for 4x1 MUX
module mux_ 4_1(y, s1, s0, i3, i2, i1, i0);
output reg y;
input i3, i2, i1, i0;
input s1, s0;
always@(s1, s0, i3, i2, i1, i0)
begin
if (s0 = = 0 & s1 = = 0)
y = i0;
else if (s0 = = 0 & s1 = = 1)
y = i1;
else if (s0 = = 1 & s1 = = 0)
y = i2;
else if (s0 = = 1 & s1 = = 1)
y = i3;
end
endmodule

Pre Lab Work:

Q1. Draw the Logic Diagram and truth table for 8-bit shift registers.
Q2. What are the different types of Shift registers?

Q3. What is meant by registers?

Post Lab Work:

Q1. Write Verilog HDL code for 4-bit Shift registers using structural modeling.

Q2. Write HDL program for PISO, SISO, SIPO and PIPO shift registers.

Q3. Write program for memories.

 MAX. MARKS
PARTICULARS MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
30
COMPLETION
POSTLAB 30
RECORD 10
TOTAL 100

RESULT:
 Exp. No. 4
DESIGN AND IMPLEMETATION OF MEMORIES
Date:

Aim:
(i) To write a Verilog HDL program for a given Memory.
(ii) To generate *.ucf [user constraint file] by doing P&R [Placement and Routing]
simulation and implement the design in Nexys 3 – SPARTAN 6 FPGA kit.
(iii) Test the blocks generated by using chipscope pro analyzer.
Tools Required:
1. PC with Xilinx Vivado System Edition S Ver 14.6
2. Spartan 6 FPGA Trainer Kit (Nexys3™ Board)

Procedure:
(i) Analyse the design specification, draw the logic diagram and truth table for the
given design specification.
(ii) Write the Verilog-HDL code for the design specification given.
(iii) Follow the procedure given in appendix-A for simulation and implementation.
(iv) Verify the simulation result with implementation result.

Theory:
The single-port memory is basically the design as per your defined specifications.
Then, as per the specified width and depth, define the memory block that can also be
verified using field programmable gate array (FPGA) boards. Design hierarchy also
plays an important role in designing the basic building blocks required in each step
of verification. In this project we design a 64-bit x 8-bit, which is a single-port design
with common read and write addresses in Verilog. While designing this project in
ModelSim and test benches, follow the guidelines mentioned below:

1. When modelling sequential logic, use non-blocking assignments

2. When modelling latches, use non-blocking assignments
3. When modelling combinational logic with an always block, use blocking
assignments
4. When modelling both sequential and combinational logic within the same
always block, use non-blocking assignments
5. Do not mix blocking and non-blocking assignments in the same always block
6. Do not make assignments to the same variable from more than one always
Verilog code for Memory:

module single_port_ram

(
input [7:0] data,
input [5:0] addr,
input we, clk,
output [7:0] q
);

// Declare the RAM variable

reg [7:0] ram[63:0];

// Variable to hold the registered read address

reg [5:0] addr_reg;

always @ (posedge clk)

begin
// Write
if (we)
ram[addr] <= data;

addr_reg <= addr;

end

// Continuous assignment implies read returns NEW data.

// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr_reg];

endmodule
Pre lab Questions:
1. What is Memory?

2. What are the types of memory?

3. What are the functions performed by memory?

Post lab Questions:

1. Write a verilog program for 8 x 8 memory.
2. Write Verilog program for SRAM & DRAM.
3. Write Verilog program for PROM.
 MAX. MARKS
PARTICULARS
MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
COMPLETION 30
POSTLAB 30
RECORD 10
TOTAL 100

RESULT:
Mealy State Machine

Moore State Machine

Exp. No. 5
DESIGN AND IMPLEMETATION OF STATE MACHINE
Date:

Aim:
(i) To write a Verilog HDL program for a given State Machine.
(ii) To generate *.ucf [user constraint file] by doing P&R [Placement and Routing]
simulation and implement the design in Nexys 3 – SPARTAN 6 FPGA kit.
(iii) Test the blocks generated by using chipscope pro analyzer.
Tools Required:
1. PC with Xilinx Vivado System Edition S Ver 14.6
2. Spartan 6 FPGA Trainer Kit (Nexys3™ Board)

Procedure:
(i) Analyse the design specification, draw the logic diagram and truth table for the
given design specification.
(ii) Write the Verilog-HDL code for the design specification given.
(iii) Follow the procedure given in appendix-A for simulation and implementation.
(iv) Verify the simulation result with implementation result.

Designing Finite State Machines (FSM):

Designing a synchronous finite state machine (FSM) is a common task for a

digital logic engineer. A finite state machine can be divided in to two types: Moore and
Mealy state machines. Fig. 1 has the general structure for Moore and Fig. 2 has general
structure for Mealy. The current state of the machine is stored in the state memory, a set
of n flip-flops clocked by a single clock signal (hence “synchronous” state machine). The
state vector (also current state or just state) is the value currently stored by the state
memory. The next state of the machine is a function of the state vector in Moore;
function of state vector and the inputs in Mealy.

Verilog Coding:
The logic in a state machine is described using a case statement or the equivalent
(e.g., if-else). All possible combinations of current state and inputs are enumerated, and
the appropriate values are specified for next state and the outputs. A state machine may
be coded as in Code 1 using two separate case statements, or, as in code 2, using only
one.
State diagram for Moore machine:

Fig. 3

State diagram for Mealy Machine:

A single case statement may be preferred for Mealy machines where the outputs depend
on the state transition rather than just the current state.
Consider the case of a circuit to detect a pair of 1's or 0's in the single bit input. That
is, input will be a series of one's and zero's. If two one's or two zero's comes one after
another, output should go high. Otherwise output should be low.
Here is a Moore type state transition diagram [Fig. 3] for the circuit. When reset,
state goes to 00; If input is 1, state will be 01 and if input is 0, state goes to 10. State will
be 11 if input repeats. After state 11, goes to 10 state or 01 depending on the inp, since
overlapping pair should not be considered. That is, if 111 come, it should consider only
one pair.
Now, let us re-design the above circuit using Mealy style state machine is shown
in fig. 4. Output depends on both state and input. State transition diagram is as follows:
When reset, state becomes idle, that is 00. Next, if 1 comes, state becomes 01 and
if 0 comes state becomes 10 with output 0. We have showed input 1, output 0 as 1/0. If
input bit repeats, output becomes 1 and state goes to 00.
Now, let us discuss difference between Moore and Mealy state machines
depending on these codes.

 Moore state machine is easier to design than Mealy. First design the states
depending on the previous state and input. Then design output only depending on
state. Whereas in Mealy, you have to consider both state and input while designing
the output.
 Mealy state machine uses less state than the Moore. Since inputs influence the
output in the immediate clock, memory needed to remember the input is less. So,
it uses less flip flops and hence circuit is simpler.
 In Mealy, output changes immediately when the input changes. We can observe
this point when you simulate the codes above. In Moore example, output
becomes high in the clock next to the clock in which state goes 11. So, Mealy is
faster than Moore. Mealy gives immediate response to input and Moore gives
response in the next clock.
Verilog HDL code for Moore state Machine:

module moore_verilog_code(out, in, rst, clk);

output out; input
in; input clk, rst;
reg out; reg[1:0]
state;
parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
always @(posedge clk or negedge rst) if(rst==0)
begin state=s0; out=0; end
else begin case
(state)
s0: begin out=0; if(in==0) state=s1; else state=s0; end s1:
begin out=0; if(in==0) state=s1; else state=s2; end s2:
begin out=0; if(in==0) state=s3; else state=s0; end s3:
begin out=1; if(in==0) state=s1; else state=s2; end default:
state=s0;
endcase
end endmodule

Verilog HDL code for Mealy State Machine:

module mealy_verilog_code(out, in, rst, clk);

output out; input
in; input clk, rst;
reg out; reg[1:0]
state;
parameters0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
always @(posedge clk or negedge rst)
if(rst==0) begin state=s0; out=0; end else
begin
case (state)
s0: if(in==0) begin out=0; state=s1; end
else begin out=0; state=s0; end
s1: if(in==0) beginout=0; state=s1; end else
begin out=0; state=s2; end
Pre Lab Question:

Q1. Design a state Machine for a sequence detector which can detect a sequence of 110
on its input X. When this sequence is detected the output Y will be equal to 1 for exactly
one clock cycle.

Post Lab Question:

Q1. Write a Verilog HDL code for Q1 given above.

 s2: if(in==0) begin out=0; state=s3; end
else begin out=0; state=s0; end
s3: if(in==0) begin out=0; state=s1; end
else begin out=1; state=s2; end
default: state=s0;
endcase
end
endmodule

MAX. MARKS
PARTICULARS MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
COMPLETION 30
POSTLAB 30
RECORD 10
TOTAL 100

RESULT:
 Exp. No. 7
DESIGN AND IMPLEMETATION OF 4-BIT SYNCHRNOUS
Date: COUNTER USING FLIP-FLOPS

Aim:
To design and simulate a 4-bit synchronous counters using Flip-flops.

Tools Required:
 PC with Mentor Graphics Tool/ Microwind Tool or any equivalent software.

Procedure:
1. Draw the schematic for CMOS Logic gates.
2. Follow the procedure given in appendix-B for schematic design Dsch tool.
3. Generate Verilog HDL file for automatic Layout design.
4. Follow the procedure given in appendix-B for generation and simulation of
Layout.
5. Verify the simulation result.

Theory:

Synchronous Counters are so called because the clock input of all the individual flip-flops
within the counter are all clocked together at the same time by the same clock signal. It
can be seen above, that the external clock pulses (pulses to be counted) are fed directly to
each of the JK Flip flops in the counter chain and that both the J and K inputs are all tied
together in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they
connected HIGH, logic “1” allowing the flip- flop to toggle on every clock pulse. Then the
synchronous counter follows a predetermined sequence of states in response to the
common clock signal, advancing one state for each pulse.

The J and K inputs of flip-flop FFB are connected directly to the output QA of flip- flop
FFA, but the J and K inputs of flip-flops FFC and FFD are driven from separate
AND gates which are also supplied with signals from the input and output of the
previous stage. These additional AND gates generate the required logic for the JK inputs
of the next stage.
Up/Down Counter
module BCDupdown(Clk, reset, UpOrDown, Count ); // module Declaration
// input and output declarations
input Clk,reset,UpOrDown;
output [3 : 0] Count;
reg [3 : 0] Count = 0;
always @(posedge(Clk),UpOrDown)
begin
if(reset == 1)
Count <= 0;
else
begin
if(UpOrDown == 1) // High for Up Counter and Low for Down Counter
begin
if(Count == 15)
Count <= 0;
else
Count <= Count + 1;
end
else
begin
if(Count == 0)
Count <= 15;
else
Count <= Count - 1;
end
end
end
endmodule
Pre lab Questions:

1. What is Counter?

2. What are different types of counters?

Post Lab Questions:

1. Differentiate Synchronous and Asynchronous counters.

2. Design counters using other than JK flipflops

 MAX. MARKS
PARTICULARS
MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
COMPLETION 30
POSTLAB 30
RECORD 10
TOTAL 100

Result:
 Exp. No. 8
DESIGN AND SIMULATE CMOS BASIC GATES & AMP;
Date: FLIP-FLOPS

Aim:

To design and simulate a CMOS Basic logic gates and Flip flops using digital using
digital flow

Tools Required:

1. PC with Microwind Tool/ Mentor Graphics Tool or any equivalent software.

Procedure:
1. Draw the schematic for CMOS Logic gates.

2. Follow the procedure given in appendix-B for schematic design Dsch tool.

3. Generate Verilog HDL file for automatic Layout design.

4. Follow the procedure given in appendix-B for generation and simulation of

Layout.

5. Verify the simulation result.

Pre Lab Questions:

1. Write the Switching characteristics of CMOS Inverter.

2. Write down the conditions for the PMOS & NMOS transistors in DC
characteristics of CMOS Inverter.

3. How to design AND and OR using NAND-NOR Implementation?

Circuit diagram:
NAND Gate:

NOR gate:
Post Lab Questions:

1. Design AND logic gate using Microwind.

2. Design OR logic gate using Microwind.
3. Design and Implement XOR & XNOR logic gates
4. Design and Implement schematic for Flip-flops.

MAX. MARKS
PARTICULARS
MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
30
COMPLETION
POSTLAB 30
RECORD 10
TOTAL 100

Result:
 Exp. No. 9
DESIGN AND IMPLEMETATION OF 4-BIT SYNCHRNOUS
Date: COUNTER USING FLIP-FLOPS

Aim:

To design and simulate a 4-bit synchronous counters using Flip-flops.

Tools Required:
 PC with Mentor
 Graphics Tool/ Microwind Tool or any equivalent software.

Procedure:
1. Draw the schematic for CMOS Logic gates.
2. Follow the procedure given in appendix-B for schematic design Dsch tool.
3. Generate Verilog HDL file for automatic Layout design.
4. Follow the procedure given in appendix-B for generation and simulation of
Layout.
5. Verify the simulation result.

Theory:

Synchronous Counters are so called because the clock input of all the individual flip-flops
within the counter are all clocked together at the same time by the same clock signal. It can be
seen above, that the external clock pulses (pulses to be counted) are fed directly to each of the
JK Flip flops in the counter chain and that both the J and K inputs are all tied together in toggle
mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic “1”
allowing the flip- flop to toggle on every clock pulse. Then the synchronous counter follows a
predetermined sequence of states in response to the common clock signal, advancing one state
for each pulse.

The J and K inputs of flip-flop FFB are connected directly to the output QA of flip- flop FFA,
but the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates
which are also supplied with signals from the input and output of the previous stage.
These additional AND gates generate the required logic for the JK inputs of the next stage.
Pre lab Questions:

1. What is Counter?

2. What are differ

ent types of counters?

Post Lab Questions:

1. Differentiate Synchronous and Asynchronous counters.

2. Design counters using other than JK flipflops

 MAX. MARKS
PARTICULARS
MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
30
COMPLETION
POSTLAB 30
RECORD 10
TOTAL 100

Result:
Exp. No. 10
DESIGN AND SIMULATE A CMOS INVERTING/NON
Date: INVERTING AMPLIFIER

Aim:
To design and simulate a CMOS Inverting Amplifiers.

Tools Required:

1. PC with Mentor Graphics Tool/ Microwind Tool or any equivalent software.

Procedure:

1. Draw the schematic for CMOS Inverting Amplifier.

2. Follow the procedure given in appendix-B for schematic design Dsch tool.
3. Generate Verilog HDL file for automatic Layout design.
4. Follow the procedure given in appendix-B for generation and simulation of
Layout.
5. Verify the simulation result.

Theory:

The inverter is the basic gain stage of CMOS analog circuits. In this the inverter
uses the common source configuration with active resistor as a load or a current
source as a load. The various configurations of CMOS inverter amplifier are :

1) active load inverter

2) Current source load inverter
3) Push-pull inverter
Circuit diagram:
Pre lab Questions:

1. What is Amplifier?
2. Differentiate Inverting and Non-Inverting Amplifier.
3. Draw the diagram for Amplifier using Transistor.

Post lab Questions:

1. Design Amplifiers using Transistors.
2. Calculate the Gain for the specified values.
3. Design Amplifiers using Op-amp.
4. Calculate the Gain for the specified values.

MAX. MARKS
PARTICULARS
MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
30
COMPLETION
POSTLAB 30
RECORD 10
TOTAL 100

Result:
Exp. No. 11
DESIGN AND SIMULATE COMMON SOURCE, COMMON
Date: GATE AND COMMON DRAIN AMPLIFIER

Aim:

To design and simulate basic Common Source, Common drain and Common gate Amplifier.

Tools Required:

PC with Mentor Graphics Tool/ Microwind Tool or any equivalent software.

Procedure:

1. Draw the schematic for Common Source/drain/gate Amplifier.

2. Follow the procedure given in appendix-B for schematic design Dsch tool.
3. Generate Verilog HDL file for automatic Layout design.
4. Follow the procedure given in appendix-B for generation and simulation of
Layout.
5. Verify the simulation result.

Theory:

In electronics, a common-source amplifier is one of three basic single-stage field-effect

transistor (FET) amplifier topologies, typically used as a voltage or
transconductance amplifier. The easiest way to tell if a FET is common source, common
drain, or common gate is to examine where the signal enters and leaves. The remaining
terminal is what is known as "common". A common-drain amplifier, also known as
a source follower, is one of three basic single-stage field effect transistor (FET) amplifier
topologies, typically used as a voltage buffer. In this circuit (NMOS) the gate terminal of
the transistor serves as the input, the source is the output, and the drain is common to
both (input and output), hence its name. The analogous bipolar junction transistor circuit
is the common-collector amplifier. This circuit is also commonly called a "stabilizer."
Figure: Common Gate, Common Source and Common Drain Amplifier
Pre lab Questions:
1. What is Common Gate, Common Source and Common Drain amplifier?
2. How to differentiate among those?
3. What is Transfer characteristics?
4. What is Frequency response of above said amplifiers?
5. What is small signal analysis for above said amplifiers?

Post lab Questions:

1. Obtain Frequency response of above said amplifiers?
2. Calculate small signal analysis for above said amplifiers.
3. Compare and analysis the output for all three amplifiers.

MAX. MARKS
PARTICULARS
MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
COMPLETION 30
POSTLAB 30
RECORD 10
TOTAL 100

Result:
Exp. No. 12
DESIGN AND SIMULATE SIMPLE 5 TRANSISTOR
Date: DIFFERENTIAL AMPLIFIER

Aim:
(i) To design and Simulate a Simple 5 Transistor Differential amplifier and
generate Verilog HDL code for the design
(ii) Synthesis and Layout generation of simple 5 transistor Differential
Amplifier using standard cell based approach.
(iii) Analyze the static timing, area and power consumption of the circuit
designed.
(iv) Calculate Gain, ICMR and CMRR for the circuit simulated.

Tools Required:
1. PC with Mentor Graphics Tool/ Microwind Tool or any equivalent software.

Procedure:
1. Draw the schematic for MOS Differential Amplifier.
2. Follow the procedure given in appendix-B for schematic design Dsch tool.
3. Generate Verilog HDL file for automatic Layout design.
4. Follow the procedure given in appendix-B for generation and simulation of
Layout.
5. Verify the simulation result.

Formula:

ICMR =

CMRR =

Gain =
Circuit Diagram

Pre Lab Work:

Q1. Write the formula to find Gain, ICMR, CMRR for the 5 transistor differential amplifier in
the space provided.
Q2. Draw the CMOS Inverter Schematic.

1. CMRR = 20log|Ao/Ac| dB.

2. The ICMR is given by

3. Differential Amplifier Gain AD is given by. AD = VOUT / (V1 – V2) = R2 / R1

Post Lab Work:
Q1. Generate Verilog HDL code for the Iverter Schematic, generate layout using standard
cell based.

Q2. Implement a CMOS inverter in the following three cases and analyze the
result in tabulation.

Case 1: PMOS: W=0.600um, L=0.120um & NMOS: W=0.600um,

L=0.120um. Case 2: PMOS: W=0.120um, L=0.120um & NMOS:

W=0.600um, L=0.120um.

Case 3: PMOS: W=0.600um, L=0.120um & NMOS: W=0.120um, L=0.120um.

120nm Technology
Standard cell
Parameter based design Case 1 Case 2 Case 3

Rise time

Fall time

Delay

Power
Consumption

Surface Area
 MAX. MARKS
PARTICULARS
MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
COMPLETION 30
POSTLAB 30
RECORD 10
TOTAL 100

Result:
 Exp. No. 13
DESIGN AND IMPLEMENTATION OF ALU
Date:

Aim:
(i) To write a Verilog HDL program for ALU.
(ii) To generate *.ucf [user constraint file] by doing P&R [Placement and Routing]
Simulation and implement the design in Nexys 3 – SPARTAN 6 FPGA kit.
Tools Required:
1. PC with Xilinx Vivado System Edition S Ver 14.6
2. Spartan 6 FPGA Trainer Kit (Nexys3™ Board)

Procedure:
(i) Analyse the design specification, draw the logic diagram and truth table for the
given design specification.
(ii) Write the Verilog-HDL code for the design specification given.
(iii) Follow the procedure given in appendix-A for simulation and implementation.
(iv) Verify the simulation result with implementation result.

Verilog code for ALU:

module ALU(A,B,Op,R );

input [7:0] A,B;

input [2:0] Op;

output [7:0] R;

wire [7:0] Reg1,Reg2;

reg [7:0] Reg3;

assign Reg1 = A;

assign Reg2 = B;

assign R = Reg3;

always @(Op or Reg1 or Reg2)

begin

case (Op)

0 : Reg3 = Reg1 + Reg2; //addition

1 : Reg3 = Reg1 - Reg2; //subtraction

ALU:

Truth table for ALU:

A B Op R
2 : Reg3 = ~Reg1; //NOT gate

3 : Reg3 = ~(Reg1 & Reg2); //NAND gate

4 : Reg3 = ~(Reg1 | Reg2); //NOR gate

5 : Reg3 = Reg1 & Reg2; //AND gate

6 : Reg3 = Reg1 | Reg2; //OR gate

7 : Reg3 = Reg1 ^ Reg2; //XOR gate

endcase
end
endmodule

Pre Lab Work:

Q1. Read the operation of ALU and analyze the truth table.

Post Lab Work:

Q1. Draw the logic diagram of 16 bit ALU using MUX.

Q2. Write the program for the MUX and DEMUX in verilog.

MAX. MARKS
PARTICULARS
MARKS OBTAINED
PRELAB PREPARATION 30
PERFORMANCE /
COMPLETION 30
POSTLAB 30
RECORD 10
TOTAL 100

Result:
 APPENDIX - A
Steps for Functional Verification using Xilinx ISE Design Suite 14.6
1. Open ISE Design Suite 14.6

2. Open New Project

3. Enter Name of the project and select Top-level source type and click Next

4. Select device and project properties as specified for SPARTAN-6 NEXYS 3 Board, Click Next and Finish
5. Select Implementation and Right click xc6slx16-3csg324 and give New source

6. Select Verilog Module and give File name (Module name) and Next
7. Give name of input and output Ports and select direction (If necessary specify MSB and LSB) and click
Next, Finish

8. Type the program in the window opened

9. Run Check Syntax and view RTL schematic

10. If the Process "Check Syntax" completed and RTL was viewed successfully
 RTL View

11. Select ‘Simulation’ and filename.v (here basicgates.v) file

12. Run Simulate Behavioral Model in Process Window

13. After Running, a window will open to verify the simulation output for ‘Functional Verification’

14. Force the Input Values for all the Input ports specified in the program by right click the port name
and ‘Force Constant’ in Objects window

112
15. After assigning Inputs to the ports ‘Run’ the simulation by forcing the different input values (make
run length as 1ps for clear view of waveform).

For Downloading to SPARTAN-6 NEXYS 3 (G enera tin g “.U cf ” and “ .bit

“ f il e)
Continue procedure 1 to 10 as in functional verification

11. Create User constraint File

12. Give IO Port number by referring the Nexus3 .ucfmaster and save the window (.ucf file
generation)

13. Run Generate programming file in process window (.bit file generation)

`
14. Open Adept

15. Browse for .bit file in project directory and open

16. Program the selected .bit file and verify the output with SPARTAN-6 Kit
 APPENDIX B
Procedure to draw the schematic [Dssh35]
1. Open Dsch35

2. A window will open for drawing a schematic.

3. Select foundry for the design

4. For 120nm technology we are selecting cmos012.tec

5. Foundry will be shown in right bottom corner of the window

6. Place the component from symbol window, Make connections, Save the file and Make
the Verilog file.
 7. Give ok to save the file in your folder where you saved your schematic.

Procedure for Layout Generation: [Microwind35]

1. Open Microwind35

2. A window will open for drawing Layout.

 3. Select foundry for 120nm

Procedure for Compiling Verilog HDL file:

1. Go to compile  Compile Verilog file

2. Select Verilog file open compile and back to editor to see the Layout.
Make necessary changes for input and Run the simulation to see the output.

Steps for drawing Layout by semicustom design:

1. Select MOS generator from the Palette window and select nMOS/pMOS as per the
requirement by assigning Width, Length and number of fingers and place in the design
window.
2. Make connections as per the design, Run the simulation and analyze the result.