8-Channel, 16-Bit, Simultaneous Sampling

ADC with Power Scaling, 110.8 kHz BW

Data Sheet AD7761
FEATURES Linear phase digital filter
Precision ac and dc performance Low latency sinc5 filter
8-channel simultaneous sampling Wideband brick wall filter: ±0.005 dB ripple to 102.4 kHz
256 kSPS ADC ODR per channel Analog input precharge buffers
97.7 dB dynamic range Power supply
110.8 kHz input bandwidth (−3 dB BW) AVDD1 = 5 V, AVDD2 = 2.25 V to 5.0 V
−120 dB THD, typical IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V
±1 LSB INL, ±1 LSB offset error, ±5 LSB gain error 64-lead LQFP package, no exposed pad
Optimized power dissipation vs. noise vs. input bandwidth Temperature range: −40°C to +105°C
Selectable power, speed, and input bandwidth APPLICATIONS
Fast (highest speed): 110.8 kHz BW, 51.5 mW per channel
Data acquisition systems: USB/PXI/Ethernet
Median (half speed): 55.4 kHz BW, 27.5 mW per channel
Instrumentation and industrial control loops
Low power (lowest power): 13.8 kHz BW, 9.375 mW per
Audio testing and measurement
channel
Vibration and asset condition monitoring
Input BW range: dc to 110.8 kHz
3-phase power quality analysis
Programmable input bandwidth/sampling rates
Sonar
CRC error checking on data interface
High precision medical electroencephalogram (EEG)/
Daisy-chaining
electromyography (EMG)/electrocardiogram (ECG)
FUNCTIONAL BLOCK DIAGRAM
AVDD1A, AVDD2A, REGCAPA,
AVDD1B REFx+ REFx– AVDD2B REGCAPB DGND IOVDD DREGCAP

BUFFERED
VCM
PRECHARGE 1.8V 1.8V
VCM VCM ×8 REFERENCE LDO LDO
BUFFERS SYNC_IN
SYNC_OUT
START
AIN0+ P OFFSET,
Σ-Δ DIGITAL RESET
CH 0 ADC GAIN PHASE
AIN0– P FILTER CORRECTION FORMAT1
ENGINE
FORMAT0
AIN1+ P OFFSET,
CH 1 Σ-Δ
ADC GAIN PHASE
AIN1– P CORRECTION ADC
OUTPUT DRDY
SINC5 DATA
AIN2+ P LOW LATENCY SERIAL DCLK
Σ-Δ FILTER OFFSET,
CH 2 GAIN PHASE INTERFACE
ADC DOUT0
AIN2– P CORRECTION
DOUT1
AIN3+ P DOUT2
CH 3 Σ-Δ OFFSET,
DOUT3
ADC GAIN PHASE
AIN3– P CORRECTION DOUT4
WIDEBAND DOUT5
AIN4+ P LOW RIPPLE DOUT6
CH 4 Σ-Δ FILTER
OFFSET,
ADC GAIN PHASE DOUT7
AIN4– P CORRECTION

AIN5+ P
CH 5 Σ-Δ OFFSET,
ADC GAIN PHASE
AIN5– P CORRECTION ST0/CS
SPI
CONTROL ST1/SCLK
AIN6+ P INTERFACE DEC0/SDO
Σ-Δ OFFSET,
CH 6 GAIN PHASE DEC1/SDI
ADC
AIN6– P CORRECTION

AIN7+ P OFFSET,
CH 7 Σ-Δ GAIN PHASE PIN/SPI
ADC CORRECTION
AIN7– P
×16 ANALOG INPUT
PRECHARGE BUFFERS (P)
AD7761
14285-001

AVSS XTAL2/MCLK XTAL1 MODE3/GPIO3 FILTER/GPIO4

TO
MODE0/GPIO0

Figure 1.

Rev. A Document Feedback

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AD7761 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Setting the Format of Data Output .......................................... 49
Applications ....................................................................................... 1 ADC Conversion Output: Header and Data .......................... 50
Functional Block Diagram .............................................................. 1 Functionality ................................................................................... 59
Revision History ............................................................................... 3 GPIO Functionality .................................................................... 59
General Description ......................................................................... 4 Register Map Details (SPI Control) ............................................. 60
Specifications..................................................................................... 5 Register Map ............................................................................... 60
Timing Specifications ................................................................ 10 Channel Standby Register ......................................................... 62
1.8 V IOVDD Timing Specifications ....................................... 11 Channel Mode A Register ......................................................... 63
Absolute Maximum Ratings.......................................................... 15 Channel Mode B Register ......................................................... 63
Thermal Resistance .................................................................... 15 Channel Mode Select Register .................................................. 64
ESD Caution ................................................................................ 15 Power Mode Select Register ...................................................... 64
Pin Configuration and Function Descriptions ........................... 16 General Device Configuration Register .................................. 65
Typical Performance Characteristics ........................................... 20 Data Control: Soft Reset, Sync, and Single-Shot Control
Terminology .................................................................................... 26 Register ........................................................................................ 66

Theory of Operation ...................................................................... 27 Interface Configuration Register.............................................. 66

Clocking, Sampling Tree, and Power Scaling ............................. 27 Digital Filter RAM Built in Self Test (BIST) Register ............ 67

Noise Performance and Resolution.......................................... 28 Status Register ............................................................................. 67

Applications Information .............................................................. 30 Revision Identification Register ............................................... 68

Power Supplies ............................................................................ 31 GPIO Control Register .............................................................. 68

Device Configuration ................................................................ 32 GPIO Write Data Register ......................................................... 69

Pin Control Mode ....................................................................... 32 GPIO Read Data Register .......................................................... 69

SPI Control .................................................................................. 35 Analog Input Precharge Buffer Enable Register Channel 0 to
Channel 3 .................................................................................... 69
SPI Control Functionality ......................................................... 36
Analog Input Precharge Buffer Enable Register Channel 4 to
SPI Control Mode Extra Diagnostic Features ........................ 38 Channel 7 .................................................................................... 70
Circuit Information ........................................................................ 39 Positive Reference Precharge Buffer Enable Register ............ 70
Core Signal Chain....................................................................... 39 Negative Reference Precharge Buffer Enable Register .......... 71
Analog Inputs .............................................................................. 40 Offset Registers ........................................................................... 71
VCM ............................................................................................. 41 Gain Registers ............................................................................. 72
Reference Input ........................................................................... 42 Sync Phase Offset Registers ...................................................... 72
Clock Selection ........................................................................... 42 ADC Diagnostic Receive Select Register ................................ 72
Digital Filtering ........................................................................... 42 ADC Diagnostic Control Register ........................................... 73
Decimation Rate Control .......................................................... 46 Modulator Delay Control Register........................................... 74
Antialiasing ................................................................................. 46 Chopping Control Register ....................................................... 74
Calibration ................................................................................... 48 Outline Dimensions ....................................................................... 75
Data Interface .................................................................................. 49 Ordering Guide .......................................................................... 75

Rev. A | Page 2 of 75
Data Sheet AD7761
REVISION HISTORY
9/2017—Rev. 0 to Rev. A Moved Table 26................................................................................ 45
Changed Focus Mode to Low Power Mode ............... Throughout Changes to Modulator Saturation Point Section ........................ 47
Changes to Table 1 ............................................................................ 5 Added Figure 68 .............................................................................. 47
Changes to Figure 2.........................................................................13 Changes to Bit 7 Bit Name, Table 31, and ERROR_FLAGGED
Changes to Thermal Resistance Section and Table 7 .................15 Section .............................................................................................. 50
Changes to Table 8 ..........................................................................16 Changes to Data Interface: One-Shot Conversion Operation
Changes to Figure 47 ......................................................................27 Section .............................................................................................. 53
Changes to Figure 48 ......................................................................30 Changes to CRC Check on Data Interface Section .................... 55
Changes to MCLK Source Selection Section ...............................37 Added CRC Code Example Section ............................................. 56
Changes to Analog Input Precharge Buffers Section .................38 Change to Register 0x05, Bit 6, Table 33 ...................................... 60
Changes to Analog Inputs Section ................................................40 Changes to Table 39 ........................................................................ 65
Added Figure 61; Renumbered Sequentially ...............................41 Changes to Analog Input Precharge Buffer Enable Register
Changes to Table 24 ........................................................................41 Channel 0 to Channel 3 Section .................................................... 69
Changes to Reference Input Section .............................................42 Changes to Analog Input Precharge Buffer Enable Register
Added Figure 62 ..............................................................................42 Channel 4 to Channel 7 Section .................................................... 70
Added Filter Settling Time Section ...............................................43
Changes to Wideband Low Ripple Filter Section .......................43 4/2016—Revision 0: Initial Version
Moved Table 25 ................................................................................44

Rev. A | Page 3 of 75
AD7761 Data Sheet

GENERAL DESCRIPTION
The AD7761 is an 8-channel, simultaneous sampling sigma-delta The wideband and sinc5 filters can be selected and run on a per
(Σ-Δ) analog-to-digital converter (ADC) with a Σ-Δ modulator channel basis.
and digital filter per channel, enabling synchronized sampling of ac Within these filter options, the user can improve the dynamic
and dc signals. range by selecting from decimation rates of ×32, ×64, ×128,
The AD7761 achieves 97.7 dB dynamic range at a maximum ×256, ×512, and ×1024. The ability to vary the decimation
input bandwidth of 110.8 kHz, combined with typical performance filtering optimizes noise performance to the required input
of ±1 LSB integral nonlinearity (INL), ±1 LSB offset error, and bandwidth.
±5 LSB gain error. Embedded analog functionality on each ADC channel makes
The AD7761 user can trade off input bandwidth, output data rate, design easier, such as a precharge buffer on each analog input
and power dissipation. Select one of three power modes to optimize that reduces analog input current and a precharge reference
the device for noise targets and power consumption. The buffer per channel reduces input current and glitches on the
flexibility of the AD7761 allows it to become a reusable platform reference input terminals.
for low power dc and high performance ac measurement The device operates with a 5 V AVDD1A and AVDD1B supply,
modules. a 2.25 V to 5.0 V AVDD2A and AVDD2B supply, and a 2.5 V to
The AD7761 has three modes: fast mode (256 kSPS maximum, 3.3 V or 1.8 V IOVDD supply (see the 1.8 V IOVDD Operation
110.8 kHz input bandwidth, 51.5 mW per channel), median section for specific requirements for operating at 1.8 V IOVDD).
mode (128 kSPS maximum, 55.4 kHz input bandwidth, 27.5 mW The device requires an external reference; the absolute input
per channel) and low power mode (32 kSPS maximum, 13.8 kHz reference voltage range is 1 V to AVDD1 − AVSS.
input bandwidth, 9.375 mW per channel).
For the purposes of clarity within this data sheet, the AVDD1A
The AD7761 offers extensive digital filtering capabilities, such as and AVDD1B supplies are referred to as AVDD1 and the AVDD2A
a wideband, low ±0.005 dB pass-band ripple, antialiasing low- and AVDD2B supplies are referred to as AVDD2. For the
pass filter with sharp roll-off, and 105 dB attenuation at the negative supplies, AVSS refers to the AVSS1A, AVSS1B,
Nyquist frequency. AVSS2A, AVSS2B, and AVSS pins.
Frequency domain measurements can use the wideband linear The specified operating temperature range is −40°C to +105°C.
phase filter. This filter has a flat pass band (±0.005 dB ripple) The device is housed in a 10 mm × 10 mm 64-lead LQFP package
from dc to 102.4 kHz at 256 kSPS, from dc to 51.2 kHz at with a 12 mm × 12 mm printed circuit board (PCB) footprint.
128 kSPS, or from dc to 12.8 kHz at 32 kSPS.
Throughout this data sheet, multifunction pins, such as
The AD7761 also offers sinc response via a sinc5 filter, a low XTAL2/MCLK, are referred to either by the entire pin name or
latency path for low bandwidth, and low noise measurements. by a single function of the pin, for example MCLK, when only
that function is relevant.

Rev. A | Page 4 of 75
Data Sheet AD7761

SPECIFICATIONS
AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 1.72 V to 1.88 V and 2.25 V to 3.6 V, AVSS =
DGND = 0 V, REFx+ = 4.096 V and REFx− = 0 V, MCLK = 32.768 MHz, analog input precharge buffers on, reference precharge buffers
off, wideband filter, fCHOP = fMOD/32, TA = −40°C to +105°C, unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR), per Fast 8 256 kSPS
Channel 1
Median 4 128 kSPS
Low power 1 32 kSPS
−3 dB Bandwidth (BW) Fast, wideband filter 110.8 kHz
Median, wideband filter 55.4 kHz
Low power, wideband filter 13.8 kHz
Data Output Coding Twos complement, MSB first
No Missing Codes 2 16 Bits
DYNAMIC PERFORMANCE
Decimation by 32, 256 kSPS ODR
Dynamic Range Shorted input, wideband filter 97.3 97.7 dB
Signal-to-Noise Ratio (SNR) 1 kHz, −0.5 dBFS, sine wave input
Sinc5 filter 97.3 97.9 dB
Wideband filter 97.3 97.7 dB
Signal-to-Noise-and-Distortion 1 kHz, −0.5 dBFS, sine wave input 97.3 97.7 dB
Ratio (SINAD)
Total Harmonic Distortion (THD) 1 kHz, −0.5 dBFS, sine wave input −120 −107 dB
Spurious-Free Dynamic Range (SFDR) 126 dBc
INTERMODULATON DISTORTION (IMD) fINA = 9.7 kHz, fINB = 10.3 kHz
Second order −125 dB
Third order −124 dB
ACCURACY
INL 3 Endpoint method ±1 ± 1.5 LSB
Offset Error 4 ±1 ±2 LSB
Gain Error4 TA = 25°C ±5 ±40 LSB
Gain Drift vs. Temperature2 ±0.01 ±0.02 LSB/°C
VCM PIN
Output With respect to AVSS (AVDD1 − V
AVSS)/2
Load Regulation ∆VOUT/∆IL 400 µV/mA
Voltage Regulation Applies to the following VCM output 5 µV/V
options only: VCM = ∆VOUT/∆(AVDD1 −
AVSS)/2, VCM = 1.65 V, and VCM = 2.5 V
Short-Circuit Current 30 mA
ANALOG INPUTS See the Analog Inputs section
Differential Input Voltage Range VREF = (REFx+) − (REFx−) −VREF +VREF V
Input Common-Mode Range2 AVSS AVDD1 V
Absolute Analog Input Voltage Limits2 AVSS AVDD1 V
Analog Input Current
Unbuffered Differential component ±48 µA/V
Common-mode component ±17 µA/V
Precharge Buffer On 5 −20 µA
Input Current Drift
Unbuffered ±5 nA/V/°C
Precharge Buffer On ±31 nA/°C

Rev. A | Page 5 of 75
AD7761 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
EXTERNAL REFERENCE
Reference Voltage VREF = (REFx+) − (REFx−) 1 AVDD1 − AVSS V
Absolute Reference Voltage Limits2 Precharge reference buffers off AVSS − AVDD1 + 0.05 V
0.05
Precharge reference buffers on AVSS AVDD1 V
Average Reference Current Fast mode
Precharge reference buffers off ±72 µA/V/channel
Precharge reference buffers on ±16 µA/V/channel
Average Reference Current Drift Fast mode
Precharge reference buffers off ±1.7 nA/V/°C
Precharge reference buffers on ±49 nA/V/°C
Common-Mode Rejection 95 dB
DIGITAL FILTER RESPONSE
Low Ripple Wideband Filter FILTER = 0
Decimation Rate Up to six selectable decimation rates 32 1024
Group Delay Latency 34/ODR sec
Settling Time Complete settling 68/ODR sec
Pass-Band Ripple2 ±0.005 dB
Pass Band ±0.005 dB bandwidth 0.4 × ODR Hz
−0.1 dB bandwidth 0.409 × ODR Hz
−3 dB bandwidth 0.433 × ODR Hz
Stop Band Frequency Attenuation > 105 dB 0.499 × ODR Hz
Stop Band Attenuation 105 dB
Sinc5 Filter FILTER = 1
Decimation Rate Up to six selectable decimation rates 32 1024
Group Delay Latency 3/ODR sec
Settling Time Complete settling 7/ODR sec
Pass Band −3 dB bandwidth 0.204 × ODR Hz
REJECTION
AC Power Supply Rejection Ratio VIN = 0.1 V, AVDD1 = 5 V, AVDD2 =
(PSRR) 5 V, IOVDD = 2.5 V
AVDD1 90 dB
AVDD2 100 dB
IOVDD 75 dB
DC PSRR VIN = 1 V
AVDD1 100 dB
AVDD2 118 dB
IOVDD 90 dB
Analog Input Common-Mode
Rejection Ratio (CMRR)
DC VIN = 0.1 V 95 dB
AC Up to 10 kHz 95 dB
Crosstalk −0.5 dBFS input on adjacent channels −120 dB
CLOCK See the Clock Selection section for
data sheet performance functionality
Crystal Frequency 8 32.768 34 MHz
External Clock (MCLK) 32.768 MHz
Duty Cycle 50:50 %
MCLK Pulse Width2
Logic Low 12.2 ns
Logic High 12.2 ns
CMOS Clock Input Voltage See the Logic Inputs parameter
High, VINH
Low, VINL
Rev. A | Page 6 of 75
Data Sheet AD7761
Parameter Test Conditions/Comments Min Typ Max Unit
LVDS Clock2 RL = 100 Ω
Differential Input Voltage 100 650 mV
Common-Mode Input Voltage 800 1575 mV
Absolute Input Voltage 1.88 V
ADC RESET2
ADC Start-Up Time After Reset6 Time to first DRDY, fast mode, 1.58 1.66 ms
decimation by 32
Minimum RESET Low Pulse Width tMCLK = 1/MCLK 2 × tMCLK
LOGIC INPUTS
Input Voltage2
High, VINH 0.65 × V
IOVDD
Low, VINL 2.25 V < IOVDD < 3.6 V 0.7 V
1.72 V < IOVDD < 1.88 V 0.4 V
Hysteresis2 2.25 V < IOVDD < 3.6 V 0.04 0.09 V
1.72 V < IOVDD < 1.88 V 0.04 0.2 V
Leakage Current −10 +0.03 +10 µA
RESET pin 7 −10 +10 µA
LOGIC OUTPUTS
Output Voltage2
High, VOH ISOURCE = 200 μA 0.8 × V
IOVDD
Low, VOL ISINK = 400 µA 0.4 V
Leakage Current Floating state −10 +10 µA
Output Capacitance Floating state 10 pF
SYSTEM CALIBRATION2
Full-Scale Calibration Limit 1.05 × VREF V
Zero-Scale Calibration Limit −1.05 × V
VREF
Input Span 0.4 × VREF 2.1 × VREF V
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 − AVSS 4.5 5.0 5.5 V
AVDD2 − AVSS 2.0 2.25 to 5.0 5.5 V
AVSS − DGND −2.75 0 V
IOVDD − DGND 1.72 2.5 to 3.3 3.6 V
or 1.8
POWER SUPPLY CURRENTS Maximum output data rate, CMOS
MCLK, eight DOUTx signals, all
supplies at maximum voltages, all
channels in Channel Mode A
Eight Channels Active
Fast Mode
AVDD1 Current Precharge reference buffers off 36 40 mA
Precharge reference buffers on 57.5 64 mA
AVDD2 Current 37.5 40 mA
IOVDD Current Wideband filter 63 69 mA
Sinc5 filter2 27 29 mA
Median Mode
AVDD1 Current Precharge reference buffers off 18.5 mA
Precharge reference buffers on 29 mA
AVDD2 Current 21.3 mA
IOVDD Current Wideband filter 34 mA
Sinc5 filter 16 mA
Rev. A | Page 7 of 75
AD7761 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
Low Power Mode
AVDD1 Current Precharge reference buffers off 5.1 mA
Precharge reference buffers on 8 mA
AVDD2 Current 9.3 mA
IOVDD Current Wideband filter 12.5 mA
Sinc5 filter 8 mA
Four Channels Active2
Fast Mode
AVDD1 Current Precharge reference buffers off 18.2 20.3 mA
Precharge reference buffers on 28.8 32.5 mA
AVDD2 Current 18.8 20.3 mA
IOVDD Current Wideband filter 43.5 47.7 mA
Sinc5 filter 17 18.6 mA
Median Mode
AVDD1 Current Precharge reference buffers off 9.3 mA
Precharge reference buffers on 14.7 mA
AVDD2 Current 10.7 mA
IOVDD Current Wideband filter 24.5 mA
Sinc5 filter 11 mA
Low Power Mode
AVDD1 Current Precharge reference buffers off 2.7 mA
Precharge reference buffers on 4.1 mA
AVDD2 Current 4.7 mA
IOVDD Current Wideband filter 10 mA
Sinc5 filter 6.5 mA
Two Channels Active2
Fast Mode
AVDD1 Current Precharge reference buffers off 9.3 10.5 mA
Precharge reference buffers on 14.7 16.6 mA
AVDD2 Current 9.5 10.5 mA
IOVDD Current Wideband filter 34 36.7 mA
Sinc5 filter 12 13.5 mA
Median Mode
AVDD1 Current Precharge reference buffers off 4.8 mA
Precharge reference buffers on 7.5 mA
AVDD2 Current 5.5 mA
IOVDD Current Wideband filter 19.5 mA
Sinc5 filter 8.5 mA
Low Power Mode
AVDD1 Current Precharge reference buffers off 1.52 mA
Precharge reference buffers on 2.2 mA
AVDD2 Current 2.4 mA
IOVDD Current Wideband filter 8.6 mA
Sinc5 filter 5.8 mA
Standby Mode All channels disabled (sinc5 filter 6.5 8 mA
enabled)
Sleep Mode Full power-down (serial peripheral 0.73 1.2 mA
interface (SPI) mode only)
Crystal Excitation Current Extra current in IOVDD when using 540 µA
an external crystal compared to
using the CMOS MCLK

Rev. A | Page 8 of 75
Data Sheet AD7761
Parameter Test Conditions/Comments Min Typ Max Unit
POWER DISSIPATION External CMOS MCLK, all channels
active, MCLK = 32.768 MHz, all
channels in Channel Mode A
Full Operating Mode Analog precharge buffers on
Wideband Filter
Fast AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, 412 446 mW
precharge reference buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, 600 645 mW
precharge reference buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 631 681 mW
IOVDD = 3.6 V, precharge reference
buffers off
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 524 571 mW
IOVDD = 1.88 V, precharge
reference buffers off2
Median AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, 220 mW
precharge reference buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, 320 mW
precharge reference buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 341 mW
IOVDD = 3.6 V, precharge reference
buffers off
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 284 mW
IOVDD = 1.88 V, precharge
reference buffers off
Low Power AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, 75 mW
precharge reference buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, 107 mW
precharge reference buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 124 mW
IOVDD = 3.6 V, precharge reference
buffers off
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 99 mW
IOVDD = 1.88 V, precharge
reference buffers off
Sinc5 Filter2
Fast AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, 325 355 mW
precharge reference buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, 475 525 mW
precharge reference buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 501 545 mW
IOVDD = 3.6 V, precharge reference
buffers off
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 455 495 mW
IOVDD = 1.88 V, precharge
reference buffers off
Median AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, 175 mW
precharge reference buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, 260 mW
precharge reference buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 277 mW
IOVDD = 3.6 V, precharge reference
buffers off
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 248 mW
IOVDD = 1.88 V, precharge
reference buffers off

Rev. A | Page 9 of 75
AD7761 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
Low Power AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, 65 mW
precharge reference buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, 95 mW
precharge reference buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 108 mW
IOVDD = 3.6 V, precharge reference
buffers off
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 94 mW
IOVDD = 1.88 V, precharge
reference buffers off
Standby Mode All channels disabled; AVDD1 = 5 V, mW
AVDD2 = IOVDD = 2.5 V 14.5
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V 21 mW
AVDD1 = AVDD2 = 5.5 V, IOVDD = 23.5 29 mW
3.6 V
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 12.5 mW
IOVDD = 1.88 V
Sleep Mode Full power-down (SPI mode only); mW
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V 1.8
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V 2.5 mW
AVDD1 = AVDD2 = 5.5 V, IOVDD = 2.7 6.5 mW
3.6 V
AVDD1 = 5.5 V, AVDD2 = 5.5 V, 1.5 mW
IOVDD = 1.88 V
1
The output data rate ranges refer to the programmable decimation rates available on the AD7761 for a fixed MCLK rate of 32.768 MHz. Varying MCLK rates allow users
a wider variation of ODR.
2
These specifications are not production tested but are supported by characterization data at initial product release.
3
The maximum INL specification is guaranteed by design and characterization testing prior to release. This specification is not production tested.
4
Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration
reduces the gain error to the order of the noise for the programmed output data rate.
5
−25 μA is measured when the analog input is close to either the AVDD1 or AVSS rail. The input current reduces as the common-mode voltage approaches (AVDD1 −
AVSS)/2. The analog input current scales with the MCLK frequency and device power mode.
6
For lower MCLK rates or higher decimation rates, use Table 25 and Table 26 to calculate any additional delay before the first DRDY pulse.
7
The RESET pin has an internal pull-up device to IOVDD.

TIMING SPECIFICATIONS
AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 2.25 V to 3.6 V, Input Logic 0 = DGND, Input Logic 1 = IOVDD;
CLOAD = 10 pF on the DCLK pin, CLOAD = 20 pF on the other digital outputs; REFx+ = 4.096 V, TA = −40°C to +105°C. See Table 4 and
Table 5 for timing specifications at 1.8 V IOVDD.

Table 2. Data Interface Timing1

Parameter Description Test Conditions/Comments Min Typ Max Unit
MCLK Master clock 1.15 34 MHz
fMOD Modulator frequency Fast mode MCLK/4 Hz
Median mode MCLK/8 Hz
Low power mode MCLK/32 Hz
t1 DRDY high time tDCLK = t8 + t9 tDCLK − 10% 28 ns
t2 DCLK rising edge to DRDY rising edge 2 ns
t3 DCLK rising to DRDY falling −3.5 0 ns
t4 DCLK rise to DOUTx valid 1.5 ns
t5 DCLK rise to DOUTx invalid −3 ns
t6 DOUTx valid to DCLK falling 9.5 tDCLK/2 ns
t7 DCLK falling edge to DOUTx invalid 9.5 tDCLK/2 ns
t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns
t8a = DCLK = MCLK/2 tMCLK = 1/MCLK tMCLK ns
t8b = DCLK = MCLK/4 2 × tMCLK ns
t8c = DCLK = MCLK/8 4 × tMCLK ns
Rev. A | Page 10 of 75
Data Sheet AD7761
Parameter Description Test Conditions/Comments Min Typ Max Unit
t9 DCLK low time DCLK = MCLK/1 50:50 CMOS clock (tDCLK/2) − 5 tMCLK/2 tDCLK/2 ns
t9a = DCLK = MCLK/2 tMCLK ns
t9b = DCLK = MCLK/4 2 × tMCLK ns
t9c = DCLK = MCLK/8 4 × tMCLK ns
t10 MCLK rising to DCLK rising CMOS clock 30 ns
t11 Setup time of DOUT6 and DOUT7 14 ns
t12 Hold time of DOUT6 and DOUT7 0 ns
t13 START low time 1 × tMCLK ns
t14 MCLK to SYNC_OUT valid CMOS clock
SYNC_OUT RETIME_EN bit 4.5 22 ns
disabled; measured from
falling edge of MCLK
SYNC_OUT RETIME_EN bit 9.5 27.5 ns
enabled; measured from
rising edge of MCLK
t15 SYNC_IN setup time CMOS clock 0 ns
t16 SYNC_IN hold time CMOS clock 10 ns
1
These specifications are not production tested but are supported by characterization data at initial product release.

Table 3. SPI Control Interface Timing 1

Parameter Description Test Conditions/Comments Min Typ Max Unit
t17 SCLK period 100 ns
t18 CS falling edge to SCLK rising edge 26.5 ns
t19 SCLK falling edge to CS rising edge 27 ns
t20 CS falling edge to data output enable 22.5 40.5 ns
t21 SCLK high time 20 50 ns
t22 SCLK low time 20 50 ns
t23 SCLK falling edge to SDO valid 15 ns
t24 SDO hold time after SCLK falling 7 ns
t25 SDI setup time 0 ns
t26 SDI hold time 6 ns
t27 SCLK enable time 0 ns
t28 SCLK disable time 0 ns
t29 CS high time 10 ns
t30 CS low time fMOD = MCLK/4 1.1 × tMCLK ns
fMOD = MCLK/8 2.2 × tMCLK ns
fMOD = MCLK/32 8.8 × tMCLK ns
1
These specifications are not production tested but are supported by characterization data at initial product release.

1.8 V IOVDD TIMING SPECIFICATIONS

AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 1.72 V to 1.88 V (DREGCAP tied to IOVDD), Input Logic 0 =
DGND, Input Logic 1 = IOVDD, CLOAD = 10 pF on DCLK pin, CLOAD = 20 pF on other digital outputs, TA = −40°C to +105°C.

Table 4. Data Interface Timing 1

Parameter Description Test Conditions/Comments Min Typ Max Unit
MCLK Master clock 1.15 34 MHz
fMOD Modulator frequency Fast mode MCLK/4 Hz
Median mode MCLK/8 Hz
Low power mode MCLK/32 Hz
t1 DRDY high time tDCLK − 10% 28 ns
t2 DCLK rising edge to DRDY rising edge 2 ns
t3 DCLK rising to DRDY falling −4.5 0 ns
Rev. A | Page 11 of 75
AD7761 Data Sheet
Parameter Description Test Conditions/Comments Min Typ Max Unit
t4 DCLK rise to DOUTx valid 2.0 ns
t5 DCLK rise to DOUTx invalid −4 ns
t6 DOUTx valid to DCLK falling 8.5 tDCLK/2 ns
t7 DCLK falling edge to DOUTx invalid 8.5 tDCLK/2 ns
t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns
t8a = DCLK = MCLK/2 tMCLK ns
t8b = DCLK = MCLK/4 2 × tMCLK ns
t8c = DCLK = MCLK/8 4 × tMCLK ns
t9 DCLK low time DCLK = MCLK/1 50:50 CMOS clock (tDCLK/2) − 5 tMCLK/2 tDCLK/2 ns
t9a = DCLK = MCLK/2 tMCLK ns
t9b = DCLK = MCLK/4 2 × tMCLK ns
t9c = DCLK = MCLK/8 4 × tMCLK ns
t10 MCLK rising to DCLK rising CMOS clock 37 ns
t11 Setup time DOUT6 and DOUT7 14 ns
t12 Hold time DOUT6 and DOUT7 0 ns
t13 START low time 1 × tMCLK ns
t14 MCLK to SYNC_OUT valid CMOS clock
SYNC_OUT RETIME_EN bit 10 31 ns
disabled; measured from
falling edge of MCLK
SYNC_OUT RETIME_EN bit 15 37 ns
enabled; measured from
rising edge of MCLK
t15 SYNC_IN setup time CMOS clock 0 ns
t16 SYNC_IN hold time CMOS clock 11 ns
1
These specifications are not production tested but are supported by characterization data at initial product release.

Table 5. SPI Control Interface Timing 1

Parameter Description Test Conditions/Comments Min Typ Max Unit
t17 SCLK period 100 ns
t18 CS falling edge to SCLK rising edge 31.5 ns
t19 SCLK falling edge to CS rising edge 30 ns
t20 CS falling edge to data output enable 29 54 ns
t21 SCLK high time 20 50 ns
t22 SCLK low time 20 50 ns
t23 SCLK falling edge to SDO valid 16 ns
t24 SDO hold time after SCLK falling 7 ns
t25 SDI setup time 0 ns
t26 SDI hold time 10 ns
t27 SCLK enable time 0 ns
t28 SCLK disable time 0 ns
t29 CS high time 10 ns
t30 CS low time fMOD = MCLK/4 1.1 × tMCLK ns
fMOD = MCLK/8 2.2 × tMCLK ns
fMOD = MCLK/32 8.8 × tMCLK ns
1
These specifications are not production tested but are supported by characterization data at initial product release.

Rev. A | Page 12 of 75
Data Sheet AD7761
Timing Diagrams
t1

DRDY tODR = 1/ODR

t2 t8

DCLK

t5 t9
t3 t4 t6

DOUTx D23

14285-002
t7

Figure 2. Data Interface Timing Diagram

MCLK

t8a t10

DCLK = MCLK/2

t8b t9a

DCLK = MCLK/4
t9b

t8c

DCLK = MCLK/8

14285-003
t9c

Figure 3. MCLK to DCLK Divider Timing Diagram

DRDY tODR

DCLK

t11

DOUT6
AND
DOUT7

t12
14285-004

Figure 4. Daisy-Chain Setup and Hold Timing Diagram

MCLK

START

t14
t13
14285-005

SYNC_OUT

Figure 5. Asynchronous START and SYNC_OUT Timing Diagram

Rev. A | Page 13 of 75
AD7761 Data Sheet

MCLK

SYNC_IN

14285-006
t15 t16 t15

Figure 6. Synchronous SYNC_IN Pulse Timing Diagram

t30

CS

t18 t17 t21 t19

SCLK

t22

SDO MSB

14285-007
t20 t24 t23

Figure 7. SPI Serial Read Timing Diagram

t30

CS

t18

SCLK

t25
t26
14285-008

SDI MSB LSB

Figure 8. SPI Serial Write Timing Diagram

t29

CS

SCLK
14285-009

t28 t27

Figure 9. SCLK Enable and Disable Timing Diagram

Rev. A | Page 14 of 75
Data Sheet AD7761

ABSOLUTE MAXIMUM RATINGS

Table 6. Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
Parameter Rating
stress rating only; functional operation of the product at these
AVDD1, AVDD2 to AVSS1 −0.3 V to +6.5 V
or any other conditions above those indicated in the operational
AVDD1 to DGND −0.3 V to +6.5 V
section of this specification is not implied. Operation beyond
IOVDD to DGND −0.3 V to +6.5 V
the maximum operating conditions for extended periods may
IOVDD, DREGCAP to DGND (IOVDD Tied −0.3 V to +2.25 V
to DREGCAP for 1.8 V Operation) affect product reliability.
IOVDD to AVSS −0.3 V to +7.5 V THERMAL RESISTANCE
AVSS to DGND −3.25 V to +0.3 V
Thermal performance is directly linked to PCB design and
Analog Input Voltage to AVSS −0.3 V to AVDD1 + 0.3 V
operating environment. Careful attention to PCB thermal
Reference Input Voltage to AVSS −0.3 V to AVDD1 + 0.3 V
design is required.
Digital Input Voltage to DGND −0.3 V to IOVDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to IOVDD + 0.3 V Table 7. Thermal Resistance
Operating Temperature Range −40°C to +105°C Package Type θJA θJC Unit JEDEC Board Layers
Storage Temperature Range −65°C to +150°C ST-64-2 38 9.2 °C/W 2P2S1
Pb-Free Temperature, Soldering 260°C
1
Reflow (10 sec to 30 sec) 2P2S is a JEDEC standard PCB configuration per JEDEC Standard JESD51-7.
Maximum Junction Temperature 150°C
Maximum Package Classification 260°C ESD CAUTION
Temperature
1
Transient currents of up to 100 mA do not cause silicon controlled rectifier
(SCR) latch-up.

Rev. A | Page 15 of 75
AD7761 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REGCAPA

REGCAPB
FORMAT0
FORMAT1
CLK_SEL
AVDD2A

AVDD2B
AVSS2A

AVSS2B
PIN/SPI
AIN0+

AIN4+
AIN0–

AIN4–
AVSS
VCM
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

AIN1– 1 48 AIN5–
AIN1+ 2 47 AIN5+
AVSS1A 3 46 AVSS1B
AVDD1A 4 45 AVDD1B
REF1– 5 44 REF2–
REF1+ 6 43 REF2+
AIN2– 7 42 AIN6–
AIN2+ 8
AD7761 41 AIN6+
TOP VIEW
AIN3– 9 (Not to Scale) 40 AIN7–
AIN3+ 10 39 AIN7+
FILTER/GPIO4 11 38 SYNC_OUT
MODE0/GPIO0 12 37 START
MODE1/GPIO1 13 36 SYNC_IN
MODE2/GPIO2 14 35 IOVDD
MODE3/GPIO3 15 34 DREGCAP
ST0/CS 16 33 DGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

XTAL1
XTAL2/MCLK
ST1/SCLK

DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
DCLK

RESET
DRDY
DEC1/SDI
DEC0/SDO

14285-010
Figure 10. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Type 1 Description
1 AIN1− AI Negative Analog Input to ADC Channel 1.
2 AIN1+ AI Positive Analog Input to ADC Channel 1.
3 AVSS1A P Negative Analog Supply. This pin is nominally 0 V.
4 AVDD1A P Analog Supply Voltage, 5 V ± 10% with Respect to AVSS.
5 REF1− AI Reference Input Negative. REF1− is the negative reference terminal for Channel 0 to Channel 3. The
REF1− voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to AVSS with a high quality
capacitor, and maintain a low impedance between this capacitor and Pin 3.
6 REF1+ AI Reference Input Positive. REF1+ is the positive reference terminal for Channel 0 to Channel 3.
The REF1+ voltage range is from (AVSS + 1 V) to AVDD1. Apply an external reference differential
between REF1+ and REF1− in the range from 1 V to |AVDD1 − AVSS|. Decouple this pin to AVSS
with a high quality capacitor, and maintain a low impedance between this capacitor and Pin 3.
7 AIN2− AI Negative Analog Input to ADC Channel 2.
8 AIN2+ AI Positive Analog Input to ADC Channel 2.
9 AIN3− AI Negative Analog Input to ADC Channel 3.
10 AIN3+ AI Positive Analog Input to ADC Channel 3.
11 FILTER/GPIO4 DI/O Filter Select/General-Purpose Input/Output 4. In pin control mode, this pin selects the filter type.
Set this pin to Logic 1 for the sinc5 filter. This sinc5 filter is a low latency filter, and is best for dc
applications or when a user has specialized postfiltering implemented off chip.
Set this pin to Logic 0 for the wideband low ripple filter response. This filter has a steep
transition band and 105 dB stop band attenuation. Full attenuation at Nyquist (ODR/2) means
that no aliasing occurs at ODR/2 out to the first chopping zone.
In SPI control mode, this pin can be used as a general-purpose input/output (GPIO4). For further
information on GPIO configuration, see the GPIO Functionality section.
In SPI control mode, when not used as a GPIO pin, and when using a crystal as the clock source,
this pin must be set to 1.

Rev. A | Page 16 of 75
Data Sheet AD7761
Pin No. Mnemonic Type 1 Description
12, 13, MODE0/GPIO0, DI/DI/O Mode Selection/General-Purpose Input/Output Pin 0 to Pin 3.
14, 15 MODE1/GPIO1, In pin control mode, the MODEx pins set the mode of operation for all ADC channels, controlling
MODE2/GPIO2, power consumption, DCLK frequency, and the ADC conversion type, allowing one-shot
MODE3/GPIO3 conversion operation.
In SPI control mode, the GPIOx pins, in addition to the FILTER/GPIO4 pin, form five general-
purpose input/output pins (GPIO4 to GPIO0).
16 ST0/CS DI Standby 0/Chip Select Input.
In pin control mode, a Logic 1 places Channel 0 to Channel 3 into standby mode.
In SPI control mode, this pin is the active low chip select input to the SPI control interface.
17 ST1/SCLK DI Standby 1/Serial Clock Input.
In pin control mode, a Logic 1 places Channel 4 to Channel 7 into standby mode.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into
standby mode, the crystal circuitry is also disabled for maximum power saving. Channel 4 must
be enabled while the external crystal is used on the AD7761.
In SPI control mode, this pin is the serial clock input pin for the SPI control interface.
18 DEC1/SDI DI Decimation Rate Control Input 1/Serial Data Input.
In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC channels.
In SPI control mode, this pin is the serial data input pin used to write data to the AD7761
register bank.
19 DEC0/SDO DI/O Decimation Rate Control Input 0/Serial Data Output.
In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC channels.
In SPI control mode, this pin is the serial data output pin, allowing readback from the AD7761
registers.
20 DOUT7 DI/O Conversion Data Output 7. This pin is synchronous to DCLK and framed by DRDY. This pin acts as
a digital input from a separate AD7761 device if configured in a synchronized multidevice daisy
chain when the FORMATx pins are configured as 01. To use the AD7761 in a daisy chain, hardwire the
FORMATx pins as either 01, 10, or 11, depending on the best interfacing format for the application.
When FORMATx is set to 10 or 11, connect this pin to ground through a pull-down resistor.
21 DOUT6 DI/O Conversion Data Output 6. This pin is synchronous to DCLK and framed by DRDY. This pin acts as
a digital input from a separate AD7761 device if configured in a synchronized multidevice daisy
chain. To use this pin in a daisy chain, hardwire the FORMATx pins as either 01, 10, or 11,
depending on the best interfacing format for the application.
22 DOUT5 DO Conversion Data Output 5. This pin is synchronous to DCLK and framed by DRDY.
23 DOUT4 DO Conversion Data Output 4. This pin is synchronous to DCLK and framed by DRDY.
24 DOUT3 DO Conversion Data Output 3. This pin is synchronous to DCLK and framed by DRDY.
25 DOUT2 DO Conversion Data Output 2. This pin is synchronous to DCLK and framed by DRDY.
26 DOUT1 DO Conversion Data Output 1. This pin is synchronous to DCLK and framed by DRDY.
27 DOUT0 DO Conversion Data Output 0. This pin is synchronous to DCLK and framed by DRDY
28 DCLK DO ADC Conversion Data Clock. This pin clocks conversion data out to the digital host, either digital
signal processing (DSP) or field programmable gate array (FPGA). This pin is synchronous
with DRDY and any conversion data output on DOUT0 to DOUT7 and is derived from the MCLK
signal. This pin is unrelated to the control SPI interface.
29 DRDY DO Data Ready. Periodic signal output framing the conversion results from the eight ADCs. This pin
is synchronous to DCLK and DOUT0 to DOUT7.
30 RESET DI Hardware Asynchronous Reset Input. After the device is fully powered up, it is recommended to
perform a hard or soft reset.
31 XTAL1 DI Input 1 for Crystal or Connection to an LVDS Clock. When CLK_SEL is 0, connect XTAL1 to DGND.
In SPI control mode, when using a crystal source, the FILTER pin must be set to Logic 1 for
correct operation.

Rev. A | Page 17 of 75
AD7761 Data Sheet
Pin No. Mnemonic Type 1 Description
32 XTAL2/MCLK DI Input 2 for CMOS or Crystal/LVDS Sampling Clock. See the CLK_SEL pin for the details of this
configuration.
External crystal. XTAL2 is connected to the external crystal. In SPI control mode, when using a
crystal source, the FILTER pin must be set to Logic 1 for correct operation.
LVDS. A second LVDS input is connected to this pin.
CMOS clock. This pin operates as an MCLK input. CMOS input with logic level of IOVDD/DGND.
Set FILTER pin to Logic 1 for crystal clock source.
33 DGND P Digital Ground. This pin is nominally 0 V.
34 DREGCAP AO Digital Low Dropout (LDO) Regulator Output. Decouple this pin to DGND with a high quality,
low equivalent series resistance (ESR), 10 µF capacitor. For optimum performance, use a
decoupling capacitor with an ESR specification between 50 mΩ and 400 mΩ. This pin is not for
use in circuits external to the AD7761. For 1.8 V IOVDD operation, connect this pin to IOVDD via
an external trace to provide power to the digital processing core.
35 IOVDD P Digital Supply. This pin sets the logic levels for all interface pins. IOVDD also powers the digital
processing core via the digital LDO when IOVDD is at least 2.25 V. For 1.8 V IOVDD operation,
connect this pin to DREGCAP via an external trace to provide power to the digital processing core.
36 SYNC_IN DI Synchronization Input. SYNC_IN receives the synchronous signal from SYNC_OUT. It is used in
the synchronization of any AD7761 that requires simultaneous sampling or is in a daisy chain.
Ignore the START and SYNC_OUT functions if the SYNC_IN pin is connected to the system
synchronization pulse. This signal pulse must be synchronous to the MCLK clock domain.
37 START DI Start Signal. The START pulse synchronizes the AD7761 to other devices. The signal can be
asynchronous. The AD7761 samples the input and then outputs a SYNC_OUT pulse.
This SYNC_OUT pulse must be routed to the SYNC_IN pin of this device and any other AD7761
devices that must be synchronized together. This means that the user does not need to run the
ADCs and their digital host from the same clock domain, which is useful when there are long
traces or back planes between the ADC and the controller. If this pin is not used, it must be tied
to a Logic 1 through a pull-up resistor.
38 SYNC_OUT DO Synchronization Output. This pin operates only when using the START input. When using
the START input feature, the SYNC_OUT pin must be connected to SYNC_IN via an external
trace. SYNC_OUT is a digital output that is synchronous to the MCLK signal; the synchronization
signal driven in on START is internally synchronized to the MCLK signal and is driven out
on SYNC_OUT. SYNC_OUT can also be routed to other AD7761 devices requiring simultaneous
sampling and/or daisy-chaining, ensuring synchronization of devices related to the MCLK clock
domain. It must then be wired to drive the SYNC_IN pin on the same AD7761 and on the other
AD7761 devices.
39 AIN7+ AI Positive Analog Input to ADC Channel 7.
40 AIN7− AI Negative Analog Input to ADC Channel 7.
41 AIN6+ AI Positive Analog Input to ADC Channel 6.
42 AIN6− AI Negative Analog Input to ADC Channel 6.
43 REF2+ AI Reference Input Positive. REF2+ is the positive reference terminal for Channel 4 to Channel 7.
The REF2+ voltage range is from (AVSS + 1 V) to AVDD1. Apply an external reference differential
between REF2+ and REF2− in the range from 1 V to |AVDD1 − AVSS|. Decouple this pin to AVSS
with a high quality capacitor, and maintain a low impedance between this capacitor and Pin 46.
44 REF2− AI Reference Input Negative. REF2− is the negative reference terminal for Channel 4 to Channel 7. The
REF2− voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to AVSS with a high quality
capacitor, and maintain a low impedance between this capacitor and Pin 46.
45 AVDD1B P Analog Supply Voltage. This pin is 5 V ± 10% with respect to AVSS.
46 AVSS1B P Negative Analog Supply. This pin is nominally 0 V.
47 AIN5+ AI Positive Analog Input to ADC Channel 5.
48 AIN5− AI Negative Analog Input to ADC Channel 5.
49 AIN4+ AI Positive Analog Input to ADC Channel 4.
50 AIN4− AI Negative Analog Input to ADC Channel 4.
51 AVSS2B P Negative Analog Supply. This pin is nominally 0 V.
52 REGCAPB AO Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
53 AVDD2B P Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.
54 AVSS P Negative Analog Supply. This pin is nominally 0 V.

Rev. A | Page 18 of 75
Data Sheet AD7761
Pin No. Mnemonic Type 1 Description
55, 56 FORMAT1, DI Format Selection Pins. Hardwire the FORMATx pins to the required values in pin control and SPI
FORMAT0 control mode. These pins set the number of DOUTx pins used to output ADC conversion data. The
FORMATx pins are checked by the AD7761 on power-up; the AD7761 then remains in this data
output configuration.
57 PIN/SPI DI Pin Control/SPI Control. This pin sets the control method.
Logic 0 = pin control mode for the AD7761. Pin control mode allows pin strapped configuration
of the AD7761 by tying logic input pins to the required logic levels. Tie the logic pins (MODE0 to
MODE4, DEC0 and DEC1, and FILTER) as required for the configuration.
Logic 1 = SPI control mode for the AD7761. Use the SPI control interface signals (CS, SCLK, SDI,
and SDO) for reading and writing to the AD7761 memory map.
58 CLK_SEL DI Clock Select.
0 = pull this pin low for the CMOS clock option. The clock is applied to Pin 32 (connect Pin 31 to
DGND).
1 = pull this pin high for the crystal or LVDS clock option. The crystal or LVDS clock is applied to
Pin 31 and Pin 32. The LVDS option is available only in SPI control mode. A write is required to
enable the LVDS clock option.
59 VCM AO Common-Mode Voltage Output. This pin outputs (AVDD1 − AVSS)/2, which is 2.5 V by default in
pin control mode. Configure this pin to (AVDD1 − AVSS)/2, 2.5 V, 2.14 V, or 1.65 V in SPI control
mode. When driving capacitive loads larger than 0.1 µF, it is recommended to place a 50 Ω series
resistor between this pin and the capacitive load for stability.
60 AVDD2A P Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.
61 REGCAPA AO Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
62 AVSS2A P Negative Analog Supply. This pin is nominally 0 V.
63 AIN0− AI Negative Analog Input to ADC Channel 0.
64 AIN0+ AI Positive Analog Input to ADC Channel 0.
1
AI is analog input, P is power, DI/O is digital input/output, DI is digital input, DO is digital output, and AO is analog output.

Rev. A | Page 19 of 75
AD7761 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 5 V, AVDD2 = 2.5 V, AVSS = 0 V, IOVDD = 2.5 V, VREF = 4.096 V, TA = 25°C, wideband filter, decimation = ×32, MCLK =
32.768 MHz, analog input precharge buffers on, precharge reference buffers off, unless otherwise noted.
0 0
SNR = 97.7dB SNR = 97.8dB
THD = –123.8dB THD = –124.2dB
–20 –20

–40 –40

–60 –60

AMPLITUDE (dB)
AMPLITUDE (dB)

–80 –80

–100 –100

–120 –120

–140 –140

–160 –160

–180 –180

–200 –200

14285-017
14285-011

10 100 1k 10k 100k 10 100 1k 10k 100k

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 11. Fast Fourier Transform (FFT), Fast Mode, Wideband Filter, Figure 14. FFT, Fast Mode, Sinc5 Filter, −0.5 dBFS
−0.5 dBFS

0 0
SNR = 97.7dB SNR = 97.9dB
THD = –125.1dB THD = –125.1dB
–20 –20

–40 –40

–60 –60
AMPLITUDE (dB)

AMPLITUDE (dB)

–80 –80

–100 –100

–120 –120

–140 –140

–160 –160

–180 –180

–200 –200
14285-012

14285-018
10 100 1k 10k 100k 10 100 1k 10k 100k
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 12. FFT, Median Mode, Wideband Filter, −0.5 dBFS Figure 15. FFT, Median Mode, Sinc5 Filter, −0.5 dBFS

0 0
SNR = 97.7dB SNR = 97.9dB
THD = –128.3dB THD = –128.3dB
–20 –20

–40 –40

–60 –60
AMPLITUDE (dB)

AMPLITUDE (dB)

–80 –80

–100 –100

–120 –120

–140 –140

–160 –160

–180 –180

–200 –200
14285-013

14285-019

1 10 100 1k 10k 1 10 100 1k 10k

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 13. FFT, Low Power Mode, Wideband Filter, −0.5 dBFS Figure 16. FFT, Low Power Mode, Sinc5 Filter, −0.5 dBFS

Rev. A | Page 20 of 75
Data Sheet AD7761
0 99 0
SNR = 97.9dB
THD = –119.9dB
–20 98 SNR, FAST –20
–40
97
–40

THD AND THD + N (dB)

–60
96
AMPLITUDE (dB)

–60
–80

SNR (dB)
95
–100 –80
94 THD + N, FAST
–120
–100
93
–140 THD, FAST
–120
92
–160

91 –140
–180
fIN = 1kHz
–200 90 –160

14285-027
14285-023
5 50 500 5000 0 5 10 15 20 25 30 35 40
FREQUENCY (Hz) MCLK FREQUENCY (MHz)

Figure 17. FFT One-Shot Mode, Sinc5 Filter, Median Mode, Figure 20. SNR, THD, and THD + N vs. MCLK Frequency
Decimation = ×64, −0.5 dBFS, SYNC_IN Frequency = MCLK/4000

0 0
SECOND-ORDER IMD = –125.2dB
THIRD-ORDER IMD = –120.8 dB
–20
–20
–40

–60 –40
AMPLITUDE (dB)

–80
THD (dB) –60
–100 FAST
–80 MEDIAN
–120
FOCUS
–140 –100

–160
–120
–180

–200 –140

14285-028
14285-024

100 1k 10k 100k 10 100 1k 10k 100k

FREQUENCY (Hz) INPUT FREQUENCY (Hz)

Figure 18. IMD with Input Signals at 9.7 kHz and 10.3 kHz Figure 21. THD vs. Input Frequency, Three Power Modes, Wideband Filter

0 0
fIN = 3.15kHz
INTERFERER (1kHz) ON ALL OTHER CHANNELS
–20
–20

–40
THD AND THD + N (dB)

–40
–60
AMPLITUDE (dB)

–60
–80

–100 –80

–120 THD + N
–100
–140
–120 THD
–160

–180 –140
14285-030
14285-016

0 1 2 3 4 5 6 7 –40 –30 –20 –10 0

CHANNEL INPUT AMPLITUDE (dBFS)

Figure 19. Crosstalk Figure 22. THD and THD + N vs. Input Amplitude, Wideband Filter, Fast Mode

Rev. A | Page 21 of 75
AD7761 Data Sheet
1.0 35

0.8 +105°C
FAST 30 +25°C
0.6 MEDIAN –40°C

NUMBER OF OCCURRENCES
FOCUS
0.4 25
INL ERROR (LSB)

0.2
20
0

–0.2 15

–0.4
10
–0.6

–0.8 5

–1.0

14285-032
0
–VREF 0V +VREF

14285-036
–4

0
2
4
6
8
–8
–6

–2

10
12
14
16
–16
–14
–12
–10
INPUT VOLTAGE (V)
GAIN ERROR ( LSB)

Figure 23. INL Error vs. Input Voltage Figure 26. Gain Error Distribution (100 Devices Sampled)

1.0 25

0.8 –40°C
0°C
0.6 +25°C 20

NUMBER OF OCCURRENCES
+85°C
0.4 +105°C
INL ERROR (LSB)

0.2 15

–0.2 10

–0.4

–0.6 5

–0.8

–1.0 0
14285-033

14285-037
–VREF 0V +VREF 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
INPUT VOLTAGE (V) GAIN ERROR (LSB)

Figure 24. INL Error vs. Input Voltage for Various Temperatures, Figure 27. Channel to Channel Gain Error Matching (100 Devices Sampled)
Fast Mode

18000 0

16000 –20
NUMBER OF OCCURRENCES

14000 –40

12000 –60
AC CMRR (dB)

10000 –80

8000 –100

6000 –120

4000 –140

2000 –160

0 –180
14285-038

10 100 1k 10k 100k 1M 10M

0
0.2
0.4
0.6
0.8
1.0
–2.0
–1.8
–1.6
–1.4
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2

14285-034

INPUT FREQUENCY (Hz)

OFFSET ERROR (LSB)

Figure 25. Offset Error Distribution (Approximately 2500 Devices Sampled) Figure 28. AC CMRR vs. Input Frequency

Rev. A | Page 22 of 75
Data Sheet AD7761
0 20
DCLK = 32.768MHz
AVDD1 = 5V + 100mV p-p
–10 0

–20 –20

–30 –40

AMPLITUDE (dB)
FOCUS
AC PSRR (dB)

–40 –60 MEDIAN

FAST
–50 –80

–60 CH0 CH1 CH2 CH3 –100

CH4 CH5 CH6 CH7
–70 –120

–80 –140
–90 –160
–100 –180

14285-039
100 1k 10k 100k 1M 10M

14285-042
–0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5
FREQUENCY (Hz)
NORMALIZED INPUT FREQUENCY (fIN/fODR)

Figure 29. AC PSRR vs. Frequency, AVDD1 Figure 32. Wideband Filter Profile, Amplitude vs. fIN/fODR

0 5 70000
DCLK = 32.768MHz
AVDD2 = 5V + 100mV p-p
–10 4
60000
–20
3
–30 AINx 50000
2
DOUTx
AC PSRR (dB)

DOUTx (Code)
–40
40000
AINx (V)

1
–50
0 30000
–60 CH0 CH1 CH2 CH3
CH4 CH5 CH6 CH7
–1
–70 20000
–2
–80
10000
–90 –3

–100 –4 0

14285-043
14285-040

100 1k 10k 100k 1M 10M 0 10 20 30 40 50 60 70 80

FREQUENCY (Hz) SAMPLES

Figure 30. AC PSRR vs. Frequency, AVDD2 Figure 33. Step Response, Wideband Filter

0 0.005
FOCUS
–10 0.004 MEDIAN
FAST
–20 0.003
IOVDD = 1.8V, DCLK = 32.768MHz, CH7
–30
IOVDD = 2.5V, DCLK = 32.768MHz, CH7 0.002
IOVDD = 1.8V, DCLK = 8.192MHz, CH7
AMPLITUDE (dB)

–40
AC PSRR (dB)

IOVDD = 2.5V, DCLK = 8.192MHz, CH7 0.001

–50
0
–60
–0.001
–70

–80 –0.002

–90 –0.003

–100 –0.004
–110
14285-041

100 1k 10k 100k 1M 10M –0.005

14285-044

0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (Hz)
NORMALIZED INPUT FREQUENCY (fIN/fODR)

Figure 31. AC PSRR vs. Frequency, IOVDD Figure 34. Wideband Filter Ripple

Rev. A | Page 23 of 75
AD7761 Data Sheet
0 0

REFERENCE INPUT CURRENT (µA/V/CHANNEL)

–20 –10

–40 –20
AMPLITUDE (dB)

–60 –30

–80 –40
FAST WITH PRECHARGE
–50 FAST, NO PRECHARGE
–100 MEDIAN WITH PRECHARGE
MEDIAN, NO PRECHARGE
–60 FOCUS WITH PRECHARGE
–120
FOCUS, NO PRECHARGE
RESOLUTION LIMIT = –110dB
–70
–140

–80

14285-048
–160 –40 25 105

14285-045
0 1 2 3 4 5 6
TEMPERATURE (°C)
NORMALIZED INPUT FREQUENCY (fIN/fODR)

Figure 35. Sinc5 Filter Profile, Amplitude vs. fIN/fODR Figure 38. Reference Input Current vs. Temperature, Reference Precharge
Buffers On/Off

5 70000
AVDD1 = 5V, AVSS = 0V
VCM_VSEL = 10
120
4 PART TO PART DISTRIBUTION
60000

NUMBER OF OCCURRENCES
3 100
AINx 50000
2
DOUTx
80
DOUTx (Code)

40000
AINx (V)

0 60
30000

–1
40
20000
–2
10000 20
–3

–4 0 0

14285-049
14285-046

0 5 10 15 20 25 30 2.42 2.43 2.44 2.45 2.46 2.47

SAMPLES VCM (V)

Figure 36. Step Response, Sinc5 Filter Figure 39. VCM Output Voltage Distribution

60 40
DIFFERENTIAL COMPONENT, NO PRECHARGE (µA/V)
50
35
40 FAST
ANALOG INPUT CURRENT (µA)

30
SUPPLY CURRENT (mA)

30
COMMON-MODE COMPONENT, NO PRECHARGE (µA/V) 25
20

10 20
MEDIAN
0
15
–10
TOTAL CURRENT, PRECHARGE ON (µA) 10
–20
FOCUS
5
–30

–40 0
14285-047

14285-050

–40 25 105 –40 –25 –10 5 20 35 50 65 80 95 110

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 37. Analog Input Current vs. Temperature, Analog Input Precharge Figure 40. Supply Current vs. Temperature, AVDD1
Buffers On/Off

Rev. A | Page 24 of 75
Data Sheet AD7761
40 500

FAST 450 FAST, WIDEBAND FILTER

35
400
30
SUPPLY CURRENT (mA)

350 FAST, SINC5 FILTER

TOTAL POWER (mW)

25
300

20 MEDIAN 250 MEDIAN, WIDEBAND FILTER

200
15
150 MEDIAN, SINC5 FILTER
10 FOCUS
100 FOCUS, WIDEBAND FILTER
5

14285-053
50 FOCUS, SINC5 FILTER

0 0

14285-051
–40 –25 –10 5 20 35 50 65 80 95 110 –40 25 105
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 41. Supply Current vs. Temperature, AVDD2 Figure 43. Total Power vs. Temperature

70

60
FAST, SINC5
FAST, WIDEBAND
MEDIAN, SINC5
SUPPLY CURRENT (mA)

50
MEDIAN, WIDEBAND
FOCUS, SINC5
FOCUS, WIDEBAND
40

30

20

10

0
14285-052

–40 –25 –10 5 20 35 50 65 80 95 110

TEMPERATURE (°C)

Figure 42. Supply Current vs. Temperature, IOVDD

Rev. A | Page 25 of 75
AD7761 Data Sheet

TERMINOLOGY
AC Common-Mode Rejection Ratio (AC CMRR) As a result, the second-order and third-order terms are
AC CMRR is defined as the ratio of the power in the ADC output specified separately. The calculation of the intermodulation
at frequency, f, to the power of a sine wave applied to the common- distortion is as per the THD specification, where it is the ratio
mode voltage of AINx+ and AINx− at frequency, fS. of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals, expressed in
AC CMRR (dB) = 10log(Pf/PfS) decibels.
where: Least Significant Bit (LSB)
Pf is the power at frequency, f, in the ADC output. The least significant bit, or LSB, is the smallest increment that
PfS is the power at frequency, fS, in the ADC output. can be represented by a converter. For a fully differential input
Gain Error ADC with N bits of resolution, the LSB expressed in volts is as
The first transition (from 100 … 000 to 100 … 001) occurs at a follows:
level ½ LSB above nominal negative full scale (−4.0959375 V for LSB (V) = (2 × VREF)/2N
the ±4.096 V range). The last transition (from 011 … 110 to
011 … 111) occurs for an analog voltage 1½ LSB below the where:
nominal full scale (+4.0959375 V for the ±4.096 V range). The VREF is the difference voltage between the REFx+ and REFx− pins.
gain error is the deviation of the difference between the actual level N = 16.
of the last transition and the actual level of the first transition from Offset Error
the difference between the ideal levels. Offset error is the difference between the ideal midscale input
Gain Error Drift voltage (0 V) and the actual voltage producing the midscale
Gain error drift is defined as the gain error change due to a output code.
temperature change of 1°C. It is expressed in parts per million Power Supply Rejection Ratio (PSRR)
per degree Celsius. Variations in power supply affect the full-scale transition but
Integral Nonlinearity (INL) Error not the linearity of the converter. PSRR is the maximum change
INL error refers to the deviation of each individual code from a in the full-scale transition point due to a change in the power
line drawn from negative full scale through positive full scale. supply voltage from the nominal value.
The point used as negative full scale occurs ½ LSB before the Signal-to-Noise Ratio (SNR)
first code transition. Positive full scale is defined as a level SNR is the ratio of the rms value of the actual input signal to
1½ LSB beyond the last code transition. The deviation is measured the rms sum of all other spectral components below the Nyquist
from the middle of each code to the true straight line. frequency, excluding harmonics and dc. The value for SNR is
Intermodulation Distortion (IMD) expressed in decibels.
With inputs consisting of sine waves at two frequencies, fa and Signal-to-Noise-and-Distortion Ratio (SINAD)
fb, any active device with nonlinearities creates distortion SINAD is the ratio of the rms value of the actual input signal to
products at the sum and difference frequencies of mfa and nfb, the rms sum of all other spectral components below the Nyquist
where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion frequency, including harmonics but excluding dc. The value for
terms are those for which neither m or n are equal to 0. For SINAD is expressed in decibels.
example, the second-order terms include (fa + fb) and (fa − fb), Spurious-Free Dynamic Range (SFDR)
and the third-order terms include (2fa + fb), (2fa − fb), (fa + SFDR is the difference, in decibels, between the rms amplitude
2fb), and (fa − 2fb). of the input signal and the peak spurious signal (excluding the
The AD7761 is tested using the CCIF standard, in which two first five harmonics).
input frequencies near to each other are used. In this case, the Total Harmonic Distortion (THD)
second-order terms are usually distanced in frequency from the THD is the ratio of the rms sum of the first five harmonic
original sine waves, and the third-order terms are usually at a components to the rms value of a full-scale input signal and
frequency close to the input frequencies. is expressed in decibels.

Rev. A | Page 26 of 75
Data Sheet AD7761

THEORY OF OPERATION
The AD7761 is an 8-channel, simultaneously sampled, low CLOCKING, SAMPLING TREE, AND POWER SCALING
noise, Σ-∆ ADC. The AD7761 includes multiple ADC cores. Each of these ADCs
Each ADC within the AD7761 employs a Σ-Δ modulator whose receives the same master clock signal, MCLK. The MCLK signal
clock runs at a frequency of fMOD. The modulator samples the can be sourced from one of three options: a CMOS clock, a crystal
inputs at a rate of 2 × fMOD, to convert the analog input into an connected between the XTAL1 and XTAL2 pins, or in the form
equivalent 16-bit digital representation, and these samples there- of an LVDS signal. The MCLK signal received by the AD7761 is
fore represent a quantized version of the analog input signal. used to define the modulator clock rate, fMOD, and in turn the
The Σ-Δ conversion technique is an oversampled architecture. sampling frequency of the modulator of 2 × fMOD. The same
This oversampled approach spreads the quantization noise over MCLK signal is also used to define the digital output clock,
a wide frequency band (see Figure 44). To reduce the quantization DCLK. The fMOD and DCLK internal signals are synchronous
noise in the signal band, the high order modulator shapes the noise with MCLK.
spectrum so that most of the noise energy is shifted out of the Figure 47 shows the clock tree from the MCLK input to the
band of interest (see Figure 45). The digital filter that follows the modulator, the digital filter, and the DCLK output. There are
modulator removes the large out of band quantization noise divider settings for MCLK and DCLK. These dividers, in
(see Figure 46). conjunction with the power mode and digital filter decimation
For further information on the basics as well as more advanced settings, are key to the operation of the AD7761.
concepts of Σ-Δ ADCs, see the MT-022 Tutorial and the The AD7761 has the ability to scale power consumption vs. the
MT-023 Tutorial. input bandwidth or desired noise. The user controls two para-
Digital filtering has certain advantages over analog filtering. First, it meters to achieve this: MCLK division and power mode. When
is insensitive to component tolerances and the variation of combined, these two settings determine the clock frequency of the
component parameters over time and temperature. And because modulator (fMOD) and the bias current supplied to each modulator.
digital filtering on the AD7761 occurs after the analog-to-digital The power mode (fast, median, or low power) sets the noise, speed
conversion, it can remove some of the noise injected during the capability, and current consumption of the modulator. The
conversion process; analog filtering cannot remove noise power mode is the dominant control for scaling the power
injected during conversion. Second, the digital filter combines consumption of the ADC. All settings of MCLK division and
low pass-band ripple with a steep roll-off and high stop-band power mode apply to all ADC channels.
attenuation, while also maintaining a linear phase response, DCLK_DIV
00: DCLK = MCLK/8
which is difficult to achieve in an analog filter implementation. 01: DCLK = MCLK/4
10: DCLK = MCLK/2
MCLK_DIV 11: DCLK = MCLK/1
MCLK/4
MCLK/8
QUANTIZATION NOISE MCLK/32
14285-054

fMOD/2 DCLK
BAND OF INTEREST
ADC DIGITAL DATA
FILTER INTERFACE DRDY
Figure 44. Σ-Δ ADC Quantization Noise (Linear Scale X-Axis) MODULATOR
CONTROL DOUTx

POWER MODES: DECIMATION RATES = ×32, ×64,

FAST ×128, ×256, ×512, ×1024

14285-057
MEDIAN
LOW POWER
NOISE SHAPING
Figure 47. Sampling Structure, Defined by the MCLK, DCLK_DIV, and
14285-055

fMOD/2 MCLK_DIV Settings

BAND OF INTEREST

Figure 45. Σ-Δ ADC Noise Shaping (Linear Scale X-Axis) The modulator clock frequency (fMOD) is determined by selecting
one of three clock divider settings: MCLK/4, MCLK/8, or
MCLK/32.
Although the MCLK division and power modes are independent
DIGITAL FILTER CUTOFF FREQUENCY
settings, there are restrictions that must be adhered to. A valid
range of modulator frequencies exists for each power mode.
14285-056

BAND OF INTEREST
fMOD/2 Table 9 describes this recommended range, which allows the
Figure 46. Σ-Δ ADC Digital Filter Cutoff Frequency (Linear Scale X-Axis) device to achieve the best performance while minimizing power
consumption. The AD7761 specifications do not cover the
performance and function beyond the maximum fMOD for a given
power mode.

Rev. A | Page 27 of 75
AD7761 Data Sheet
For example, to maximize the speed of conversion or input Configuration A
bandwidth in fast mode, an MCLK of 32.768 MHz is required To maximize the dynamic range, use the following settings:
and MCLK_DIV = 4 must be selected for a modulator
frequency of 8.192 MHz. • MCLK = 16 MHz
• Median power
Table 9. Recommended fMOD Range for Each Power Mode • fMOD = MCLK/4
Power Mode Recommended fMOD (MHz), MCLK = 32.768 MHz • Decimation = ×64 (digital filter setting)
Low Power 0.036 to 1.024 • ODR = 62.5 kHz
Median 1.024 to 4.096
Fast 4.096 to 8.192 This configuration maximizes the available decimation rate (or
oversampling ratio) for the bandwidth required and MCLK rate
Control of the settings for the power mode, the modulator available. The decimation averages the noise from the modulator,
frequency, and the data clock frequency differs in pin control maximizing the dynamic range.
mode vs. SPI control mode.
Configuration B
In SPI control mode, the user can program the power mode, the
To minimize power, use the following settings:
MCLK divider (MCLK_DIV), and the DCLK frequency using
Register 0x04 and Register 0x07 (see Table 38 and Table 41 for • MCLK = 16 MHz
register information). Independent selection of the power mode • Median power
and MCLK_DIV allows full freedom in the MCLK speed selection • fMOD = MCLK/8
to achieve a target modulator frequency. • Decimation = ×32 (digital filter setting)
In pin control mode, the MODEx pins determine the power • ODR = 62.5 kHz
mode, the modulator frequency, and the DCLK frequency. The This configuration reduces the clocking speed of the modulator
modulator frequency tracks the power mode. This means that and the digital filter.
fMOD is fixed at MCLK/32 for low power mode, MCLK/8 for
When compared to Configuration A, Configuration B saves
median mode, and MCLK/4 for fast mode (see Table 18).
48 mW of power. The trade-off in the case of Configuration B is
Example of Power vs. Noise Performance Optimization that the digital filter must run at a 2× lower decimation rate.
Depending on the bandwidth of interest for the measurement, This 2× reduction in decimation rate (or oversampling ratio)
the user can choose a strategy of either lowest current consumption results in a 3 dB reduction in the dynamic range vs. Config-
or highest resolution. This choice is due to an overlap in the uration A.
coverage of each power mode. The AD7761 offers the ability to Clocking Out the ADC Conversion Results (DCLK)
balance the MCLK division ratio with the rate of decimation
The AD7761 DCLK is a divided version of the master clock
(averaging) set in the digital filter. Lower power can be achieved
input. As shown in Figure 47, the DCLK_DIV setting determines
by using lower modulator clock frequencies. Conversely, the
the speed of the DCLK. DCLK is a continuous clock.
highest resolution can be achieved by using higher modulator
clock frequencies and maximizing the amount of oversampling. The user can set the DCLK frequency rate to one of four divisions
of MCLK: MCLK/1, MCLK/2, MCLK/4, and MCLK/8. Because
As an example, consider a system constraint with a maximum
there are eight channels and 24 bits of data per conversion, the
available MCLK of 16 MHz. The system is targeting a measure-
conversion time and the setting of DCLK directly determine the
ment bandwidth of approximately 25 kHz with the wideband
number of data output lines that are required via the FORMATx
filter, setting the output data rate of the AD7761 to 62.5 kHz.
pin settings. Thus, the intended minimum decimation and desired
Because of the low MCLK frequency available and the system
DCLK_DIV setting must be understood prior to choosing the
power budget, median power mode is used.
setting of the FORMATx pins.
In median power mode, this 25 kHz input bandwidth can be
achieved by setting the MCLK division and decimation ratio to NOISE PERFORMANCE AND RESOLUTION
balance, using two configurations (Configuration A and Table 10 and Table 11 show the noise performance for the
Configuration B). This flexibility is possible in SPI control wideband and sinc5 digital filters of the AD7761 for various
mode only. output data rates and power modes. The noise values specified
are typical for the bipolar input range with an external 4.096 V
reference (VREF).
The LSB size with 4.096 V reference is 125 µV, and is calculated
as follows:
LSB (V) = (2 × VREF)/216

Rev. A | Page 28 of 75
Data Sheet AD7761
Table 10. Wideband Filter Noise: Performance vs. Output Data Rate
Output Data Rate (kSPS) −3 dB Bandwidth (kHz) RMS Noise (µV)
Fast Mode
256 110.8 11.58
128 55.4 7.77
64 27.7 5.42
32 13.9 3.82
16 6.9 2.72
8 3.5 1.94
Median Mode
128 55.4 11.36
64 27.7 7.6
32 13.9 5.3
16 6.9 3.74
8 3.5 2.64
4 1.7 1.87
Low Power Mode
32 13.9 11.28
16 6.9 7.54
8 3.5 5.25
4 1.7 3.71
2 0.87 2.62
1 0.43 1.85

Table 11. Sinc5 Filter Noise: Performance vs. Output Data Rate
Output Data Rate (kSPS) −3 dB Bandwidth (kHz) RMS Noise (µV)
Fast Mode
256 52.224 7.83
128 26.112 5.43
64 13.056 3.82
32 6.528 2.71
16 3.264 1.93
8 1.632 1.39
Median Mode
128 26.112 7.68
64 13.056 5.3
32 6.528 3.72
16 3.264 2.64
8 1.632 1.87
4 0.816 1.33
Low Power Mode
32 6.528 7.65
16 3.264 5.26
8 1.632 3.7
4 0.816 2.61
2 0.408 1.85
1 0.204 1.31

Rev. A | Page 29 of 75
AD7761 Data Sheet

APPLICATIONS INFORMATION
The AD7761 offers users a multichannel platform measurement • Control of reference and analog input precharge buffers on
solution for ac and dc signal processing. a per channel basis.
Flexible filtering allows the AD7761 to be configured to • Wideband, low ripple, digital filter for ac measurement.
simultaneously sample ac and dc signals on a per channel basis. • Fast sinc5 filter for precision low frequency measurement.
Power scaling allows users to trade off the input bandwidth of • Two channel modes, defined by the user selected filter choice,
the measurement vs. the current consumption. This ability, and decimation ratios, can be defined for use on different
coupled with the flexibility of the digital filtering, allows the ADC channels. This enables optimization of the input
user to optimize the energy efficiency of the measurement, bandwidth versus the signal of interest.
while still meeting power, bandwidth, and performance targets. • Option of SPI or pin strapped control and configuration.
Key capabilities that allow users to choose the AD7761 as their • Offset, gain, and phase calibration registers per channel.
platform high resolution ADC are highlighted as follows: • Common-mode voltage output buffer for use by a driver
amplifier.
• Eight fully differential or pseudo differential analog inputs.
• On-board AVDD2 and IOVDD LDOs for the low power,
• Fast throughput simultaneous sampling ADCs catering for
1.8 V, internal circuitry.
input signals up to 110.8 kHz.
• Three selectable power modes (fast, median, and low Refer to Figure 48 and Table 12 for the typical connections
power) for scaling the current consumption and input and minimum requirements to get started using the AD7761.
bandwidth of the ADC for optimal measurement Table 13 shows the typical power and performance of the
efficiency. AD7761 for the available power modes, for each filter type.
• Analog input precharge and reference precharge buffers
reduce the drive requirements of external amplifiers.

AVDD1A, AVDD2A,
AVDD1B AVDD2B IOVDD
SUGGESTED OP AMPS:
FAST MODE: ADA4896-2 OR ADA4807-2
MEDIAN MODE: ADA4940-2 OR ADA4807-2
LOW POWER MODE: ADA4805-2

REGCAPA, DREGCAP SYNC_IN

REGCAPB
VCM AD7761 SYNC_OUT
START
RESET
FORMATx
DRDY
AIN0+ DCLK
5V DOUT0
AIN0– ADC
SINC5 DATA DOUT1
LOW LATENCY FILTER SERIAL DOUT2
AIN7+ INTERFACE DOUT3
ADA4940-1/ Σ-Δ DOUT4
SPI
ADA4940-2 AIN7– ADC CONTROL
DOUT5
INTERFACE DOUT6
WIDEBAND DOUT7
LOW RIPPLE FILTER

PRECHARGE
BUFFERS ST0/CS
ST1/SCLK
DEC0/SDO
DEC1/SDI
FILTER/GPIO4

AVSS REFx+ REFx– XTAL2/MCLK XTAL1 PIN/SPI MODE3/GPIO3

VIN TO
– MODE0/GPIO0
VIN VOUT +
ADR4540
ADA4841-1
14285-058

Figure 48. Typical Connection Diagram

Rev. A | Page 30 of 75
Data Sheet AD7761
Table 12. Requirements to Operate the AD7761
Requirement Description
Power Supplies 5 V AVDD1 supply, 2.25 V to 5 V AVDD2 supply, 1.8 V or 2.5 V to 3.3 V IOVDD supply (ADP7104/ADP7118)
External Reference 2.5 V, 4.096 V, or 5 V (ADR4525, ADR4540, or ADR4550)
External Driver Amplifiers The ADA4896-2, the ADA4940-1/ADA4940-2, the ADA4805-2, and the ADA4807-2
External Clock Crystal or a CMOS/LVDS clock for the ADC modulator sampling
FPGA or DSP Input/output voltage of 2.5 V to 3.6 V, or 1.8 V (see the 1.8 V IOVDD Operation section)

Table 13. Speed, Dynamic Range, THD, and Power Overview; Eight Channels Active, Decimate by 321
Output Sinc5 Filter Wideband Filter
Power Data Rate THD Dynamic Bandwidth Power Dissipation Dynamic Bandwidth Power Dissipation
Mode (kSPS) (dB) Range (dB) (kHz) (mW per channel) Range (dB) (kHz) (mW per channel)
Fast 256 −115 97.7 52.224 41 97.7 110.8 52
Median 128 −120 97.7 26.112 22 97.7 55.4 28
Low Power 32 −120 97.7 6.528 8.5 97.7 13.9 9.5
1
Analog precharge buffers on, precharge reference buffers and VCM disabled, typical values, AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, VREF = 4.096 V, MCLK = 32.768 MHz,
DCLK = MCLK/4, TA = 25°C.

POWER SUPPLIES IOVDD powers the internal 1.8 V digital LDO regulator. This
The AD7761 has three independent power supplies: AVDD1 regulator powers the digital logic of the ADC. IOVDD also sets
(given by the AVDD1A pin and the AVDD2A pin), AVDD2 the voltage levels for the SPI interface of the ADC. IOVDD is
(given by the AVDD2A pin and the AVDD2B pin), and IOVDD. referenced to DGND, and the voltage on IOVDD can vary from
2.25 V (minimum) to 3.6 V (maximum), with respect to DGND.
The reference potentials for these supplies are AVSS and DGND. IOVDD can also be configured to run at 1.8 V. In this case, IOVDD
Tie all the AVSS supply pins (AVSS1A, AVSS1B, AVSS2A, AVSS2B, and DREGCAP must be tied together and must be within the
and AVSS) to the same potential with respect to DGND. AVDD1A, range of 1.72 V (minimum) to 1.88 V (maximum), with respect
AVDD1B, AVDD2A, and AVDD2B are referenced to this AVSS to DGND. See the 1.8 V IOVDD Operation section for more
rail. IOVDD is referenced to DGND. information on operating the AD7761 at 1.8 V IOVDD.
The supplies can be powered within the following ranges: Recommended Power Supply Configuration
• AVDD1 = 5 V ± 10%, relative to AVSS Analog Devices, Inc., has a wide range of power management
• AVDD2 = 2 V to 5.5 V, relative to AVSS products to meet the requirements of most high performance
• IOVDD (with internal regulator) = 2.25 V to 3.6 V, relative signal chains.
to DGND An example of a power solution that uses the ADP7118 is shown
• IOVDD (bypassing regulator) = 1.72 V to 1.88 V, relative to in Figure 49. The ADP7118 provides positive supply rails for
DGND optimal converter performance, creating either a single 5 V,
• AVSS = −2.75 V to 0 V, relative to DGND 3.3 V, or dual AVDD1 and AVDD2/IOVDD, depending on the
The AVDD1A and AVDD1B (AVDD1) supplies power the analog required supply configuration. The ADP7118 can operate from
front end, reference input, and common-mode output circuitry. input voltages of up to 20 V.
AVDD1 is referenced to AVSS, and all AVDD1 supplies must be 12V ADP7118 5V: AVDD1x
INPUT LDO
tied to the same potential with respect to AVSS. If AVDD1 supplies
14285-059

are used in a ±2.5 V split supply configuration, the ADC inputs are ADP7118 3.3V: AVDD2x/IOVDD
LDO
truly bipolar. When using split supplies, reference the absolute
maximum ratings, which apply to the voltage allowed between Figure 49. Power Supply Configuration
the AVSS and IOVDD supplies. Alternatively, the ADP7112 or ADP7104 can be selected for
The AVDD2A and AVDD2B (AVDD2) supplies connect to powering the AD7761. Refer to the AN-1120 Application Note
internal 1.8 V analog LDO regulators. The regulators power the for more information regarding low noise LDO performance
ADC core. AVDD2 is referenced to AVSS, and all AVDD2 supplies and power supply filtering.
must be tied to the same potential with respect to AVSS. The
voltage on AVDD2 can range from 2 V (minimum) to 5.5 V
(maximum), with respect to AVSS.

Rev. A | Page 31 of 75
AD7761 Data Sheet
1.8 V IOVDD Operation DEVICE CONFIGURATION
The AD7761 contains an internal 1.8 V LDO on the IOVDD The AD7761 has independent paths for reading data from the
supply to regulate the IOVDD down to the operating voltage of the ADC conversions and for controlling the device functionality.
digital core. This internal LDO allows the internal logic to operate
For control, the device can be configured in either of two
efficiently at 1.8 V and the input/output logic to operate at the
modes. The two modes of configuration are as follows:
level set by IOVDD. The IOVDD supply is rated from 2.25 V to
3.6 V for normal operation, and 1.8 V for LDO bypass setup. • Pin control mode: pin strapped digital logic inputs (which
allows a subset of the configurability options)
38 SYNC_OUT
• SPI control mode: over a 3-wire or 4-wire SPI interface
(complete configurability)
37 START

36 SYNC_IN 1.8V IOVDD

SUPPLY
IOVDD 35
On power-up, the state of the PIN/SPI pin determines the mode
DREGCAP 34
used. Immediately after power-up, the user must apply a soft or
DGND 33
hard reset to the device when using either control mode.
28 29 30 31 32

Interface Data Format

XTAL1
XTAL2/MCLK
DCLK

RESET
DRDY

When operating the device, the data format of the serial interface is
14285-060

determined by the FORMATx pins. Table 30 shows that each ADC

can be assigned a DOUTx pin, or, alternatively, the data can be
Figure 50. DREGCAP and IOVDD Connection Diagram for 1.8 V IOVDD
Operation arranged to share the DOUTx pins in a time division multiplexed
manner. For more details, see the Data Interface section.
Users can bypass the LDO by shorting the DREGCAP pin to
IOVDD (see Figure 50), which pulls the internal LDO out of PIN CONTROL MODE
regulation and sets the internal core voltage and input/output Pin control mode eliminates the need for an SPI communication
logic levels to the IOVDD level. When bypassing the internal interface. When a single known configuration is required by the
LDO, the maximum operating voltage of the IOVDD supply is user, or when only limited reconfiguration is required, the number
equal to the maximum operating voltage of the internal digital core, of signals that require routing to the digital host can be reduced
which is 1.72 V to 1.88 V. using this mode. Pin control mode is useful in digitally isolated
Analog Supply Internal Connectivity applications where minimal adjustment of the configuration is
needed. Pin control offers a subset of the core functionality and
The AD7761 has two analog supply rails, AVDD1 and AVDD2,
ensures a known state of operation after power-up, reset, or a
which are both referred to AVSS. These supplies are completely
fault condition on the power supply. In pin control mode, the
separate from the digital pins, IOVDD, DREGCAP, and DGND. To
analog input precharge buffers are enabled by default for best
achieve optimal performance and isolation of the ADCs, more than
performance. The reference input precharge buffers are disabled
one device pin supplies these analog rails to the internal ADCs.
in pin control mode.
• AVSS1A (Pin 3) and AVSS2A (Pin 62) are internally
After any change to the configuration in pin control mode, the
connected.
user must provide a sync signal to the AD7761 by applying the
• AVSS (Pin 54) is connected to the substrate, and is connected
appropriate pulse to the START pin or the SYNC_IN pin to
internally to AVSS1B (Pin 46) and AVSS2B (Pin 51).
ensure that the configuration changes are applied correctly to
• The following supply and reference input pins are separate
the ADC and the digital filters.
on chip: AVDD1A, AVDD1B, AVDD2A, AVDD2B,
REF1+, REF1−, REF2+, and REF2−. Setting the Filter
The filter function chooses between the two filter settings. In
The details of which individual supplies are shorted internally are
pin control mode, all ADC channels use the same filter type,
given in this section for informational purposes. In general,
which is selected by the FILTER pin, as shown in Table 14.
connect the supplies as described in the Power Supplies section.
Table 14. FILTER Control Pin
Logic Level Function
1 Sinc5 filter selected
0 Wideband filter selected

Rev. A | Page 32 of 75
Data Sheet AD7761
Setting the Decimation Rate The MODEx pins map to 16 distinct settings. The settings are
Pin control mode allows selection from four possible decimation selected to optimize the use cases of the AD7761, allowing the
rates. The decimation rate is selected via the DEC1 and DEC0 pins. user to reduce the DCLK frequency for lower, less demanding
The chosen decimation rate is used on all ADC channels. Table 15 power modes and selecting either the one-shot or standard
shows the truth table for the DECx pins. conversion modes.
See Table 18 for the complete selection of operating modes that
Table 15. Decimation Rate Control Pins Truth Table
are available via the MODEx pins in pin control mode.
DEC1 DEC0 Decimation Rate
The power mode setting automatically scales the bias currents
0 0 ×32
of the ADC and divides the applied MCLK signal to the correct
0 1 ×64
setting for that mode. Note that this is not the same as using SPI
1 0 ×128
control mode, where separate bit fields exist to control the bias
1 1 ×1024
currents of the ADC and MCLK division.
Operating Mode In pin control mode, the modulator rate is fixed for each power
The MODE3 to MODE0 pins determine the configuration of all mode to achieve the best performance. Table 17 shows the
channels when using pin control mode. The variables controlled by modulator division for each power mode.
the MODEx pins are shown in Table 16. The user selects how
Table 17. Modulator Rate, Pin Control Mode
much current the device consumes, the sampling speed of the
ADC (power mode), how fast the ADC result is received by the Power Mode Modulator Rate, fMOD
digital host (DCLK_DIV), and how the ADC conversion is Fast MCLK/4
initiated (conversion operation). Figure 51 illustrates the inputs Median MCLK/8
used to configure the device in pin control mode. Low power MCLK/32

Table 16. MODEx Pins: Variables for Control Diagnostics

Control Variable Possible Settings Pin control mode offers a subset of diagnostics features. Internal
Sampling Speed/Power Consumption Fast errors are reported in the status header output with the data
Power Mode Median conversion results for each channel.
Low power Internal cyclic redundancy check (CRC) errors, memory map
Data Clock Output Frequency (DCLK_DIV) DCLK = MCLK/1 flipped bits, and external clocks not detected are reported by Bit
DCLK = MCLK/2 7 of the status header and indicate that a reset is required. The
DCLK = MCLK/4 status header also reports filter not settled, filter type, and filter
DCLK = MCLK/8 saturated signals. Users can determine when to ignore data by
Conversion Operation Standard conversion monitoring these error flags. For more information on the status
One-shot conversion header, see the ADC Conversion Output: Header and Data section.

PIN CONTROL MODE CHANNEL STANDBY OUTPUT DATA FORMAT

CH 0 TO CH 3 STANDBY 1 CHANNEL PER PIN
PIN/SPI = LOW CH 4 TO CH 7 STANDBY 4 CHANNELS PER PIN
8 CHANNELS PER PIN

PIN/SPI ST0 FORMAT0

ST1 FORMAT1
DOUT0
DOUT1
TO DSP/
FPGA
OPTION TO AD7761
SELECT FILTER
BETWEEN FILTERS DOUT7

MODE0
MODE1
DEC0/ MODE2
DEC1 MODE3

DECIMATION RATES MODE CONFIGURATION

/32 MODE 0x0 TO MODE 0xF
/64
14285-061

SET UP VIA 4 PINS

/128
/1024

Figure 51. Pin Configurable Functions

Rev. A | Page 33 of 75
AD7761 Data Sheet
Table 18. MODEx Selection Details: Pin Control Mode
Mode Hex. MODE3 MODE2 MODE1 MODE0 Power Mode DCLK Frequency Data Conversion
0x0 0 0 0 0 Low power MCLK/1 Standard
0x1 0 0 0 1 Low power MCLK/2 Standard
0x2 0 0 1 0 Low power MCLK/4 Standard
0x3 0 0 1 1 Low power MCLK/8 Standard
0x4 0 1 0 0 Median MCLK/1 Standard
0x5 0 1 0 1 Median MCLK/2 Standard
0x6 0 1 1 0 Median MCLK/4 Standard
0x7 0 1 1 1 Median MCLK/8 Standard
0x8 1 0 0 0 Fast MCLK/1 Standard
0x9 1 0 0 1 Fast MCLK/2 Standard
0xA 1 0 1 0 Fast MCLK/4 Standard
0xB 1 0 1 1 Fast MCLK/8 Standard
0xC 1 1 0 0 Low power MCLK/1 One-shot
0xD 1 1 0 1 Median MCLK/1 One-shot
0xE 1 1 1 0 Fast MCLK/2 One-shot
0xF 1 1 1 1 Fast MCLK/1 One-shot

Table 19. MODEx Example Selection

Mode Hex MODE3 MODE2 MODE1 MODE0 Power Mode DCLK Frequency Data Conversion
0x3 0 0 1 1 Low Power MCLK/8 Standard

Configuration Example Channel Standby

In the example shown in Table 19, the lowest current Table 20 shows how the user can put channels into standby mode.
consumption is used, and the AD7761 is connected to an FPGA. Set either ST0 or ST1 to Logic 1 to place banks of four channels
The FORMATx pins are set such that all eight data outputs, into standby mode. When in standby mode, the disabled channels
DOUT0 to DOUT7, connect to the FPGA. For the lowest hold their position in the output data stream. The 8-bit header
power, the lowest DCLK frequency is used. The input bandwidth and 16-bit conversion results are set to all zeros when the ADC
is set through the combination of selecting decimation by 64 channels are set to standby.
and selecting the wideband filter. The VCM voltage output is associated with the Channel 0
ODR = fMOD ÷ Decimation Ratio circuitry. If Channel 0 is put into standby mode, the VCM
where: voltage output is also disabled for maximum power savings.
fMOD is MCLK/32 for low power mode (see Table 17). Channel 0 must be enabled while VCM is being used externally
Decimation Ratio = 64. to the AD7761.

Thus, for this example, where MCLK = 32.768 MHz, The crystal excitation circuitry is associated with the Channel 4
circuitry. If Channel 4 is put into standby mode, the crystal
ODR = (32.768 MHz/32) ÷ 64 = 16 kHz circuitry is also disabled for maximum power savings. Channel 4
Minimizing the DCLK frequency means selecting DCLK = must be enabled while the external crystal is used on the AD7761.
MCLK/8, which results in a 4 MHz DCLK signal. The period of
DCLK in this case is 1/4 MHz = 250 ns. The data conversion on Table 20. Truth Table for the AD7761 ST0 and ST1 Pins
each DOUTx pin is 24 bits long. The conversion data takes 24 × ST1 ST0 Function
250 ns = 6 μs to be output. All 24 bits must be output within the 0 0 All channels operational.
ODR period of 1/16 kHz, which is approximately 64 μs. In this 0 1 Channel 0 to Channel 3 in
standby. Channel 4 to
case, the 6 μs required to read out the conversion data is well
Channel 7 operational.
within the 64 μs between conversion outputs. Therefore, this
1 0 Channel 4 to Channel 7 in
combination, which is summarized in Table 19, is viable for use. standby. Channel 0 to
Channel 3 operational.
1 1 All channels in standby.

Rev. A | Page 34 of 75
Data Sheet AD7761
SPI CONTROL SPI Interface Details
The AD7761 has a 4-wire SPI interface that is compatible with Each SPI access frame is 16 bits long. The MSB (Bit 15) of the
QSPI™, MICROWIRE®, and DSPs. The interface operates in SPI SDI command is the R/W bit; 1 = read and 0 = write. Bits[14:8]
Mode 0. In SPI Mode 0, SCLK idles low, the falling edge of CS of the SDI command are the address bits.
clocks out the MSB, the falling edge of SCLK is the drive edge, The SPI control interface uses an off frame protocol. This means
and the rising edge of SCLK is the sample edge. This means that that the master (FPGA/DSP) communicates with the AD7761 in
data is clocked out on the falling/drive edge and data is clocked two frames. The first frame sends a 16-bit instruction (R/W,
in on the rising/sample edge. address, and data) and the second frame is the response where
the AD7761 sends 16 bits back to the master.
During the master write command, the SDO output contains
DRIVE EDGE SAMPLE EDGE
eight leading zeros, followed by eight bits of data, as shown in
Figure 54.

14285-062
Figure 53 shows the off frame protocol. Register access responses
Figure 52. SPI Mode 0 SCLK Edges are always offset by one CS frame. In Figure 53, the response
Accessing the ADC Register Map (read RESP 1) to the first command (CMD 1) is output by the
To use SPI control mode, set the PIN/SPI pin to logic high. The AD7761 during the following CS frame at the same time as the
SPI control operates as a 16-bit, 4-wire interface, allowing read second command (CMD 2) is being sent.
and write access. Figure 54 shows the interface format between SCLK

the AD7761 and the digital host.

CS
The SPI serial control interface of the AD7761 is an independent
path for controlling and monitoring the device. There is no direct SDI CMD 1 CMD 2

14285-064
link to the data interface. The timing of MCLK and DCLK is
SDO READ RESP 1
not directly related to the timing of the SPI control interface.
Figure 53. Off Frame Protocol
However, the user must ensure that the SPI reads and writes
satisfy the minimum t30 specification (see Table 3 and Table 5) SPI Control Interface Error Handling
so that the AD7761 can detect changes to the register map. The AD7761 SPI control interface detects whether it has
SPI access is ignored during the period immediately after a received an illegal command. An illegal command is a write to a
reset. Allow the full ADC start-up time after reset (see Table 1) read only register, a write to a register address that does not
to elapse before accessing the AD7761 over the SPI interface. exist, or a read from a register address that does not exist. If any of
these illegal commands are received by the AD7761, the device
responds with an error output of 0x0E00.

SCLK

CS

SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
14285-063

SDO 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 54. Write/Read Command

Rev. A | Page 35 of 75
AD7761 Data Sheet
SPI Reset Configuration When different decimation rates are selected on different channels,
After a power-on or reset, the AD7761 default configuration is set the AD7761 outputs a data ready signal at the fastest selected
to the following low current consumption settings: decimation rate. Any channel that runs at a lower output data rate
is updated only at that slower rate. In between valid result data, the
• Low power mode with MCLK/32. data for that channel is set to zero and the repeated data bit is set in
• Interface configuration of DCLK = MCLK/8, header the header status bits to distinguish it from a real conversion result
output enabled, and CRC disabled. (see the ADC Conversion Output: Header and Data section for
• Filter configuration of Channel Mode A and Channel Mode B more information).
is set to sinc5 and decimation = ×1024. Channel mode
On the AD7761, consider Channel Mode A as the primary group.
select is set to 0x00, and all channels are assigned to
In this respect, it is recommended that there always be at least one
Channel Mode A.
channel assigned to Channel Mode A. If all eight channels of the
• Channel configuration of Channel 0 to Channel 7 is enabled,
AD7761 are assigned to Channel Mode B, conversion data is not
with the analog input buffers enabled. The reference precharge
output on the data interface for any of the channels.
buffers are disabled. The offset, gain, and phase calibration
are set to the zero position. Table 21. Channel Mode A/Channel Mode B, Register 0x01
• Continuous conversion mode is enabled. and Register 0x02
Bits Bit Name Setting Description Reset Access
SPI CONTROL FUNCTIONALITY
3 FILTER_TYPE_x Filter output 0x1 RW
SPI control offers the superset of flexibility and diagnostics to 0 Wideband filter
the user. The following sections highlight the functionality and 1 Sinc5 filter
diagnostics offered when SPI control is used. [2:0] DEC_RATE_x Decimation rate 0x5 RW
After any change to these configuration register settings, the 000 to ×32 to ×1024
101
user must provide a sync signal to the AD7761 through either
the SPI_SYNC command, or by applying the appropriate pulse Table 22. Channel Mode Selection, Register 0x03
to the START pin or SYNC_IN pin to ensure that the configuration Bits Bit Name Setting Description Reset Access
changes are applied correctly to the ADC and digital filters. [7:0] CH_x_MODE Channel x 0x0 RW
Channel Configuration 0 Mode A
1 Mode B
The AD7761 has eight fully differential analog input channels.
The channel configuration registers allow the channels to be
Reset over SPI Control Interface
individually configured to adapt to the measurement required
on that channel. Channels can be enabled or disabled using the Two successive commands must be written to the AD7761 data
channel standby register, Register 0x00. Analog input and control register to initiate a full reset of the device over the SPI
reference precharge buffers can be assigned per input terminal. interface. This action fully resets all registers to the default
Gain, offset, and phase calibration can be controlled on a per conditions. Details of the commands and their sequence are
channel basis using the calibration registers. See the Per shown in Table 40.
Channel Calibration Gain, Offset, and Sync Phase section for After a reset over the SPI control interface, the AD7761 responds
more information. to the first command sent to the device with 0x0E00. This
Channel Modes response, in addition to the fact that all registers have assumed
their default values, indicates that the software reset succeeded.
In SPI control mode, the user can set up two channel modes,
Channel Mode A (Register 0x01), and Channel Mode B Sleep Mode
(Register 0x02). Each channel mode register can have a specific Sleep mode puts the AD7761 into its lowest power mode. In
filter type and decimation ratio. Using the channel mode select sleep mode, all ADCs are disabled and a large portion of the digital
register (Register 0x03), the user can assign each channel to either core is inactive.
Channel Mode A or Channel Mode B, which maps that mode to The AD7761 SPI remains active and is available to the user when in
the required ADC channels. These modes allow different filter sleep mode. Write to Register 0x04, Bit 7 to exit sleep mode. For
types and decimation rates to be selected and mapped to any of the the lowest power consumption, select the sinc5 filter before
ADC channels. entering sleep mode.

Rev. A | Page 36 of 75
Data Sheet AD7761
Channel Standby Mode Interface Configuration
For efficient power usage, place selected channels into standby The data interface is a master output interface, where ADC
mode when not in use. Setting the bits in Register 0x00 disables conversion results are output by the AD7761 at a rate based on
the corresponding channel (see Table 34). For maximum power the mode selected. The interface consists of a data clock (DCLK),
savings, switch disabled channels to the sinc5 filter using the the data ready (DRDY) framing output, and the data output
channel mode configurations, which disables some clocks pins (DOUT0 to DOUT7).
associated with the wideband filters of those channels.
The interface can be configured to output conversion data on
The VCM voltage output is associated with the Channel 0 circuitry. one, two, or eight of the DOUTx pins. The DOUTx configuration
If Channel 0 is put into standby mode, the VCM voltage output is for the AD7761 is selected using the FORMATx pins (see Table 30).
also disabled for maximum power savings. Channel 0 must be
The DCLK rate is a direct division of the MCLK input and can
enabled while VCM is being used externally to the AD7761.
be controlled using Bits[1:0] of Register 0x07. The minimum
The crystal excitation circuitry is associated with the Channel 4 DCLK rate can be calculated as
circuitry. If Channel 4 is put into standby mode, the crystal
DCLK (minimum) = Output Data Rate × Channels per
circuitry is also disabled for maximum power savings. Channel 4
DOUTx × 24 bits
must be enabled while the external crystal is used on the AD7761.
where MCLK ≥ DCLK.
Clocking Selections
With eight ADCs enabled, an MCLK rate of 32.768 MHz, an ODR
The internal modulator frequency (fMOD) used by each of the ADCs
of 256 kSPS, and two DOUTx channels, DCLK (minimum) is
in the AD7761 is derived from the externally applied MCLK
signal. The MCLK division bits allow the user to control the 256 kSPS × 4 channels per DOUTx × 24 bits = 24.576 MHz
ratio between the MCLK frequency and the internal modulator where DCLK = MCLK/1.
clock frequency. This control allows the user to select the division
For more information on the status header, CRC, and interface
ratio that is best for their configuration.
configuration, see the Data Interface section.
The appropriate clock configuration depends on the power mode,
CRC Protection
the decimation rate, and the base MCLK frequency available in
the system. See the Clocking, Sampling Tree section for further The AD7761 can be configured to output a CRC message per
information on setting MCLK_DIV correctly. channel every 4 or 16 samples. This function is available only
with SPI control. CRC is enabled in the interface control register,
MCLK Source Selection Register 0x07 (see the CRC Check on Data Interface section).
The following clocking options are available as the MCLK input
ADC Synchronization over SPI
source in SPI control mode:
The ADC synchronization over SPI allows the user to request a
• LVDS synchronization pulse to the ADCs over the SPI interface. To
• External crystal initiate the synchronization in this manner, write to Bit 7 in
• CMOS input MCLK Register 0x06 twice.
Setting CLK_SEL to logic low configures the AD7761 for correct First, the user must write a 0, which sets SYNC_OUT low, and
operation using a CMOS clock. Setting CLK_SEL to logic high then write a 1 to set the SYNC_OUT logic high again.
enables the use of an external crystal. In SPI control mode, the
The SPI_SYNC command is recognized after the last rising
FILTER pin must be set to Logic 1 for operation of the external
edge of SCLK in the SPI instruction, where the SPI_SYNC bit is
crystal.
changed from low to high. The SPI_SYNC command is then
If CLK_SEL is set to logic high and Bit 3 of Register 0x04 is also output synchronously to the AD7761 MCLK signal on
set, the application of an LVDS clock signal to the MCLK pin is the SYNC_OUT pin. The user must connect the SYNC_OUT
enabled. LVDS clocking is exclusive to SPI control mode and signal to the SYNC_IN pin on the PCB.
requires the register selection for operation (see Table 38).
The DCLK rate is derived from MCLK. DCLK division (the
ratio between MCLK and DCLK) is controlled in the interface
configuration selection register, Register 0x07 (see Table 41).

Rev. A | Page 37 of 75
AD7761 Data Sheet
IOVDD
Per Channel Calibration Gain, Offset, and Sync Phase
AD7761 The user can adjust the gain, offset, and sync phase of the
START AD7761. These options are available only in SPI control mode.
SYNC_OUT
Further register information and calibration instructions are
MASTER MCLK SYNCHRONIZATION
CLOCK LOGIC

available in the Offset Registers section, the Gain Registers section,

DIGITAL FILTER DRDY and the Sync Phase Offset Registers section. See the Calibration
DOUT0
SPI INTERFACE SYNC_IN
DOUT1 section for information on calibration equations.

DSP/
GPIOs

14285-065
FPGA
The AD7761 has five GPIO pins available when operating in SPI
Figure 55. Connection Diagram for Synchronization Using SPI_SYNC
control mode. For further information on GPIO configuration,
see the GPIO Functionality section.
The SYNC_OUT pin can also be routed to the SYNC_IN pins of
other AD7761 devices, allowing simultaneous sampling to occur SPI CONTROL MODE EXTRA DIAGNOSTIC
across larger channel count systems. Any daisy-chained system of FEATURES
AD7761 devices requires that all ADCs be synchronized. RAM Built In Self Test
In a daisy-chained system of AD7761 devices, two successive The read only memory (RAM) built in self test (BIST) is a
synchronization pulses must be applied to guarantee that all coefficient check for the digital filters. The AD7761 DSP path uses
ADCs are synchronized. Two synchronization pulses are also some internal memories for storing data associated with filtering
required in a system of more than one AD7761 device sharing a and calibration. A user may, if desired, initiate a built in self test
single MCLK signal, where the DRDY pin of only one device is (BIST) of these memories. Normal conversions are not possible
used to detect new data. while BIST is running. The test is started by writing to the BIST
control register, Register 0x08. The results and status of the test are
As per any synchronization pulse present on the SYNC_IN pin, available in the status register, Register 0x09 (see Table 43).
the digital filters of the AD7761 are reset by the SPI_SYNC
command. The full settling time of the filters must then elapse Normal ADC conversion is disrupted when this test is run. A
before valid data is output on the data interface. synchronization pulse is required after this test is complete to
resume normal ADC operation.
Analog Input Precharge Buffers
Revision Identification Number
The AD7761 contains precharge buffers on each analog input to
ease the drive requirements on the external amplifier. Each analog The AD7761 contains an identification register that is accessible
input precharge buffer can be enabled or disabled using the analog in SPI control mode, the revision identification register. This
input precharge buffer registers (see Table 48 and Table 49). register is an excellent way to verify the correct operation of the
When writing to these registers, the user must write the inverse serial control interface. Register information is available in the
of the required bit settings. For example, to clear Bit 1 of this Revision Identification Register section.
register, the user must write 0x01 to the register. This clears Diagnostic Meter Mode
Bit 1 and sets all other bits. If the user reads the register again The diagnostic metering mode can be used to verify the
after writing 0x01, the data read is 0xFE, as required. functionality of each ADC by internally passing a positive full-
Reference Precharge Buffers scale, midscale, or negative full-scale voltage to the ADC. The
The AD7761 contains reference precharge buffers on each user can then read the resulting ADC conversion result to
reference input to ease the drive requirements on the external determine that the ADC is operating correctly. To configure
reference and help to settle any nonlinearity on the reference ADC conversion diagnostics, see the ADC Diagnostic Receive
inputs. Each reference precharge buffer can be enabled or Select Register section and the ADC Diagnostic Control
disabled using the reference precharge buffer registers (see Register section.
Table 50 and Table 51).

Rev. A | Page 38 of 75
Data Sheet AD7761

CIRCUIT INFORMATION
CORE SIGNAL CHAIN of power modes gives more flexibility to control the bandwidth
Each ADC channel on the AD7761 has an identical signal path and power dissipation for the AD7761. Table 9 shows the
from the analog input pins to the data interface. Figure 57 shows recommended fMOD frequencies for each power mode, and
a top level implementation of the core signal chain. Each ADC Table 38 shows the register information for the AD7761.
channel has its own Σ-Δ modulator that oversamples the analog
input and passes the digital representation to the digital filter block.

ADC CODE (TWOS COMPLEMENT)

The modulator sampling frequency (fMOD) ranges are explained 011 ... 111
in the Clocking, Sampling Tree, and Power Scaling section. The 011 ... 110
011 ... 101
data is filtered, scaled for gain and offset (depending on user
settings), and then output on the data interface. Control of the
flexible settings for the signal chain is provided by either using the
pin control or the SPI control mode, set at power-up by the state of
the PIN/SPI input pin.
The AD7761 can use up to a 5 V reference and converts the 100 ... 010
100 ... 001
differential voltage between the analog inputs (AINx+ and AINx−) 100 ... 000
into a digital output. The analog inputs can be configured as either –FS –FS + 1LSB +FS – 1LSB
differential or pseudo differential inputs. As a pseudo differential

14285-066
–FS + 0.5LSB +FS – 1.5LSB

input, either AINx+ or AINx− can be connected to a constant ANALOG INPUT

input voltage (such as 0 V, AVSS, or some other reference voltage). Figure 56. ADC Ideal Transfer Functions (FS is Full Scale)
The ADC converts the voltage difference between the analog
Table 23. Output Codes and Ideal Input Voltages
input pins into a digital code on the output. Using a common-
Analog Input
mode voltage of AVDD1/2 for the analog inputs, AINx+ and (AINx+ − (AINx−)) Digital Output Code,
AINx−, maximizes the ADC input range. The 16-bit conversion Description VREF = 4.096 V Twos Complement (Hex.)
result is in twos complement, MSB first, format. Figure 56 FS − 1 LSB +4.095875 V 0x7FFF
shows the ideal transfer functions for the AD7761. Midscale + 1 LSB +125 µV 0x0001
ADC Power Modes Midscale 0V 0x0000
The AD7761 has three selectable power modes. In pin control Midscale − 1 LSB −125 µV 0xFFFF
mode, the modulator rate and power mode are tied together for −FS + 1 LSB −4.095875 V 0x8001
best performance. In SPI control mode, the user can select the −FS −4.096 V 0x8000
power mode and modulator MCLK divider settings. The choice

MCLK START SYNC_OUT SYNC_IN RESET

SIGNAL CHAIN
PRECHARGE FOR SINGLE CHANNEL
BUFFER
DRDY
AINx+ DATA
Σ-Δ DIGITAL
MODULATOR FILTER INTERFACE DOUTx
AINx– CONTROL
DCLK
ESD
PROTECTION CONTROL BLOCK

PIN/SPI

CONTROL
OPTION PIN CONTROL SPI CONTROL
PIN OR SPI
14285-067

FILTER/GPIO4 MODE3/GPIO3 CS SCLK SDO SDI

TO
MODE0/GPIO0

Figure 57. Top Level Core Signal Chain and Control

Rev. A | Page 39 of 75
AD7761 Data Sheet
ANALOG INPUTS 0
PRECHARGE BUFFERED AINx+
PRECHARGE BUFFERED AINx–
Figure 58 shows the AD7761 analog front end. The electrostatic –5
discharge (ESD) protection diodes that are designed to protect
the ADC from some short duration overvoltage and ESD events –10
are shown on the signal path. The analog input is sampled at

AIN (µA)
twice the modulator sampling frequency, fMOD, which is derived –15
from MCLK. By default, the ADC internal sampling capacitors,
CS1 and CS2, are driven by a per channel analog input precharge –20
buffer to ease the driving requirement of the external network.
BPS 0+ –25
AVDD1
PHI 0
AIN0+ CS1 –30

14285-070
PHI 1 0 1 2 3 4
INPUT VOLTAGE (VDIFF)
AVSS

BPS 0– PHI 1 Figure 60. Analog Input Current (AIN) vs. Input Voltage, Analog Input
AVDD1
Precharge Buffer On, VCM = 2.5 V, fMOD = 8.192 MHz
CS2
PHI 0
AIN0–
The analog input precharge buffers can be turned on/off by
means of a register write to Register 0x11 and Register 0x12
14285-068

AVSS (Precharge Buffer Register 1 and Precharge Buffer Register 2,

Figure 58. Analog Front End respectively). When writing to these registers, the user must
The analog input precharge buffers, if enabled, are enabled for a set write the inverse of the required bit settings. For example, to
period of time for each fMOD cycle. The period of time is dependent clear Bit 1 of this register, the user must write 0x01 to the
on the power mode of the AD7761. The precharge buffer is on for register. This clears Bit 1 and sets all other bits. If the user reads
approximately 15 ns in fast mode, 29 ns in median mode, and the register again after writing 0x01, the data read is 0xFE, as
116 ns in low power mode. For the initial rough charging of the required.
switched capacitor network, the bypass switches, BPS 0+ and Each analog input precharge buffer is selectable per channel. In
BPS 0−, remain open during this first phase. For the remaining pin control mode, the analog input precharge buffers are always
phase, the bypass switches are closed, and the fine accuracy enabled for optimum performance.
settling charge is provided by the external source. PHI 0 and PHI 1
When the analog input precharge buffers are disabled, the
represent the modulator clock sampling phases that switch the
analog input current is sourced completely from the analog
input signals onto the sampling capacitors, CS1 and CS2.
input source. The unbuffered analog input current is calculated
The analog input precharge buffers reduce the switching kickback from two components: the differential input voltage on the
from the sampling stage to the external circuitry. The precharge analog input pair, and the analog input voltage with respect to
buffer reduces the average input current by a factor of eight, and AVSS. With the precharge buffers disabled, for 32.768 MHz
makes the input current more signal independent, to reduce the MCLK in fast mode with fMOD = MCLK/4, the differential input
effects of sampling distortion. This reduction in drive requirements current is approximately 48 µA/V and the current with respect
allows pairing of the AD7761 with lower power, lower bandwidth to ground is approximately 17 µA/V.
front-end driver amplifiers such as the ADA4940-1/ADA4940-2.
For example, if the precharge buffers are off, with AIN1+ = 5 V,
400
and AIN1− = 0 V, estimate the current in each input pin as
300 follows:
200 AIN1+ = 5 V × 48 µA/V + 5 V × 17 µA/V = 325 µA

100
AIN1− = −5 V × 48 µA/V + 0 V × 17 µA/V = −240 µA
When the precharge buffers are enabled, the absolute voltage with
AIN (µA)

0
respect to AVSS determines the majority of the current. The
–100 maximum input current of approximately −25 µA is measured
–200
when the analog input is close to either the AVDD1 or AVSS rails.
With either precharge buffers enabled or disabled, the analog
–300
UNBUFFERED AINx+ input current scales linearly with the modulator clock rate. The
UNBUFFERED AINx–
–400 analog input current vs. input voltage is shown in Figure 59.
14285-069

0 1 2 3 4 5 6
INPUT VOLTAGE (VDIFF)

Figure 59. Analog Input Current (AIN) vs. Input Voltage, Analog Input
Precharge Buffer Off, VCM = 2.5 V, fMOD = 8.192 MHz

Rev. A | Page 40 of 75
Data Sheet AD7761
Full settling of the analog inputs to the ADC requires the use of an VCM
external amplifier. Pair amplifiers such as the ADA4805-2 for low AD7761
power mode, or the ADA4805-2 or ADA4940-1/ADA4940-2 for
ADA4805-2
median and fast modes, with the AD7761 (see Table 24 for details +INx
RIN AINx+
on some of these pairings). Running the AD7761 in median and
C1
low power modes or reducing the MCLK rate reduces the load C3
24-BIT
Σ-Δ
and speed requirements of the amplifier; therefore, lower power –INx
RIN
C2
AINx–
ADC

amplifiers can be paired with the analog inputs to achieve the

14285-161
PRECHARGE
optimum signal chain efficiency. BUFFERS

There is a resistor/capacitor (RC) network between the Figure 61. Typical Input Structure for an RC Network
amplifier output and the ADC input. Figure 61 shows a typical
RC network used for the AD7761 for most amplifier pairings. VCM
The RC network performs a variety of tasks. C1 and C2 are The AD7761 provides a buffered common-mode voltage output
charge reservoirs to the ADC, providing the ADC with fast on Pin 59. This output can bias up analog input signals. By
charge current to the sampling capacitors. incorporating the VCM buffer into the ADC, the AD7761
Capacitor C3 removes common-mode errors between the reduces component count and board space. In pin control
AINx+ and AINx− inputs. These capacitors, in combination mode, the VCM potential is fixed to (AVDD1 − AVSS)/2, and
with RIN, form a low-pass filter to filter out glitches related to is enabled by default.
the input switching. The input resistance also stabilizes the In SPI control mode, configure the VCM potential using the
amplifier when driving large capacitor loads and prevents the general configuration register (Register 0x05). The output can
amplifier from oscillating. be enabled or disabled, and set to (AVDD1 − AVSS)/2, 1.65 V,
The optimum driver amplifiers for each of these requirements 2.14 V, or 2.5 V, with respect to AVSS.
of power, performance, and supply are as follows: The VCM voltage output is associated with the Channel 0
• The ADA4805-2 is suited for low power, particularly in low circuitry. If Channel 0 is put into standby mode, the VCM
power mode. voltage output is also disabled for maximum power savings.
Channel 0 must be enabled while VCM is being used externally
• The ADA4940-1 is suited for single-supply operation,
to the AD7761.
which is also the recommended fully differential amplifier
to drive the AD7761.
For more details, see the AN-1384.

Table 24. Amplifier Pairing Options

Amplifier Power Analog Input Precharge Total Power (Amplifier + AD7761)
Power Mode Amplifier (mW/channel)1 Buffer (mW/channel)1
Fast ADA4940-2 13.4 On 64.9
Median ADA4805-2 6.9 On 34.4
Low Power ADA4805-2 6.5 On 15.9
1
Typical power at 25°C.

Rev. A | Page 41 of 75
AD7761 Data Sheet
REFERENCE INPUT Three clock source input options are available to the AD7761:
The AD7761 has two differential reference input pairs. REF1+ external CMOS, crystal oscillator, or LVDS. The clock is selected on
and REF1− are the reference inputs for Channel 0 to Channel 3, power-up and is determined by the state of the CLK_SEL pin.
and REF2+ and REF2− are for Channel 4 to Channel 7. The If CLK_SEL = 0, the CMOS clock option is selected and the
absolute input reference voltage range is 1 V to AVDD1 − AVSS. clock is applied to Pin 32 (Pin 31 is tied to DGND).
Like the analog inputs, the reference inputs have a precharge buffer If CLK_SEL = 1, the crystal or LVDS option is selected and the
option. Each ADC has an individual buffer for each REFx+ and crystal or LVDS is applied to Pin 31 and Pin 32. The LVDS
REFx−. The precharge buffers help reduce the burden on the option is available only in SPI control mode. An SPI write to
external reference circuitry. Bit 3 of Register 0x04 enables the LVDS clock option.
In pin control mode, the reference precharge buffers are off by DIGITAL FILTERING
default. In SPI control mode, the user can enable or disable the The AD7761 offers two types of digital filters. In SPI control
reference precharge buffers. In the case of unipolar analog supplies, mode, these filters can be chosen on a per channel basis. In pin
in SPI control mode, the user can achieve the best performance and control mode, only one filter can be selected for all channels. The
power efficiency by enabling only the REFx+ buffers. The reference digital filters available on the AD7761 are
input current scales linearly with the modulator clock rate.
• Sinc5 low latency filter, −3 dB at 0.204 × ODR
For 32 MHz MCLK and MCLK/4 fast mode, the differential
• Wideband low ripple filter, −3 dB at 0.433 × ODR
input current is ~72 µA/V per channel, unbuffered, and
~16 µA/V per channel with the precharge buffers enabled. Both filters can be operated in one of six different decimation rates,
With the precharge buffers off, REFx+ = 5 V, and REFx− = 0 V, allowing the user to choose the optimal input bandwidth and speed
of the conversion vs. the desired power mode or resolution.
REFx± = 5 V × 72 µA/V = 360 µA
Sinc5 Filter
With the precharge buffers on, REFx+ = 5 V, and REFx− = 0 V,
Most precision Σ-Δ ADCs use a sinc filter. The sinc5 filter offered
REFx± = 5 V × 16 µA/V = 80 µA in the AD7761 enables a low latency signal path useful for dc
For the best performance and headroom, it is recommended to inputs, for control loops, or where other specific postprocessing
use a 4.096 V reference such as the ADR444 or the ADR4540. is required. The sinc5 filter path offers the lowest noise and power
consumption. The sinc5 filter has a −3 dB BW of 0.204 × ODR.
For the best performance at high sampling rates, it is recommended
Table 11 contains the noise performance for the sinc5 filter across
to use an external reference drive amplifier such as the ADA4841-1
power modes and decimation ratios.
or the AD8031. Figure 62 shows a configuration diagram of the
0
reference connection.
VIN –20

REFx+ –40
VIN VOUT

ADA4841-1 –60
ADR4540 AD7761
AMPLITUDE (dB)

–80
14285-162

REFx–
–100

Figure 62. Typical Reference Input Configuration Diagram –120

CLOCK SELECTION –140

The AD7761 has an internal oscillator used for initial power-up –160

of the device. After the AD7761 completes the start-up routine, –180

the device normally transfer control of the internal clocking to –200

14285-071

0 2 4 6 8 10 12 14 16
the externally applied MCLK. The AD7761 counts the falling
NORMALIZED INPUT FREQUENCY (fIN/fODR)
edges of the external MCLK over a given number of internal clock
cycles to determine if the clock is valid and at least a frequency of Figure 63. Sinc5 Filter Frequency Response (Decimation = ×32)
1.15 MHz. If there is a fault with the external MCLK, the transfer of The settling times for the AD7761 when using the sinc5 filter are
control does not occur, the AD7761 outputs an error in the shown in Table 26.
status header, and the clock error bit is set in the device status
register. No conversion data is output and a reset is required to
exit this error state.

Rev. A | Page 42 of 75
Data Sheet AD7761
Wideband Low Ripple Filter 0
–10
The wideband filter, referred to as a brick wall filter, has a low ripple –20
pass band, within ±0.005 dB of ripple, of 0.4 × ODR. The wideband –30
filter has full attenuation at 0.499 × ODR (Nyquist), maximizing –40

AMPLITUDE (dB)
antialias protection. The wideband filter has a pass-band ripple of –50
–60
±0.005 dB and a stop band attenuation of 105 dB from Nyquist
–70
out to fCHOP. For more information on antialiasing and fCHOP –80
aliasing, see the Antialiasing section. –90

The wideband filter is a very high order digital filter with a group –100
–110
delay of approximately 34/ODR. After a synchronization pulse,
–120
there is an additional delay from the SYNC_IN rising edge to –130
fully settled data. The settling times for the AD7761 when using –140

14285-072
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
the wideband filter are shown in Table 25. See Table 10 for the
NORMALIZED INPUT FREQUENCY (fIN/fODR)
noise performance of the wideband filter across power modes
and decimation rates. Figure 64. Wideband Filter Frequency Response
0.010
Filter Settling Time
0.008
The AD7761 digital filters are resynchronized on the rising edge
0.006
of the SYNC_IN signal. This resynchronization should be
provided after power-up in pin control mode or SPI control 0.004

AMPLITUDE (dB)
mode, and after any reconfiguration of the device in SPI control 0.002
mode, prior to capturing ADC samples. Once the SYNC_IN 0
rising edge is provided, there is a deterministic delay until the
–0.002
first new conversion result is available, and until the first settled
–0.004
data is available.
–0.006
Table 25 and Table 26 provide these delays, measured in MCLK
cycles, for wideband and sinc5 filters, respectively, for each –0.008

possible setting of MCLK_DIV. Each table provides the delays –0.010

14285-073
0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
for configurations in which all channels are using the exact NORMALIZED INPUT FREQUENCY (fIN/fODR)
same configuration (Group B unused), and for configurations
Figure 65. Wideband Filter Pass-Band Ripple
in which one or more channels have a different decimation rate
1.2
applied (Group B is used).
For example, if a user configures channels with the wideband 1.0

filter and MCLK_DIV = MCLK/4, and assigns some channels

0.8
to Group A with decimate x32 and others to Group B with
AMPLITUDE (dB)

decimate x64, then the delay until the first DRDY after the 0.6
SYNC_IN is 758 MCLK periods. All active channels then output
the first data after 758 MCLK periods. However, due to differing 0.4

decimation rates across channels, in this case the first settled

0.2
data becomes available for the Group A channels 8,822 MCLK
periods after SYNC_IN, and after 17,014 MCLK periods for 0
Group B channels.
–0.2
14285-074

0 10 20 30 40 50 60 70 80
OUTPUT DATA RATE SAMPLES

Figure 66. Wideband Filter Step Response

Rev. A | Page 43 of 75
AD7761 Data Sheet
Table 25. Wideband Filter SYNC_IN to Settled Data
Delay from First MCLK Delay from First MCLK Rise After SYNC_IN
Rise After SYNC_IN Rise to Rise to Earliest Settled Data, DRDY Rise
MCLK_DIV Filter Type Decimation Factor First DRDY Rise Group A Group B
Setting Group A Group B Group A Group B MCLK Periods MCLK Periods MCLK Periods
MCLK/4 Wideband Wideband 32 Unused 336 8400 Not applicable
Wideband Wideband 64 Unused 620 16,748 Not applicable
Wideband Wideband 128 Unused 1187 33,443 Not applicable
Wideband Wideband 256 Unused 2325 66,837 Not applicable
Wideband Wideband 512 Unused 4601 133,625 Not applicable
Wideband Wideband 1024 Unused 9153 267,201 Not applicable
Wideband Wideband 32 32 758 8822 8822
Wideband Wideband 32 64 758 8822 17,014
Wideband Wideband 32 128 758 8822 33,526
Wideband Wideband 32 256 758 8822 66,934
Wideband Wideband 32 512 758 8822 133,622
Wideband Wideband 32 1024 758 8822 267,253
Wideband Wideband 64 32 759 17,015 8823
Wideband Wideband 128 32 760 33,528 8824
Wideband Wideband 256 32 762 66,938 8826
Wideband Wideband 512 32 782 133,646 8846
Wideband Wideband 1024 32 806 267,302 8870
MCLK/8 Wideband Wideband 32 Unused 656 16,784 Not applicable
Wideband Wideband 64 Unused 1225 33,481 Not applicable
Wideband Wideband 128 Unused 2359 66,871 Not applicable
Wideband Wideband 256 Unused 4635 133,659 Not applicable
Wideband Wideband 512 Unused 9187 267,235 Not applicable
Wideband Wideband 1024 Unused 18,291 534,387 Not applicable
Wideband Wideband 32 32 820 16,948 16,948
Wideband Wideband 32 64 820 16,948 33,588
Wideband Wideband 32 128 820 16,948 66,868
Wideband Wideband 32 256 820 16,948 133,684
Wideband Wideband 32 512 820 16,948 267,316
Wideband Wideband 32 1024 820 16,948 534,580
Wideband Wideband 64 32 822 33,590 16,950
Wideband Wideband 128 32 824 66,872 16,952
Wideband Wideband 256 32 844 133,708 16,972
Wideband Wideband 512 32 836 267,332 16,964
Wideband Wideband 1024 32 852 534,612 16,980
MCLK/32 Wideband Wideband 32 Unused 2587 67,099 Not applicable
Wideband Wideband 64 Unused 4855 133,879 Not applicable
Wideband Wideband 128 Unused 9391 267,439 Not applicable
Wideband Wideband 256 Unused 18,495 534,591 Not applicable
Wideband Wideband 512 Unused 36,703 1,068,895 Not applicable
Wideband Wideband 1024 Unused 73,119 2,137,503 Not applicable
Wideband Wideband 32 32 2587 67,099 67,099
Wideband Wideband 32 64 2587 67,099 134,683
Wideband Wideband 32 128 2587 67,099 267,803
Wideband Wideband 32 256 2587 67,099 535,067
Wideband Wideband 32 512 2587 67,099 1,069,595
Wideband Wideband 32 1024 2587 67,099 2,137,627
Wideband Wideband 64 32 2587 134,683 67,099
Wideband Wideband 128 32 2587 267,803 67,099
Wideband Wideband 256 32 2587 535,067 67,099
Wideband Wideband 512 32 2587 1,069,595 67,099
Wideband Wideband 1024 32 2587 2,137,627 67,099

Rev. A | Page 44 of 75
Data Sheet AD7761
Table 26. Sinc5 Filter SYNC_IN to Settled Data
Delay from First MCLK Delay from First MCLK Rise After SYNC_IN
Rise After SYNC_IN Rise Rise to Earliest Settled Data, DRDY Rise
Power Filter Type Decimation Factor to First DRDY Rise Group A Group B
Mode Group A Group B Group A Group B MCLK Periods MCLK Periods MCLK Periods
MCLK/4 Sinc5 Sinc5 32 Unused 199 839 Not applicable
Sinc5 Sinc5 64 Unused 327 1607 Not applicable
Sinc5 Sinc5 128 Unused 583 3143 Not applicable
Sinc5 Sinc5 256 Unused 1095 6215 Not applicable
Sinc5 Sinc5 512 Unused 2119 12359 Not applicable
Sinc5 Sinc5 1024 Unused 4167 24,647 Not applicable
Sinc5 Sinc5 32 32 199 839 839
Sinc5 Sinc5 32 64 199 839 1607
Sinc5 Sinc5 32 128 199 839 3143
Sinc5 Sinc5 32 256 199 839 6215
Sinc5 Sinc5 32 512 199 839 12,359
Sinc5 Sinc5 32 1024 199 839 24,647
Sinc5 Sinc5 64 32 199 1607 839
Sinc5 Sinc5 1024 32 199 24,647 839
MCLK/8 Sinc5 Sinc5 32 Unused 383 1663 Not applicable
Sinc5 Sinc5 64 Unused 639 3199 Not applicable
Sinc5 Sinc5 128 Unused 1151 6271 Not applicable
Sinc5 Sinc5 256 Unused 2175 12,415 Not applicable
Sinc5 Sinc5 512 Unused 4223 24,703 Not applicable
Sinc5 Sinc5 1024 Unused 8319 49,279 Not applicable
Sinc5 Sinc5 32 32 383 1663 1663
Sinc5 Sinc5 32 64 383 1663 3199
Sinc5 Sinc5 32 128 383 1663 6271
Sinc5 Sinc5 32 256 398 1663 12,415
Sinc5 Sinc5 32 512 398 1663 24,703
Sinc5 Sinc5 32 1024 398 1663 49,279
Sinc5 Sinc5 64 32 383 3199 1663
Sinc5 Sinc5 1024 32 398 49,279 1663
MCLK/32 Sinc5 Sinc5 32 Unused 1487 6607 Not applicable
Sinc5 Sinc5 64 Unused 2511 12,751 Not applicable
Sinc5 Sinc5 128 Unused 4559 25,039 Not applicable
Sinc5 Sinc5 256 Unused 8655 49,615 Not applicable
Sinc5 Sinc5 512 Unused 16,847 98,767 Not applicable
Sinc5 Sinc5 1024 Unused 33,231 197,071 Not applicable
Sinc5 Sinc5 32 32 1487 6607 6607
Sinc5 Sinc5 32 64 1487 6607 12,751
Sinc5 Sinc5 32 128 1487 6607 25,039
Sinc5 Sinc5 32 256 1487 6607 49,615
Sinc5 Sinc5 32 512 1487 6607 98,767
Sinc5 Sinc5 32 1024 1487 6607 197,071
Sinc5 Sinc5 64 32 1487 12,751 6607
Sinc5 Sinc5 1024 32 1487 197,071 6607

Rev. A | Page 45 of 75
AD7761 Data Sheet
DECIMATION RATE CONTROL The modulator has no rejection to signals that are at frequencies in
The AD7761 has programmable decimation rates for the digital zones around 2 × fMOD and all even multiples of fMOD. Signals at
filters. The decimation rates allow the user to reduce the measure- these frequencies are aliased by the AD7761. For the AD7761,
ment bandwidth, reducing the speed but increasing the resolution. the first of these zones that requires protection is at 2 × fMOD.
When using the SPI control, control the decimation rate on the Because typical switch capacitor, discrete time Σ-Δ modulators
AD7761 through the channel mode registers. These registers set provide no protection to aliasing at the frequency, fMOD, the
two separate channel modes with a given decimation rate and AD7761 provides a distinct advantage in this regard.
filter type. Each ADC is mapped to one of these modes via the Figure 67 shows the frequency response of the modulator and
channel mode select register. Table 27 details both the decimation wideband digital filter to out of band tones at the analog input.
rates available, and the filter types for selection, within Channel Figure 67 shows the magnitude of an alias that is seen in band
Mode A and Channel Mode B. vs. the frequency of the signal sampled at the analog input. The
In pin control mode, the decimation ratio is controlled by the relationship between the input signal and the modulator frequency
DEC0 and DEC1 pins; see Table 15 for the decimation is expressed in a normalized manner as a ratio of the input signal
configuration in pin control mode. frequency (fIN) to the modulator frequency (fMOD). This data
demonstrates the ADC frequency response relative to out of band
Table 27. Channel Mode x Registers, Register 0x01 and tones when using the wideband filter. The fIN is swept from dc to
Register 0x02 20 MHz. In fast mode, using an 8.192 MHz fMOD frequency, the
Bits Name Logic Value Decimation Rate x-axis spans ratios of fIN/fMOD from 0 to 2.44 (equivalent to fIN of
3 FILTER_TYPE_x 0 Wideband filter 0 Hz to 20 MHz). A similar characteristic occurs in median and
1 Sinc5 filter low power modes.
[2:0] DEC_RATE_x 000 32 The notch appears in Figure 67 with fIN at fMOD (designated at
001 64 fIN/fMOD = 1.00 on the x-axis). An input at this frequency is
010 128 attenuated by 35 dB, which adds to the attenuation of any external
011 256 antialiasing filter, thus reducing the frequency roll-off require-
100 512 ment of the external filter. If the plot is swept further in frequency,
101 1024 the notch is seen to recur at fIN/fMOD = 3.00.
110 1024
The point where fIN = 2 × fMOD (designated on the x-axis at 2.00)
111 1024
offers 0 dB attenuation, indicating that all signals falling at this
ANTIALIASING frequency alias directly back into the ADC conversion results, in
Because the AD7761 is a switched capacitor, discrete time ADC, accordance with the sampling theory.
the user may want to employ external analog antialiasing filters to The AD7761 wideband digital filter also offers an added
protect against foldback of out of band tones. protection against aliasing. Because the wideband filter has full
Within this section, an out of band tone refers to an input fre- attenuation at the Nyquist frequency (fODR/2, where fODR = fMOD/
quency greater than the pass band frequency specification of Decimation Rate), input frequencies, and in particular harmonics
the digital filter that is applied at the analog input. of input frequencies, that may fall close to fODR/2, do not fold back
into the pass band of the AD7761.
When designing an antialiasing filter for the AD7761, three main
0
aliasing regions must be taken into account. After the alias –10 fCHOP = fMOD/32
WITH RESPECT TO IN-BAND MAGNITUDE

requirements of each zone are understood, the user can design –20 fCHOP = fMOD/8
an antialiasing filter to meet the needs of the specific application. –30
The three zones for consideration are related to the modulator
ALIAS MAGNITUDE (dB)

–40

sampling frequency, the modulator chopping frequency, and the –50

–60
modulator saturation point.
–70
Modulator Sampling Frequency –80
–90
The AD7761 modulator signal transfer function includes a notch,
–100
at odd multiples of fMOD, to reject tones or harmonics related to –110
the modulator clock. The modulator itself attenuates signals at –120
frequencies of fMOD, 3 × fMOD, 5 × fMOD, and so on. For an MCLK –130

frequency of 32.768 MHz, the attenuation is approximately –140

0
0.125
0.250
0.375
0.500
0.625
0.750
0.875
1.000
1.125
1.250
1.375
1.500
1.625
1.750
1.875
2.000
2.125
2.250
2.375
2.500

35 dB in fast mode, 41 dB in median mode, and 53 dB in low

14285-075

power mode. Attenuation is increased by 6 dB across each power fIN/fMOD

mode, with every halving of the MCLK frequency, for example, Figure 67. Rejection of Out of Band Input Tones, Wideband Filter,
when reducing the clock from 32.768 MHz to 16.384 MHz. Decimation = ×32, fMOD = 8.192 MHz, Analog Input Sweep from DC to 20 MHz

Rev. A | Page 46 of 75
Data Sheet AD7761
Modulator Chopping Frequency Modulator Saturation Point
Figure 67 plots two scenarios that relate to the chopping frequency A Σ-Δ modulator can be considered a standard control loop,
of the AD7761 modulator. employing negative feedback. The control loop works to ensure
The AD7761 uses a chopping technique in the modulator similar that the average processed error signal is very small over time. It
to that of a chopped amplifier to remove offset, offset drift, and uses an integrator to remember preceding errors and force the
1/f noise. The AD7761 default chopping rate is fMOD/32. In pin mean error to be zero. As the input signal rate of change increases
control mode, the chop frequency is hardwired to fMOD/32. In with respect to the modulator clock, fMOD, a larger voltage feedback
SPI control mode, the user can select the chop frequency to be error is processed. Above a certain frequency, the error begins
either fMOD/32 or fMOD/8. to saturate the modulator.

As shown in Figure 67, the stop band rejection of the digital For the AD7761, the modulator may saturate for full-scale input
filter is reduced at frequencies that relate to even multiples of frequencies greater than fMOD/16 (as shown in Figure 68),
the chopping frequency (fCHOP). All other out of band frequencies depending on the rate of change of input signal, input signal
(excluding those already discussed relating to the modulator amplitude, and reference input level. A half power input tone at
clock frequency, fMOD) are rejected by the stop band attenuation fMOD/8 can also cause the modulator to saturate. In applications
of the digital filter. An out of band tone with a frequency in the where there may be high amplitude and frequency out of band
range of (2 × fCHOP ) ± f3dB, where f3dB is the filter bandwidth tones, a first-order antialiasing filter is required with a −3 dB
employed, is attenuated to the envelope determined by the chop corner frequency set at fMOD/16 to protect against modulator
frequency setting (see Figure 67), and aliased into the pass saturation. For example, if operating the AD7761 at full speed
band. Out of band tones near additional even multiples of fCHOP and using a decimation rate of ×32 to achieve an output data
(that is, N × fCHOP, where N is an even integer), are attenuated rate of 256 kSPS, the modulator rate is equal to 8.192 MHz. In
and aliased in the same way. this instance, to protect against saturation, set the antialiasing
filter −3 dB corner frequency to 512 kHz.
Chopping at fMOD/32 offers the best performance for noise, 3
offset, and offset drift for the AD7761.
0
For ac performance it may be useful to select chopping at fMOD/8 –3
as this moves the first chopping tone to a higher frequency.
ALLOWED INPUT (dB)

–6
However, chopping at fMOD/8 may lead to slightly degraded
noise (approximately 1 dB loss in dynamic range) and offset –9

performance compared to the default chop rate of fMOD/32. –12

Table 28 shows the aliasing achieved by different order anti- –15

aliasing filter options at the critical frequencies of fMOD/32 and –18

fMOD/8 for chop aliasing, fMOD/16 for modulator saturation, and –21
2 × fMOD for the first zone with 0 dB attenuation. It assumes the –24 MAX SIGNAL
corner frequency of the antialiasing filter is at fMOD/64, which is –27
FIRST ORDER (fMOD/64)

14285-168
just above the maximum input bandwidth that the AD7761 0.0004 0.004 0.04 0.4
fIN/fMOD
digital filter can pass when using a decimate by 32 filter setting.
Figure 68. Maximum Input Signal vs. Frequency
Table 28. External Antialiasing Filter Attenuation
fMOD/32 fMOD/16 fMOD/8 2 × fMOD
RC Filter (dB) (dB) (dB) (dB)
First Order −6 −12 −18 −42
Second Order −12 −24 −36 −84
Third Order −18 −36 −54 −126

Rev. A | Page 47 of 75
AD7761 Data Sheet
CALIBRATION the ADC input channels, relative to one another. The range of
In SPI control mode, the AD7761 offers users the ability to adjust phase compensation is limited to a maximum of one conversion
offset, gain, and phase delay on a per channel basis. cycle, and the resolution of the correction depends on the
decimation rate in use.
Offset Adjustment
Table 29 displays the resolution and register bits used for phase
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_ offset for each decimation ratio.
OFFSET_LSB registers are 24-bit, signed twos complement
registers for channel offset adjustment. If the channel gain setting is Table 29. Phase Delay Resolution
at its ideal nominal value of 0x555555, an LSB of offset register Decimation Sync Phase Offset
adjustment changes the digital output by −1/192 LSBs. For Ratio Resolution Steps Register Bits
example, changing the offset register from 0 to 4800 changes the ×32 1/fMOD 32 [7:3]
digital output by −25 LSBs. Because offset calibration occurs ×64 1/fMOD 64 [7:2]
before gain calibration, the ratio of −1/192 changes linearly with ×128 1/fMOD 128 [7:1]
gain adjustment via the Channel x gain registers (see Table 53). ×256 1/fMOD 256 [7:0]
After a reset or power cycle, the offset register values revert to the ×512 2/fMOD 256 [7:0]
default factory setting. ×1024 4/fMOD 256 [7:0]
Gain Adjustment Adjusting the sync phase of channels can affect the time to the
Each ADC channel has an associated gain coefficient. The first DRDY pulse after the sync pulse, as well as the time to Bit 6
coefficient is stored in three single-byte registers split up as of the header status (filter not settled data bit) being cleared,
MSB, MID, and LSB. Each of the gain registers are factory that is, the time to settled data.
programmed. Nominally, this gain is around the value 0x555555 If all channels are using the sinc5 filter, the time to the
(for an ADC channel). The user can overwrite the gain register first DRDY pulse is not affected by the adjustment of the sync
setting. However, after a reset or power cycle, the gain register phase offset, assuming that at least one channel has zero sync
values revert to the hard coded programmed factory setting. phase offset adjustment. If all channels have a nonzero sync phase
Calculate the approximate result that is output using the offset setting, the time to the first DRDY pulse is delayed
following formula: according to the channel that has the least offset applied.
Channels with a sync offset adjustment setting that delays the
 3 × VIN  Gain 4,194,300
Data =  × 2 21 − (Offset )  × × internal sync signal, relative to other channels, may not output
 VREF  1024 2 42
settled data until after the next DRDY pulse. In other words,
where: there may be a delay of one ODR period between the settled
Offset is the offset register setting. data being output by the AD7761 for the channels with added
Gain is the gain register setting. phase delay.
Sync Phase Offset Adjustment If all channels are using the wideband filter, the time to the
The AD7761 has one synchronization signal for all channels. first DRDY pulse and the time to settled data is delayed
The sync phase offset register allows the user to vary the phase according to the channel with the maximum phase delay
delay on each channel relative to the synchronization edge setting. In this case, the interface waits for the latest channel and
received on the SYNC_IN pin. outputs data for all channels when that channel is ready.
By default, all ADC channels react simultaneously to
the SYNC_IN pulse. The sync phase registers can be
programmed to equalize known external phase differences on

Rev. A | Page 48 of 75
Data Sheet AD7761

DATA INTERFACE
SETTING THE FORMAT OF DATA OUTPUT Higher DCLK rates make it easier to receive the conversion data
The data interface format is determined by setting the from the AD7761 with a lower number of DOUTx lines;
FORMATx pins. The logic state of the FORMATx pins is read however, there is a trade-off against ADC offset performance
on power-up and determines how many data lines (DOUTx) the with higher DCLK frequencies. For the best offset and offset
ADC conversions are output on. drift performance, use the lowest DCLK frequency possible.
The user can choose to reduce the DCLK frequency by an
Because the FORMATx pins are read on power-up of the appropriate selection of MCLK frequency, DCLK divider,
AD7761 and the device remains in this output configuration, and/or the number of DOUTx lines used.
this function must always be hardwired and cannot be altered
dynamically. Table 30, Figure 69, Figure 70, and Figure 71 show Table 30. FORMATx Truth Table
the formatting configuration for the digital output pins on the FORMAT1 FORMAT0 Description
AD7761. 0 0 Each ADC channel outputs on its own
dedicated pin. DOUT0 to DOUT7 are
Calculate the minimum required DCLK rate for a given data
in use.
interface configuration as follows:
0 1 The ADCs share the DOUT0 and
DCLK (minimum) = Output Data Rate × Channels per DOUT1 pins: Channel 0 to Channel 3
DOUTx × 24 output on DOUT0. Channel 4 to
Channel 7 output on DOUT1. The ADC
where MCLK ≥ DCLK. channels share data pins in time
For example, if MCLK = 32.768 MHz, with two DOUTx lines, division multiplexed (TDM) output.
DOUT0 and DOUT1 are in use.
DCLK (minimum) = 256 kSPS × 4 channels per DOUTx × 1 X All channels output on the DOUT0 pin,
24 = 24.576 MHz in TDM output. Only DOUT0 is in use.
Therefore, DCLK = MCLK/1 is required.
Alternatively, if MCLK = 32.768 MHz, with eight DOUTx lines,
DCLK (minimum) = 256 kSPS × 1 channel per DOUTx ×
24 = 6.144 MHz
Therefore, DCLK = MCLK/4 (DCLK = 8.192 MHz) is
sufficient.
AD7761 DRDY
DCLK

DOUT0 CH 0

DOUT1 CH 1
EACH ADC HAS A 0 FORMAT0
DEDICATED DOUTx PIN 0 FORMAT1

DOUT7 CH 7
DGND
14285-076

DAISY-CHAINING IS
NOT POSSIBLE IN THIS FORMAT

Figure 69. FORMATx = 00, Eight Data Output Pins

AD7761

DRDY

IOVDD DCLK
CHANNEL 0 TO CHANNEL 3
OUTPUT ON DOUT0 1 DOUT0
FORMAT0
CHANNEL 4 TO CHANNEL 7 0 FORMAT1 DOUT1
OUTPUT ON DOUT1
DGND
14285-077

DAISY-CHAINING IS
POSSIBLE IN THIS FORMAT

Figure 70. FORMATx = 01, Two Data Output Pins

Rev. A | Page 49 of 75
AD7761 Data Sheet
AD7761

DRDY
IOVDD
CHANNEL0 TO CHANNEL7
DCLK
OUTPUT ON DOUT0 1 FORMAT0
1 FORMAT1 DOUT0

14285-078
DAISY-CHAINING IS
POSSIBLE IN THIS FORMAT

Figure 71. FORMATx = 10 or 11, One Data Output Pin

ADC CONVERSION OUTPUT: HEADER AND DATA wideband and sinc5 filters are shown in Table 25 and Table 26,
The AD7761 data is output on the DOUT0 to DOUT7 pins, respectively. This bit is set if this settling delay has not yet elapsed.
depending on the FORMATx pins. The actual structure of the Repeated Data
data output for each ADC result is shown in Figure 72. Each If different channels use different decimation rates, data outputs
ADC result comprises 24 bits. The first eight bits are the header are repeated for the slower speed channels. In these cases, the
status bits, which contain status information and the channel header is output as normal with the repeated data bit set to 1,
number. The names of each of the header status bits are shown and the following repeated ADC result is output as all zeros.
in Table 31, and their functions are explained in the subsequent This bit indicates that the conversion result of all zeros is not
sections. This header is followed by a 16-bit ADC output in real; it indicates that there is a repeated data condition because
twos complement coding, MSB first. two different decimation rates are selected. This condition can
Transitions on the DRDY and the DOUTx pins are aligned with only occur during SPI control of the AD7761.
the rising edge of DCLK. See Figure 2 and Table 2 for details. Filter Type
In pin control mode, all channels operate using one filter
DRDY
selection. The filter selected in pin control mode is determined
by the logic level of the FILTER pin. In SPI control mode, the
DOUTx N–1 HEADER N ADC DATA N digital filters can be selected on a per channel basis, using the
14285-079

8 BITS 16 BITS mode registers. This header bit is 0 for channels using the
Figure 72. ADC Output: 8-Bit Header, 16-Bit ADC Conversion Data
wideband filter, and 1 for channels using the sinc5 filter.
Filter Saturated
Table 31. Header Status Bits
Bit Bit Name
The filter saturated bit indicates that the filter output is clipping at
7 ERROR_FLAGGED
either positive or negative full scale. The digital filter clips if the
6 Filter not settled signal goes beyond the specification of the filter; it does not wrap.
5 Repeated data The clipping may be caused by the analog input exceeding the
4 Filter type analog input range, or by a step change in the input, which may
3 Filter saturated cause overshoot in the digital filter. Clipping may also occur
[2:0] Channel ID[2:0] when the combination of the analog input signal and the channel
gain register setting causes the signal seen by the filter to be
ERROR_FLAGGED higher than the analog input range.
The ERROR_FLAGGED bit indicates when a serious error Channel ID
occurs. If this bit is set, a reset is required to clear this bit. This bit
The channel ID bits indicate the ADC channel from which the
indicates that the external clock is not detected, a memory map
succeeding conversion data originates (see Table 32).
bit unexpectedly changes state, or an internal CRC error is
detected. Table 32. Channel ID vs. Channel Number
When an external clock is not detected, the conversion results are Channel Channel ID 2 Channel ID 1 Channel ID 0
output as all zeros regardless of the analog input voltages Channel 0 0 0 0
applied to the ADC channels. Channel 1 0 0 1
Channel 2 0 1 0
Filter Not Settled
Channel 3 0 1 1
After power-up, reset, or synchronization, the AD7761 clears the Channel 4 1 0 0
digital filters and begins conversion. Due to the weighting of the Channel 5 1 0 1
digital filters, there is a delay from the first conversion to fully Channel 6 1 1 0
settled data. The settling times for the AD7761 when using the Channel 7 1 1 1
Rev. A | Page 50 of 75
Data Sheet AD7761
Data Interface: Standard Conversion Operation Figure 73, Figure 74, and Figure 75 are distinct examples of the
In standard mode operation, the AD7761 operates as the master impact of the FORMATx pins on the AD7761 output operating in
and streams data to the DSP or FPGA. The AD7761 supplies the standard conversion operation.
data, the data clock (DCLK), and a falling edge framing signal Figure 73 to Figure 75 represent running the AD7761 at
(DRDY) to the slave device. All of these signals are synchronous. maximum data rate for the three FORMATx options.
The data interface connections to DSP/FPGA are shown in Figure 73 shows FORMATx = 00. Each ADC has its own data out
Figure 76. The FORMATx pins determine how the data is pin running at the MCLK/4 bit rate. In pin control mode, this is
output from the AD7761. achieved by selecting Mode 0xA (fast mode, DCLK = MCLK/4,
Figure 73 through Figure 75 show the data interface operating standard conversion, see Table 18) with the decimation rate set
in standard mode at the maximum data rate. In all as ×32.
instances, DRDY is asserted one clock cycle before the MSB of Figure 74 shows FORMATx = 01 sharing DOUT1 at the
the data conversion is made available on the data pin. maximum bit rate. In pin control mode, this is achieved by
Each DRDY falling edge starts the output of the new ADC con- selecting Mode 0x8 (fast mode, DCLK = MCLK/1, standard
version data. The first eight bits output after the DRDY falling edge conversion) with a decimation rate of ×32.
are the header bits; the last 16 bits are the ADC conversion result. If running in pin control mode, the example shown in Figure 75
represents Mode 0x4 (median mode, DCLK = MCLK/1,
standard conversion) with a decimation rate of ×32, giving the
maximum output data capacity possible on one DOUTx pin.

DCLK

SAMPLE N SAMPLE N + 1

DRDY

DOUT0

DOUT1

14285-080
DOUT7

Figure 73. FORMATx = 00: Each ADC Has a Dedicated Data Output Pin, Maximum Data Rate

DCLK

SAMPLE N SAMPLE N + 1

DRDY

DOUT0 CH0 (N) CH1 (N) CH2 (N) CH3 (N) CH0 (N + 1) CH1 (N + 1) CH2 (N + 1) CH3 (N + 1)

DOUT1 CH4 (N) CH5 (N) CH6 (N) CH7 (N) CH4 (N + 1) CH5 (N + 1) CH6 (N + 1) CH7 (N + 1)

DOUT2
14285-081

DOUT7

Figure 74. FORMATx = 01: Channel 0 to Channel 3 Share DOUT0, and Channel 4 to Channel 7 Share DOUT1, Maximum Data Rate
(DOUT6 and DOUT7 Are Inputs in This Configuration)

Rev. A | Page 51 of 75
AD7761 Data Sheet
DCLK

SAMPLE N SAMPLE N + 1 SAMPLE N + 2

DRDY

DOUT0

DOUT1

14285-082
DOUT7

Figure 75. FORMATx = 11 or 10: Channel 0 to Channel 7 Output on DOUT0 Only, Maximum Data Rate (DOUT6 and DOUT7 Are Inputs in This Configuration)

AD7761 DSP/FPGA

DCLK

DRDY

DOUT0 TO
DOUT7

14285-083
MCLK

Figure 76. Data Interface: Standard Conversion Operation, AD7761 = Master, DSP/FPGA = Slave

SYNC_IN

tSETTLE

SETTLED SETTLED
DOUT0 DATA DATA

SETTLED SETTLED
DOUT1 DATA DATA

SETTLED SETTLED
DOUT7 DATA DATA
14285-084

DRDY
24 DCLKs 24 DCLKs

Figure 77. One-Shot Mode

Rev. A | Page 52 of 75
Data Sheet AD7761
Data Interface: One-Shot Conversion Operation Daisy-Chaining
One-shot mode is available in both SPI and pin control modes. Daisy-chaining devices allows numerous devices to use the
This conversion mode is available by selecting one of Mode 0xC to same data interface lines by cascading the outputs of multiple
Mode 0xF when in pin control mode. In SPI control mode, set ADCs from separate AD7761 devices. Only one ADC device
Bit 4 (one-shot mode) of Register 0x06, the data control register. has its data interface in direct connection with the digital host.
Figure 77 shows the device operating in one-shot mode. For the AD7761, this connection can be implemented by
In one-shot mode, the AD7761 is a pseudoslave. Conversions cascading DOUT0 and DOUT1 through a number of devices, or
occur on request by the master device, for example, the DSP or using only DOUT0; whether two data output pins or only one
FPGA. The SYNC_IN pin initiates the conversion request. In data output pin is enabled depends on the FORMATx pins. The
one-shot mode, all ADCs run continuously; however, the rising ability to daisy-chain devices and the limit on the number of
edge of the SYNC_IN pin controls the point in time from which devices that can be handled by the chain is dependent on the
data is output. power mode, DCLK, and the decimation rate employed.
To receive data, the master must pulse the SYNC_IN pin to The maximum usable DCLK frequency allowed when daisy-
reset the filter and force DRDY low. DRDY subsequently goes chaining devices is limited by the combination of timing
high to indicate to the master device that the device has valid specifications in Table 2 or Table 4, as well as by the propagation
settled data available. Unlike standard mode, DRDY remains delay of the data between devices and any skew between the MCLK
signals at each AD7761 device. The propagation delay and MCLK
high for the number of clock periods of valid data before it goes
skew are dependent on the PCB layout and trace lengths.
low again; thus, in this conversion mode, it is an active high
frame of the data. This feature is especially useful for reducing component count
and wiring connections, for example, in isolated multiconverter
When the master pulses SYNC_IN and the AD7761 receives the
applications or for systems with a limited interfacing capacity.
rising edge of this signal, the digital filter is reset and the full
settling time of the filter elapses before the data is available. The When daisy-chaining on the AD7761, DOUT6 and DOUT7
duration of the settling time depends on the filter path and become serial data inputs, and DOUT0 and DOUT1 remain as
decimation rate. Running one-shot mode with the sinc5 filter serial data outputs under the control of the FORMATx pins.
allows the fastest throughput, because this filter has a lower
settling time than the wideband filter. AD7761
START

As soon as settled data is available on any channel, the device MCLK SYNCHRONIZATION
LOGIC
SYNC_OUT

outputs data from all channels. The contents of Bit 6 of the channel
header status bits indicates whether the data is fully settled. DIGITAL FILTER DRDY
DOUT0
The period before the data is settled on all channels is shown in DOUT6 DOUT7 SYNC_IN DOUT1

Figure 77. The settling time (tSETTLE) for the AD7761 in one-shot
mode is equivalent to the number of clock cycles specified as IOVDD
DSP/
FPGA

Delay from First MCLK Rise After SYNC_IN Rise to Earliest

AD7761
Settled Data, DRDY Rise in Table 26. After the data has settled START

on all channels, DRDY is asserted high and the device outputs the MASTER
CLOCK
MCLK SYNCHRONIZATION
LOGIC
SYNC_OUT
DNC

required settled data on all channels before DRDY is asserted low.

If the user configures the same filter and decimation rate on each DIGITAL FILTER DRDY
DOUT0
DNC

ADC, the data is settled for all channels on the first DRDY DOUT6 DOUT7 SYNC_IN DOUT1

output frame, which avoids a period of unsettled data prior to

the settled data and ensures that all data is output at the same time IOVDD

on all ADCs. The device then waits for another SYNC_IN signal AD7761
before outputting more data. START
MCLK SYNCHRONIZATION SYNC_OUT
DNC
Because all the ADCs are sampling continuously, one-shot LOGIC

mode affects the sampling theory of the AD7761. Particularly, a DIGITAL FILTER DRDY DNC
user periodically sending a SYNC_IN pulse to the device is a DOUT0
14285-085

DOUT6 DOUT7 SYNC_IN DOUT1

form of subsampling of the ADC output. The subsampling occurs
at the rate of the SYNC_IN pulses. The SYNC_IN pulse must be Figure 78. Daisy-Chaining Multiple AD7761 Devices
synchronous with the master clock to ensure coherent sampling
and to reduce the effects of jitter on the frequency response.

Rev. A | Page 53 of 75
AD7761 Data Sheet
Figure 78 shows an example of daisy-chaining AD7761 devices, Synchronization
when FORMATx = 01. In this case, the DOUT1 and DOUT0 pins An important consideration for daisy-chaining more than two
of the AD7761 devices are cascaded to the DOUT6 and DOUT7 AD7761 devices is synchronization. The basic provision for
pins of the next device in the chain. Data readback is analogous synchronizing multiple devices is that each device is clocked
to clocking a shift register where data is clocked out on the rising with the same base MCLK signal.
edge of DCLK. Input data on the DOUT6 and DOUT7 pins is
The AD7761 offers three options to allow ease of system synchro-
sampled on the falling edge of DCLK.
nization. Choosing between the options depends on the system, but
The scheme operates by passing the output data of the DOUT0 is determined by whether the user can supply a synchronization
and DOUT1 pins of an AD7761 upstream device to the DOUT6 pulse that is truly synchronous with the base MCLK signal.
and DOUT7 inputs of the next AD7761 device downstream in the
If the user cannot provide a signal that is synchronous to the
chain. The data then continues through the chain until it is clocked
base MCLK signal, one of the following two methods can be
onto the DOUT0 and DOUT1 pins of the final downstream
employed:
device in the chain.
Daisy-chaining can be achieved in a similar manner on the • Apply a START pulse to the first AD7761 device. The first
AD7761 when using only the DOUT0 pin. In this case, only AD7761 device samples the asynchronous START pulse
Pin 21 of the AD7761 is used as the serial data input pin. and generates a pulse on SYNC_OUT of the first device
related to the base MCLK signal for distribution locally.
In a daisy-chained system of AD7761 devices, two successive
• Use synchronization over SPI (only available in SPI control
synchronization pulses must be applied to guarantee that all ADCs
mode) to write a synchronization command to the first
are synchronized. Two synchronization pulses are also required in a
system of more than one AD7761 device sharing a single MCLK AD7761 device. Similarly to the START pin method, the
signal, where the DRDY pin of only one device is used to detect SPI sync generates a pulse on SYNC_OUT of the first device
new data. related to the base MCLK signal for distribution locally.

The maximum DCLK frequency that can be used when daisy- In both cases, route the SYNC_OUT pin of the first device to
chaining devices is a function of the AD7761 timing specifications the SYNC_IN pin of that same device and to the SYNC_IN pins
(t4, and t11 in Table 4), the MCLK duty cycle, and any timing of all other devices that are to be synchronized (see Figure 79).
differences between the AD7761 devices due to layout and spacing The SYNC_OUT pins of the other devices must remain open
of devices on the PCB. circuit. Tie all unused START pins to a Logic 1 through pull-up
Use the following formula to aid in determining the maximum resistors.
operating frequency of the interface:
AD7761
1
f MAX =
2 × (t 11 + t 4 + t P + t SKEW )
START
MCLK SYNCHRONIZATION SYNC_OUT
LOGIC

where:
DIGITAL FILTER DRDY
fMAX is the maximum useable DCLK frequency. DOUT0

t11 and t4 are the AD7761 timing specifications (see Table 4). SYNC_IN DOUT1

tP is the maximum propagation delay of the data between DSP/

FPGA
MASTER
successive AD7761 devices in the chain. CLOCK

tSKEW is the maximum skew in the MCLK signal seen by any pair of IOVDD

AD7761 devices in the chain. AD7761

The MCLK duty cycle is 50:50, or DCLK is set to MCLK/2, MCLK
START
SYNC_OUT DNC
SYNCHRONIZATION
MCLK/4, or MCLK/8. LOGIC

DNC
In the case where the MCLK duty cycle is not 50:50 and the DIGITAL FILTER
DRDY

interface is configured with DCLK = MCLK/1, ensure that the

14285-086

SYNC_IN
applied MCLK signal meets the minimum MCLK high pulse width
requirement, as calculated by the following formula: Figure 79. Synchronizing Multiple AD7761 Devices Using SYNC_OUT
MCLK Minimum High Pulse Width = t11 + t4 + tP + tSKEW

Rev. A | Page 54 of 75
Data Sheet AD7761
If the user can provide a signal that is synchronous to the base The following is an example of how the CRC works for four-
MCLK, this signal can be applied directly to the SYNC_IN pin. sample mode (see Figure 81):
Route the signal from a star point and connect it directly to 1. After a synchronization pulse is applied to the AD7761, the
the SYNC_IN pin of each AD7761 device (see Figure 80). The CRC register is cleared to 0xFF.
signal is sampled on the rising MCLK edge; setup and hold 2. The next four 16-bit conversion data samples (N to N + 3)
times are associated with the SYNC_IN input are relative to the for a given channel stream into the CRC calculation.
AD7761 MCLK rising edge. 3. For the first three samples that are output after the
In this case, tie the START pin to Logic 1 through a pull-up synchronization pulse (N to N + 2), the header contains
resistor; SYNC_OUT is not used and can remain open circuit. the normal status bits.
IOVDD
4. For the fourth sample after the synchronization pulse
(N + 3), the 8-bit CRC is sent out instead of the normal
AD7761
START
header status bits, followed by the sample conversion data.
MCLK SYNCHRONIZATION This CRC calculation includes the conversion data that is
LOGIC
output immediately after the CRC header.
DIGITAL FILTER DRDY
5. The CRC register is then cleared back to 0xFF and the
DOUT0
DOUT1
cycle begins again for the fifth to eighth samples after the
SYNC_IN
synchronization pulse.
DSP/
FPGA It is possible to have channels outputting at different rates (for
IOVDD example, decimation by 32 on Channel 0 and decimation by 64 on
Channel 1). In such cases, the CRC header still appears across all
AD7761
START channels at the same time, that is, at every fourth DRDY pulse after
MCLK SYNCHRONIZATION
LOGIC
a synchronization. For the channels operating at a relatively slower
DRDY
DOUT0 ODR, the CRC is still calculated and emitted every 4 or 16 DRDY
DOUT1
DIGITAL FILTER
cycles, even if this means that the nulled data is included.
Therefore, a CRC is calculated for only nulled samples or for a
14285-087

SYNC_IN

combination of nulled samples and actual conversion data.

Figure 80. Synchronizing Multiple AD7761 Devices Using Only SYNC_IN
The AD7761 uses a CRC polynomial to calculate the CRC
CRC Check on Data Interface message. The 8-bit CRC polynomial used is x8 + x2 + x + 1.
The AD7761 delivers 24 bits per channel as standard, which by The CRC Code Example section shows a snippet of the C code,
default consists of 8 status header bits and 16 bits of data. which shows how the CRC value can be calculated for a given
The header bits move to the default value per the description in set of ADC conversion results. Running this code on sets of 4 or
Table 31. However, there is also the option to employ a CRC 16 conversion results gives the CRC value that the AD7761 gives
check on the ADC conversion data. This functionality is available per channel. The user can then compare the computed value
only when operating in SPI control mode. The function is from this code to the actual CRC value read from the AD7761,
controlled by CRC_SELECT in the interface configuration and so confirm that the data read is without error.
register (Register 0x07). When employed, the CRC message is
calculated internally by the AD7761 on a per channel basis. The
CRC then replaces the 8-bit header every four samples or every
16 samples.

DOUT0 N–1 HEADER N DATA N HEADER N + 1 DATA N + 1 HEADER N + 2 DATA N + 2 CRC DATA N + 3
14285-088

8 BITS 16 BITS 8 BITS 16 BITS 8 BITS 16 BITS 8 BITS 16 BITS

Figure 81. CRC 4-Bit Stream

Rev. A | Page 55 of 75
AD7761 Data Sheet
CRC Code Example

#include <stdio.h>
FILE *fi1;
FILE *fo1;
main(){
int num_data_bits=16; // 24 or 16
int num_data_words=4; //4 or 16

int data;
int crc[8],crc_new[8];
int i,j,n,k,num,bit,result;
const int num_crc_bits=8;
int bit_sel[num_data_bits];

bit_sel[23] = 0x800000;
bit_sel[22] = 0x400000;
bit_sel[21] = 0x200000;
bit_sel[20] = 0x100000;
bit_sel[19] = 0x080000;
bit_sel[18] = 0x040000;
bit_sel[17] = 0x020000;
bit_sel[16] = 0x010000;
bit_sel[15] = 0x008000;
bit_sel[14] = 0x004000;
bit_sel[13] = 0x002000;
bit_sel[12] = 0x001000;
bit_sel[11] = 0x000800;
bit_sel[10] = 0x000400;
bit_sel[9] = 0x000200;
bit_sel[8] = 0x000100;
bit_sel[7] = 0x000080;
bit_sel[6] = 0x000040;
bit_sel[5] = 0x000020;
bit_sel[4] = 0x000010;
bit_sel[3] = 0x000008;
bit_sel[2] = 0x000004;
bit_sel[1] = 0x000002;
bit_sel[0] = 0x000001;

fi1 = fopen("adcdata.txt", "r");

fo1 = fopen("crc_out.txt", "w");
j = 1;

Rev. A | Page 56 of 75
Data Sheet AD7761
//initialise CRC to FF
for (i=0;i<num_crc_bits;i++) crc[i]=1;

result = ((crc[7]<<7) & 0x0080)

| ((crc[6]<<6) & 0x0040)
| ((crc[5]<<5) & 0x0020)
| ((crc[4]<<4) & 0x0010)
| ((crc[3]<<3) & 0x0008)
| ((crc[2]<<2) & 0x0004)
| ((crc[1]<<1) & 0x0002)
| ((crc[0]<<0) & 0x0001);

printf("CRC Initialised to 0x%.02X \n",result);

fprintf(fo1,"--------------------------------\n");
fprintf(fo1,"CRC Initialised to 0x%.02X \n",result);

//run CRC on data

for (n = 0; n < num_data_words; n++){

fprintf(fo1,"--------------------------------\n");
fprintf(fo1,"Loop %d start\n",n+1);
fprintf(fo1,"--------------------------------\n");
fprintf(fo1,"ADC Data values\n");
fprintf(fo1,"--------------------------------\n");
fscanf(fi1,"%x\n",&num);
fprintf(fo1,"0x%.06X\n",num);
fprintf(fo1,"--------------------------------\n");
fprintf(fo1,"CRC values\n");
fprintf(fo1,"--------------------------------\n");
for (k=num_data_bits-1;k>=0;k--){
//for (i=7;i>=0;i--){
// printf("%1d",crc[i]);
//}
bit = (num & bit_sel[k]); // msb first
data = bit>>(k);
printf(" bit_sel is: %.06X - data is : %X ",bit_sel[k], data);
crc_new[0]=data^crc[7];
//debug printf(" qq(0) = %1d ",qq[0]);
crc_new[1]=data^crc[7]^crc[0];
crc_new[2]=data^crc[7]^crc[1];
crc_new[3]=crc[2];
crc_new[4]=crc[3];
crc_new[5]=crc[4];
crc_new[6]=crc[5];
crc_new[7]=crc[6];
//debug printf("%8d ",j);
Rev. A | Page 57 of 75
AD7761 Data Sheet
for (i=num_crc_bits-1;i>=0;i--){
crc[i]=crc_new[i];
printf("%1d",crc[i]);
}
//debug printf("\n");
result = ((crc[7]<<7) & 0x0080)
| ((crc[6]<<6) & 0x0040)
| ((crc[5]<<5) & 0x0020)
| ((crc[4]<<4) & 0x0010)
| ((crc[3]<<3) & 0x0008)
| ((crc[2]<<2) & 0x0004)
| ((crc[1]<<1) & 0x0002)
| ((crc[0]<<0) & 0x0001);
printf(" intermediate res is 0x%.02X\n",result);

fprintf(fo1,"intermediate res is 0x%.02X\n",result);

if (k == 0) {
printf("loop %d:res is 0x%.02X\n",n,result);
}

}
}

fprintf(fo1,"--------------------------------\n");
printf("Final CRC value = 0x%.02X\n",result);
fprintf(fo1,"CRC value = 0x%.02X\n",result);

Rev. A | Page 58 of 75
Data Sheet AD7761

FUNCTIONALITY
GPIO FUNCTIONALITY FILTER/GPIO4 11

GPIO PINS
MODE0/GPIO0 12
The AD7761 has additional GPIO functionality when operated MODE1/GPIO1 13
in SPI control mode. This fully configurable mode allows the MODE2/GPIO2 14
device to operate five GPIOs. The GPIOx pins can be set as inputs MODE3/GPIO3 15

or outputs (read or write) on a per pin basis. ST0/CS 16

17 18 19 20 21 22 23 24 25
In write mode, these GPIO pins can be used to control other

ST1/SCLK

DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DEC1/SDI
DEC0/SDO
circuits such as switches, multiplexers, and buffers, over the
same SPI interface as the AD7761. Sharing the SPI interface in
this way allows the user to use a lower overall number of data
lines from the controller compared to a system where multiple

14285-089
control signals are required. This sharing is especially useful in TO DSP/FPGA
systems where reducing the number of control lines across an Figure 82. GPIO Functionality
isolation barrier is important. See Figure 82 for details of the
GPIOx pin options available on the AD7761. Configuration control and readback of the GPIOx pins are set
in Register 0x0E, Register 0x0F, and Register 0x10 (see Table 45,
Similarly, a GPIO read is a useful feature because it allows a Table 46, and Table 47 for more information).
peripheral device to send information to the input GPIO and
then this information can be read from the SPI interface of the
AD7761.

Rev. A | Page 59 of 75
AD7761 Data Sheet

REGISTER MAP DETAILS (SPI CONTROL)

REGISTER MAP
Table 33. Detailed Register Map
Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x00 Channel Standby CH_7 CH_6 CH_5 CH_4 CH_3 CH_2 CH_1 CH_0 0x00 RW
0x01 Channel Mode A Unused FILTER_TYPE_A DEC_RATE_A 0x0D RW
0x02 Channel Mode B Unused FILTER_TYPE_B DEC_RATE_B 0x0D RW
0x03 Channel Mode CH_7_MODE CH_6_MODE CH_5_MODE CH_4_MODE CH_3_MODE CH_2_MODE CH_1_MODE CH_0_MODE 0x00 RW
Select
0x04 POWER_MODE SLEEP_MODE Unused POWER_MODE LVDS_ENABLE Unused MCLK_DIV 0x00 RW
0x05 General Unused CLK_QUAL_DIS RETIME_EN VCM_PD Reserved Unused VCM_VSEL 0x08 RW
Configuration
0x06 Data Control SPI_SYNC Unused SINGLE_SHOT_EN Unused SPI_RESET 0x80 RW
0x07 Interface Unused CRC_SELECT DCLK_DIV 0x0 RW
Configuration
0x08 BIST Control Unused RAM_BIST_ 0x0 RW
START
0x09 Device Status Unused CHIP_ERROR NO_CLOCK_ RAM_BIST_PASS RAM_BIST_ 0x0 R
ERROR RUNNING
0x0A Revision ID REVISION_ID 0x06 R
0x0B Reserved Reserved 0x00 R
0x0C Reserved Reserved 0x00 R
0x0D Reserved Reserved 0x00 R
0x0E GPIO Control UGPIO_ Unused GPIOE4_FILTER GPIOE3_MODE3 GPIOE2_MODE2 GPIOE1_MODE1 GPIO0_MODE0 0x00 RW
ENABLE
0x0F GPIO Write Data Unused GPIO4_WRITE GPIO3_WRITE GPIO2_WRITE GPIO1_WRITE GPIO0_WRITE 0x00 RW

0x10 GPIO Read Data Unused GPIO4_READ GPIO3_READ GPIO2_READ GPIO1_READ GPIO0_READ 0x00 R
0x11 Precharge Buffer 1 CH3_PREBUF_ CH3_PREBUF_ CH2_PREBUF_ CH2_PREBUF_ CH1_PREBUF_ CH1_PREBUF_ CH0_PREBUF_ CH0_PREBUF_ 0xFF RW
NEG_EN POS_EN NEG_EN POS_EN NEG_EN POS_EN NEG_EN POS_EN
0x12 Precharge Buffer 2 CH7_PREBUF_ CH7_PREBUF_ CH6_PREBUF_ CH6_PREBUF_ CH5_PREBUF_ CH5_PREBUF_ CH4_PREBUF_ CH4_PREBUF_ 0xFF RW
NEG_EN POS_EN NEG_EN POS_EN NEG_EN POS_EN NEG_EN POS_EN
0x13 Positive Reference CH7_REFP_ CH6_REFP_ CH5_REFP_ CH4_REFP_BUF CH3_REFP_BUF CH2_REFP_BUF CH1_REFP_BUF CH0_REFP_ 0x00 RW
Precharge Buffer BUF BUF BUF BUF
0x14 Negative Reference CH7_REFN_ CH6_REFN_ CH5_REFN_ CH4_REFN_BUF CH3_REFN_BUF CH2_REFN_BUF CH1_REFN_BUF CH0_REFN_ 0x00 RW
Precharge Buffer BUF BUF BUF BUF
0x1E Channel 0 Offset CH0_OFFSET_MSB 0x00 RW
0x1F CH0_OFFSET_MID
0x20 CH0_OFFSET_LSB
0x21 Channel 1 Offset CH1_OFFSET_MSB 0x00 RW
0x22 CH1_OFFSET_MID
0x23 CH1_OFFSET_LSB
0x24 Channel 2 Offset CH2_OFFSET_MSB 0x00 RW
0x25 CH2_OFFSET_MID
0x26 CH2_OFFSET_LSB
0x27 Channel 3 Offset CH3_OFFSET_MSB 0x00 RW
0x28 CH3_OFFSET_MID
0x29 CH3_OFFSET_LSB
0x2A Channel 4 Offset CH4_OFFSET_MSB 0x00 RW
0x2B CH4_OFFSET_MID
0x2C CH4_OFFSET_LSB
0x2D Channel 5 Offset CH5_OFFSET_MSB 0x00 RW
0x2E CH5_OFFSET_MID
0x2F CH5_OFFSET_LSB
0x30 Channel 6 Offset CH6_OFFSET_MSB 0x00 RW
0x31 CH6_OFFSET_MID
0x32 CH6_OFFSET_LSB
0x33 Channel 7 Offset CH7_OFFSET_MSB 0x00 RW
0x34 CH7_OFFSET_MID
0x35 CH7_OFFSET_LSB
0x36 Channel 0 Gain CH0_GAIN_MSB 0xXX RW
0x37 CH0_GAIN_MID
0x38 CH0_GAIN_LSB

Rev. A | Page 60 of 75
Data Sheet AD7761
Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x39 Channel 1 Gain CH1_GAIN_MSB 0xXX RW
0x3A CH1_GAIN_MID
0x3B CH1_GAIN_LSB
0x3C Channel 2 Gain CH2_GAIN_MSB 0xXX RW
0x3D CH2_GAIN_MID
0x3E CH2_GAIN_LSB
0x3F Channel 3 Gain CH3_GAIN_MSB 0xXX RW
0x40 CH3_GAIN_MID
0x41 CH3_GAIN_LSB
0x42 Channel 4 Gain CH4_GAIN_MSB 0xXX RW
0x43 CH4_GAIN_MID
0x44 CH4_GAIN_LSB
0x45 Channel 5 Gain CH5_GAIN_MSB 0xXX RW
0x46 CH5_GAIN_MID
0x47 CH5_GAIN_LSB
0x48 Channel 6 Gain CH6_GAIN_MSB 0xXX RW
0x49 CH6_GAIN_MID
0x4A CH6_GAIN_LSB
0x4B Channel 7 Gain CH7_GAIN_MSB 0xXX RW
0x4C CH7_GAIN_MID
0x4D CH7_GAIN_LSB
0x4E Channel 0 Sync CH0_SYNC_OFFSET 0x00 RW
Offset
0x4F Channel 1 Sync CH1_SYNC_OFFSET 0x00 RW
Offset
0x50 Channel 2 Sync CH2_SYNC_OFFSET 0x00 RW
Offset
0x51 Channel 3 Sync CH3_SYNC_OFFSET 0x00 RW
Offset
0x52 Channel 4 Sync CH4_SYNC_OFFSET 0x00 RW
Offset
0x53 Channel 5 Sync CH5_SYNC_OFFSET 0x00 RW
Offset
0x54 Channel 6 Sync CH6_SYNC_OFFSET 0x00 RW
Offset
0x55 Channel 7 Sync CH7_SYNC_OFFSET 0x00 RW
Offset
0x56 Diagnostic Rx CH7_RX CH6_RX CH5_RX CH4_RX CH3_RX CH2_RX CH1_RX CH0_RX 0x00 RW
0x57 Diagnostic Mux Unused GRPB_SEL Unused GRPA_SEL 0x00 RW
Control
0x58 Modulator Delay Unused CLK_MOD_DEL_EN Reserved 0x02 RW
Control
0x59 Chop Control Unused GRPA_CHOP GRPB_CHOP 0x0A RW

Rev. A | Page 61 of 75
AD7761 Data Sheet
CHANNEL STANDBY REGISTER
Address: 0x00, Reset: 0x00, Name: Channel Standby
Each of the ADC channels can be put into standby mode independently by setting the appropriate bit in the channel standby register.
When a channel is in standby mode, its position in the data output stream is held. The 8-bit header is all zeros, as is the conversion result
output of 16 zeros.
The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also
disabled for maximum power savings. Channel 0 must be enabled while VCM is being used externally to the AD7761.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into standby mode, the crystal circuitry is
also disabled for maximum power savings. Channel 4 must be enabled while the external crystal is used on the AD7761.

Table 34. Bit Descriptions for Channel Standby

Bits Bit Name Settings Description Reset Access
7 CH_7 Channel 7 0x0 RW
0 Enabled
1 Standby
6 CH_6 Channel 6 0x0 RW
0 Enabled
1 Standby
5 CH_5 Channel 5 0x0 RW
0 Enabled
1 Standby
4 CH_4 Channel 4 0x0 RW
0 Enabled
1 Standby
3 CH_3 Channel 3 0x0 RW
0 Enabled
1 Standby
2 CH_2 Channel 2 0x0 RW
0 Enabled
1 Standby
1 CH_1 Channel 1 0x0 RW
0 Enabled
1 Standby
0 CH_0 Channel 0 0x0 RW
0 Enabled
1 Standby

Rev. A | Page 62 of 75
Data Sheet AD7761
CHANNEL MODE A REGISTER
Address: 0x01, Reset: 0x0D, Name: Channel Mode A
Two mode options are available on the AD7761 ADCs. The channel modes are defined by the contents of the Channel Mode A and
Channel Mode B registers. Each mode is then mapped as desired to the required ADC channel. Channel Mode A and Channel Mode B
allow different filter types and decimation rates to be selected and mapped to any of the ADC channels.
When different decimation rates are selected, the AD7761 outputs a data ready signal at the fastest selected decimation rate. Any channel
that runs at a lower output data rate is updated only at that slower rate. In between valid result data, the data for that channel is set to zero
and the repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the ADC Conversion Output:
Header and Data section).

Table 35. Bit Descriptions for Channel Mode A

Bits Bit Name Settings Description Reset Access
3 FILTER_TYPE_A Filter selection 0x1 RW
0 Wideband filter
1 Sinc5 filter
[2:0] DEC_RATE_A Decimation rate selection 0x5 RW
000 ×32
001 ×64
010 ×128
011 ×256
100 ×512
101 ×1024
110 ×1024
111 ×1024

CHANNEL MODE B REGISTER

Address: 0x02, Reset: 0x0D, Name: Channel Mode B

Table 36. Bit Descriptions for Channel Mode B

Bits Bit Name Settings Description Reset Access
3 FILTER_TYPE_B Filter selection 0x1 RW
0 Wideband filter
1 Sinc5 filter
[2:0] DEC_RATE_B Decimation rate selection 0x5 RW
000 ×32
001 ×64
010 ×128
011 ×256
100 ×512
101 ×1024
110 ×1024
111 ×1024

Rev. A | Page 63 of 75
AD7761 Data Sheet
CHANNEL MODE SELECT REGISTER
Address: 0x03, Reset: 0x00, Name: Channel Mode Select
This register selects the mapping of each ADC channel to either Channel Mode A or Channel Mode B.

Table 37. Bit Descriptions for Channel Mode Select

Bits Bit Name Settings Description Reset Access
7 CH_7_MODE Channel 7 0x0 RW
0 Mode A
1 Mode B
6 CH_6_MODE Channel 6 0x0 RW
0 Mode A
1 Mode B
5 CH_5_MODE Channel 5 0x0 RW
0 Mode A
1 Mode B
4 CH_4_MODE Channel 4 0x0 RW
0 Mode A
1 Mode B
3 CH_3_MODE Channel 3 0x0 RW
0 Mode A
1 Mode B
2 CH_2_MODE Channel 2 0x0 RW
0 Mode A
1 Mode B
1 CH_1_MODE Channel 1 0x0 RW
0 Mode A
1 Mode B
0 CH_0_MODE Channel 0 0x0 RW
0 Mode A
1 Mode B

POWER MODE SELECT REGISTER

Address: 0x04, Reset: 0x00, Name: POWER_MODE

Table 38. Bit Descriptions for POWER_MODE

Bits Bit Name Settings Description Reset Access
7 SLEEP_MODE In sleep mode, many of the digital clocks are disabled and all of the ADCs are 0x0 RW
disabled. The analog LDOs are not disabled.
The AD7761 SPI is live and is available to the user. Writing to this bit brings
the AD7761 out of sleep mode again.
0 Normal operation.
1 Sleep mode.
[5:4] POWER_MODE Power mode. The power mode bits control the power mode setting for the 0x0 RW
bias currents used on all ADCs on the AD7761. The user can select the
current consumption target to meet the application. The power modes of
fast, median, and low power give optimum performance when mapped to
the correct MCLK division setting. These power mode bits do not control the
MCLK division of the ADCs. See the MCLK_DIV bits for control of the division
of the MCLK input.
00 Low power.
10 Median.
11 Fast.
3 LVDS_ENABLE LVDS clock. 0x0 RW
0 LVDS input clock disabled.
1 LVDS input clock enabled.
Rev. A | Page 64 of 75
Data Sheet AD7761
Bits Bit Name Settings Description Reset Access
[1:0] MCLK_DIV MCLK division. The MCLK division bits control the divided ratio between the 0x0 RW
MCLK applied at the input to the AD7761 and the clock used by each of the
ADC modulators. The appropriate division ratio depends on the following
factors: power mode, decimation rate, and the base MCLK available in the
system. See the Clocking, Sampling Tree, and Power Scaling section for more
information on setting MCLK_DIV correctly.
00 MCLK/32: with a base MCLK of 32.768 MHz, set to MCLK/32 for low power mode.
10 MCLK/8: with a base MCLK of 32.768 MHz, set to MCLK/8 for median mode.
11 MCLK/4: with a base MCLK of 32.768 MHz, set to MCLK/4 for fast mode.

GENERAL DEVICE CONFIGURATION REGISTER

Address: 0x05, Reset: 0x08, Name: General Configuration

Table 39. Bit Descriptions for General Configuration

Bits Bit Name Settings Description Reset Access
6 CLK_QUAL_DIS Clock qualification disable bit. Allows the user to disable 0x0 RW
the external clock source qualification. Following a reset,
the frequency of the externally applied MCLK is checked.
It is accepted as valid if it is greater than approximately
1.15 MHz. The AD7761 then hands control over to the
external clock source. If this qualification check fails, the
NO_CLOCK_ERROR bit is set and the AD7761 continues to
run using the internal startup clock.
Users can disable this qualification check to force the
AD7761 to accept and pass control to an external clock
source with a lower frequency.
0 Enabled. Clock qualification check is performed.
1 Disabled. Clock qualification check is not performed.
5 RETIME_EN SYNC_OUT signal retime enable bit. 0x0 RW
0 Disabled: normal timing of SYNC_OUT.
1 Enabled: SYNC_OUT signal derived from alternate
MCLK edge.
4 VCM_PD VCM buffer power-down. 0x0 RW
0 Enabled: VCM buffer normal mode.
1 Powered down: VCM buffer powered down.
[1:0] VCM_VSEL VCM voltage. These bits select the output voltage of the 0x0 RW
VCM pin. This voltage is derived from the AVDD1 supply
and can be output as half of that AVDD1 voltage, or other
fixed voltages, with respect to AVSS. The VCM voltage
output is associated with the Channel 0 circuitry. If
Channel 0 is put into standby mode, the VCM voltage
output is also disabled for maximum power savings.
Channel 0 must be enabled while VCM is being used
externally to the AD7761.
00 (AVDD1 − AVSS)/2 V.
01 1.65 V.
10 2.5 V.
11 2.14 V.

Rev. A | Page 65 of 75
AD7761 Data Sheet
DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER
Address: 0x06, Reset: 0x80, Name: Data Control

Table 40. Bit Descriptions for Data Control

Bits Bit Name Settings Description Reset Access
7 SPI_SYNC Software synchronization of the AD7761. This command has the same 0x1 RW
effect as sending a signal pulse to the START pin. To operate the SPI_SYNC,
the user must write to this bit two separate times. First, write a zero,
putting SPI_SYNC low, and then write a 1 to set SPI_SYNC logic high
again. The SPI_SYNC command is recognized after the last rising edge of
SCLK in the SPI instruction where the SPI_SYNC bit is changed from low to
high. The SPI_SYNC command is then output synchronous to the AD7761
MCLK on the SYNC_OUT pin. The user must connect the SYNC_OUT signal
to the SYNC_IN pin on the PCB. The SYNC_OUT pin can also be routed to
the SYNC_IN pins of other AD7761 devices, allowing larger channel count
simultaneous sampling systems. As per any synchronization pulse seen by
the SYNC_IN pin, the digital filters of the AD7761 are reset. The full settling
time of the filters must elapse before data is output on the data interface. In a
daisy-chained system of AD7761 devices, two successive synchronization
pulses must be applied to guarantee that all ADCs are synchronized. Two
synchronization pulses are also required in a system of more than one
AD7761 device sharing a single MCLK signal, where the DRDY pin of only
one device is used to detect new data.
0 Change to SPI_SYNC low.
1 Change to SPI_SYNC high.
4 SINGLE_SHOT_EN One-shot mode. Enables one-shot mode. In one-shot mode, the AD7761 0x0 RW
outputs a conversion result in response to a SYNC_IN rising edge.
0 Disabled.
1 Enabled.
[1:0] SPI_RESET Soft reset. These bits allow a full device reset over the SPI port. Two 0x0 RW
successive commands must be received in the correct order to generate a
reset: first, write 0x03 to the soft reset bits, and then write 0x02 to the soft
reset bits. This sequence causes the digital core to reset and all registers
return to their default values. Following a soft reset, if the SPI master
sends a command to the AD7761, the device responds on the next frame
to that command with an output of 0x0E00.
00 No effect.
01 No effect.
10 Second reset command.
11 First reset command.

INTERFACE CONFIGURATION REGISTER

Address: 0x07, Reset: 0x0, Name: Interface Configuration

Table 41. Bit Descriptions for Interface Configuration

Bits Bit Name Settings Description Reset Access
[3:2] CRC_SELECT CRC select. These bits allow the user to implement a CRC on the data 0x0 RW
interface. When selected, the CRC replaces the header every fourth or 16th
output sample depending on the CRC option chosen. There are two
options for the CRC; both use the same polynomial: x8 + x2 + x + 1. The
options offer the user the ability to reduce the duty cycle of the CRC
calculation by performing it less often: in the case of having it every 16th
sample, or more often in the case of every fourth conversion. The CRC is
calculated on a per channel basis and it includes conversion data only.
00 No CRC. Status bits with every conversion.
01 Replace the header with CRC message every 4 samples.
10 Replace the header with CRC message every 16 samples.
11 Replace the header with CRC message every 16 samples.

Rev. A | Page 66 of 75
Data Sheet AD7761
Bits Bit Name Settings Description Reset Access
[1:0] DCLK_DIV DCLK divider. These bits control division of the DCLK clock used to clock 0x0 RW
out conversion data on the DOUTx pins. The DCLK signal is derived from
the MCLK signal applied to the AD7761. The DCLK divide mode allows the
user to optimize the DCLK output to fit the application. Optimizing the
DCLK signal per application depends on the requirements of the user. When
the AD7761 uses the highest capacity output on the fewest DOUTx pins, for
example, running in decimate by 32 using the DOUT0 and DOUT1 pins, the
DCLK signal must equal the MCLK signal; thus, in this case, choosing the
no division setting is the only way the user can output all the data within
the conversion period. There are other cases, however, when the ADC may
be running in fast mode with high decimation rates, or in median or low
power mode where the DCLK signal does not need to run at the same
speed as MCLK. In these cases, the DCLK divide allows the user to reduce
the clock speed and makes routing and isolating such signals easier.
00 Divide by 8.
01 Divide by 4.
10 Divide by 2.
11 No division.

DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER

Address: 0x08, Reset: 0x0, Name: BIST Control

Table 42. Bit Descriptions for BIST Control

Bits Bit Name Settings Description Reset Access
0 RAM_BIST_START RAM BIST. Filter RAM BIST is a built in self test of the internal RAM. Normal ADC 0x0 RW
conversion is disrupted when this test is run. A synchronization pulse is required
after this test is complete to resume normal ADC operation. The test can be run at
intervals depending on user preference. The status and result of the RAM BIST is
available in the device status register; see the RAM_BIST_PASS and
RAM_BIST_RUNNING bits in Table 43.
0 Off.
1 Begin RAM BIST.

STATUS REGISTER
Address: 0x09, Reset: 0x0, Name: Device Status

Table 43. Bit Descriptions for Device Status

Bits Bit Name Settings Description Reset Access
3 CHIP_ERROR Chip error. Chip error is a global error flag that is output within the status byte 0x0 R
of each ADC conversion output. The following bits lead to the chip error bit
being set to logic high: CRC check on internally hard coded settings (after power-
up) does not pass; XOR check on the internal memory does not pass (this check
runs continuously in the background); and clock error is detected on power-up.
0 No error present.
1 Error has occurred.
2 NO_CLOCK_ERROR External clock check. This bit indicates whether the externally applied MCLK is 0x0 R
detected correctly. If the MCLK is not applied correctly to the ADC at power-
up, this bit is set and the DCLK frequency is approximately 16 MHz. If this bit is set,
the chip error bit is set to logic high in the status bits of the data output
headers, and the conversion results are output as all zeros regardless of the
analog input voltages applied to the ADC channels.
0 MCLK detected.
1 No MCLK detected.
1 RAM_BIST_PASS BIST pass/fail. RAM BIST result status. This bit indicates the result of the most 0x0 R
recent RAM BIST. The result is latched to this register and is only cleared by a
device reset.
0 BIST failed or not run.
1 BIST passed.
Rev. A | Page 67 of 75
AD7761 Data Sheet
Bits Bit Name Settings Description Reset Access
0 RAM_BIST_RUNNING BIST status. Reading back the value of this bit allows the user to poll when the 0x0 R
BIST test has finished.
0 BIST not running.
1 BIST running.

REVISION IDENTIFICATION REGISTER

Address: 0x0A, Reset: 0x06, Name: Revision ID

Table 44. Bit Descriptions for Revision ID

Bits Bit Name Description Reset Access
[7:0] REVISION_ID ASIC revision. 8-bit ID for revision details. 0x06 R

GPIO CONTROL REGISTER

Address: 0x0E, Reset: 0x00, Name: GPIO Control

Table 45. Bit Descriptions for GPIO Control

Bits Bit Name Setting Description Reset Access
7 UGPIO_ENABLE User GPIO enable. The GPIOx pins are dual purpose and can be operated only 0x0 RW
when the device is in SPI control mode. By default, when the AD7761 is powered
up in SPI control mode, the GPIOx pins are disabled. This bit is a universal enable/
disable for all GPIOx input/outputs. The direction of each general-purpose pin
is determined by Bits[4:0] of this register.
0 GPIO disabled.
1 GPIO enabled.
4 GPIOE4_FILTER GPIO4 direction. This bit assigns the direction of GPIO4 as either an input or an 0x0 RW
output. For SPI control, GPIO4 maps to Pin 11, which is the FILTER/GPIO4 pin.
0 Input.
1 Output.
3 GPIOE3_MODE3 GPIO3 direction. This bit assigns the direction of GPIO3 as either an input or an 0x0 RW
output. For SPI control, GPIO3 maps to Pin 15, which is the MODE3/GPIO3 pin.
0 Input.
1 Output.
2 GPIOE2_MODE2 GPIO2 direction. This bit assigns the direction of GPIO2 as either an input or an 0x0 RW
output. For SPI control, GPIO2 maps to Pin 14, which is the MODE2/GPIO2 pin.
0 Input.
1 Output.
1 GPIOE1_MODE1 GPIO1 direction. This bit assigns the direction of GPIO1 as either an input or an 0x0 RW
output. For SPI control, GPIO1 maps to Pin 13, which is the MODE1/GPIO1 pin.
0 Input.
1 Output.
0 GPIO0_MODE0 GPIO0 direction. This bit assigns the direction of GPIO0 as either an input or an 0x0 RW
output. For SPI control, GPIO0 maps to Pin 12, which is the MODE0/GPIO0 pin.
0 Input.
1 Output.

Rev. A | Page 68 of 75
Data Sheet AD7761
GPIO WRITE DATA REGISTER
Address: 0x0F, Reset: 0x00, Name: GPIO Write Data
This register writes the values to be set on each of the general-purpose pins when selected as general-purpose outputs. Each bit, from
Bits[4:0], maps directly to the GPIOx pins.

Table 46. Bit Descriptions for GPIO Write Data

Bits Bit Name Description Reset Access
4 GPIO4_WRITE FILTER/GPIO4 0x0 RW
3 GPIO3_WRITE MODE3/GPIO3 0x0 RW
2 GPIO2_WRITE MODE2/GPIO2 0x0 RW
1 GPIO1_WRITE MODE1/GPIO1 0x0 RW
0 GPIO0_WRITE MODE0/GPIO0 0x0 RW

GPIO READ DATA REGISTER

Address: 0x10, Reset: 0x00, Name: GPIO Read Data
This register reads back the value of the logic input level at the general-purpose pins when selected to operate as general-purpose inputs.
Each bit, from Bits[4:0], maps directly to the GPIO0 to GPIO4 pins.

Table 47. Bit Descriptions for GPIO Read Data

Bits Bit Name Description Reset Access
4 GPIO4_READ FILTER/GPIO4 0x0 R
3 GPIO3_READ MODE3/GPIO3 0x0 R
2 GPIO2_READ MODE2/GPIO2 0x0 R
1 GPIO1_READ MODE1/GPIO1 0x0 R
0 GPIO0_READ MODE0/GPIO0 0x00 R

ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3

Address: 0x11, Reset: 0xFF, Name: Precharge Buffer 1
This register turns on or off the precharge buffers on the analog inputs. When writing to these registers, the user must write the inverse of
the required bit settings. For example, to clear Bit 1 of this register, the user must write 0x01 to the register. This clears Bit 1 and sets all
other bits. If the user reads the register again after writing 0x01, the data read is 0xFE, as required.

Table 48. Bit Descriptions for Precharge Buffer 1

Bits Bit Name Settings Description Reset
7 CH3_PREBUF_NEG_EN 0 Off 0x1
1 On
6 CH3_PREBUF_POS_EN 0 Off 0x1
1 On
5 CH2_PREBUF_NEG_EN 0 Off 0x1
1 On
4 CH2_PREBUF_POS_EN 0 Off 0x1
1 On
3 CH1_PREBUF_NEG_EN 0 Off 0x1
1 On
2 CH1_PREBUF_POS_EN 0 Off 0x1
1 On
1 CH0_PREBUF_NEG_EN 0 Off 0x1
1 On
0 CH0_PREBUF_POS_EN 0 Off 0x1
1 On

Rev. A | Page 69 of 75
AD7761 Data Sheet
ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7
Address: 0x12, Reset: 0xFF, Name: Precharge Buffer 2
This register turns on or off the precharge buffers on the analog inputs. When writing to these registers, the user must write the inverse of
the required bit settings. For example, to clear Bit 1 of this register, the user must write 0x01 to the register. This clears Bit 1 and sets all
other bits. If the user reads the register again after writing 0x01, the data read is 0xFE, as required.

Table 49. Bit Descriptions for Precharge Buffer 2

Bits Bit Name Settings Description Reset
7 CH7_PREBUF_NEG_EN 0 Off 0x1
1 On
6 CH7_PREBUF_POS_EN 0 Off 0x1
1 On
5 CH6_PREBUF_NEG_EN 0 Off 0x1
1 On
4 CH6_PREBUF_POS_EN 0 Off 0x1
1 On
3 CH5_PREBUF_NEG_EN 0 Off 0x1
1 On
2 CH5_PREBUF_POS_EN 0 Off 0x1
1 On
1 CH4_PREBUF_NEG_EN 0 Off 0x1
1 On
0 CH4_PREBUF_POS_EN 0 Off 0x1
1 On

POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER

Address: 0x13, Reset: 0x00, Name: Positive Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference positive input to each of the ADCs from Channel 0 to Channel 7.

Table 50. Bit Descriptions for Positive Reference Precharge Buffer

Bits Bit Name Settings Description Reset
7 CH7_REFP_BUF 0 Off 0x0
1 On
6 CH6_REFP_BUF 0 Off 0x0
1 On
5 CH5_REFP_BUF 0 Off 0x0
1 On
4 CH4_REFP_BUF 0 Off 0x0
1 On
3 CH3_REFP_BUF 0 Off 0x0
1 On
2 CH2_REFP_BUF 0 Off 0x0
1 On
1 CH1_REFP_BUF 0 Off 0x0
1 On
0 CH0_REFP_BUF 0 Off 0x0
1 On

Rev. A | Page 70 of 75
Data Sheet AD7761
NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER
Address: 0x14, Reset: 0x00, Name: Negative Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference negative input to each of the ADCs from Channel 0 to Channel 7.

Table 51. Bit Descriptions for Negative Reference Precharge Buffer

Bits Bit Name Settings Description Reset
7 CH7_REFN_BUF 0 Off 0x0
1 On
6 CH6_REFN_BUF 0 Off 0x0
1 On
5 CH5_REFN_BUF 0 Off 0x0
1 On
4 CH4_REFN_BUF 0 Off 0x0
1 On
3 CH3_REFN_BUF 0 Off 0x0
1 On
2 CH2_REFN_BUF 0 Off 0x0
1 On
1 CH1_REFN_BUF 0 Off 0x0
1 On
0 CH0_REFN_BUF 0 Off 0x0
1 On

OFFSET REGISTERS
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_OFFSET_LSB registers are 24 bit, signed twos complement registers for channel
offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital
output by −1/192 LSBs. For example, changing the offset register from 0 to 4800 changes the digital output by −25 LSBs. Because offset
adjustment occurs before gain adjustment, the ratio of 1/192 changes linearly with gain adjustment via the CHx_GAIN_x registers. After a
reset or power cycle, the register values revert to the default factory setting.

Table 52. Per Channel 24-Bit Offset Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, Mid, and LSB
Address Reset
MSB Mid LSB Name Description MSB Mid LSB Access
0x1E 0x1F 0x20 Channel 0 offset Channel 0 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x21 0x22 0x23 Channel 1 offset Channel 1 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x24 0x25 0x26 Channel 2 offset Channel 2 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x27 0x28 0x29 Channel 3 offset Channel 3 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x2A 0x2B 0x2C Channel 4 offset Channel 4 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x2D 0x2E 0x2F Channel 5 offset Channel 5 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x30 0x31 0x32 Channel 6 offset Channel 6 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW
0x33 0x34 0x35 Channel 7 offset Channel 7 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00 RW

Rev. A | Page 71 of 75
AD7761 Data Sheet
GAIN REGISTERS
Each ADC channel has an associated gain coefficient. The coefficient is stored in three single-byte registers split up as MSB, MID, and
LSB. Each of the gain registers are factory programmed. Nominally, this gain is around the value 0x555555 (for an ADC channel). The
user can overwrite the gain register setting; however, after a reset or power cycle, the gain register values revert to the hard coded
programmed factory setting.

Table 53. Per Channel 24-Bit Gain Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, Mid, and LSB
Address Reset
MSB Mid LSB Name Description MSB Mid LSB Access
0x36 0x37 0x38 Channel 0 gain Channel 0 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x39 0x3A 0x3B Channel 1 gain Channel 1 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x3C 0x3D 0x3E Channel 2 gain Channel 2 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x3F 0x40 0x41 Channel 3 gain Channel 3 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x42 0x43 0x44 Channel 4 gain Channel 4 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x45 0x46 0x47 Channel 5 gain Channel 5 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x48 0x49 0x4A Channel 6 gain Channel 6 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x4B 0x4C 0x4D Channel 7 gain Channel 7 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW

SYNC PHASE OFFSET REGISTERS

The AD7761 has one synchronization signal for all channels. The sync phase offset register allows the user to vary the phase delay on each
of the channels relative to the synchronization edge received on the SYNC_IN pin. See the Sync Phase Offset Adjustment section for details
on the use of this function.

Table 54. Per Channel 8-Bit Sync Phase Offset Registers

Address Name Description Reset Access
0x4E Channel 0 sync offset Channel 0 sync phase offset register 0x00 RW
0x4F Channel 1 sync offset Channel 1 sync phase offset register 0x00 RW
0x50 Channel 2 sync offset Channel 2 sync phase offset register 0x00 RW
0x51 Channel 3 sync offset Channel 3 sync phase offset register 0x00 RW
0x52 Channel 4 sync offset Channel 4 sync phase offset register 0x00 RW
0x53 Channel 5 sync offset Channel 5 sync phase offset register 0x00 RW
0x54 Channel 6 sync offset Channel 6 sync phase offset register 0x00 RW
0x55 Channel 7 sync offset Channel 7 sync phase offset register 0x00 RW

ADC DIAGNOSTIC RECEIVE SELECT REGISTER

Address: 0x56, Reset: 0x00, Name: Diagnostic Rx
The AD7761 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can
be converted to verify the correct operation of the ADC channel. This register enables the diagnostic. Enable the receive (Rx) for each
channel and set each bit in this register to 1.
The ADC diagnostic feature depends on some features of the analog input precharge buffers. The user must ensure that the analog input
precharge buffers are enabled on the channels that are selected to receive the diagnostic voltages internally.

Table 55. Bit Descriptions for Diagnostic Rx

Bits Bit Name Settings Description Reset Access
7 CH7_RX Channel 7 0x0 RW
0 Not in use
1 Receive
6 CH6_RX Channel 6 0x0 RW
0 Not in use
1 Receive

Rev. A | Page 72 of 75
Data Sheet AD7761
Bits Bit Name Settings Description Reset Access
5 CH5_RX Channel 5 0x0 RW
0 Not in use
1 Receive
4 CH4_RX Channel 4 0x0 RW
0 Not in use
1 Receive
3 CH3_RX Channel 3 0x0 RW
0 Not in use
1 Receive
2 CH2_RX Channel 2 0x0 RW
0 Not in use
1 Receive
1 CH1_RX Channel 1 0x0 RW
0 Not in use
1 Receive
0 CH0_RX Channel 0 0x0 RW
0 Not in use
1 Receive

ADC DIAGNOSTIC CONTROL REGISTER

Address: 0x57, Reset: 0x00, Name: Diagnostic Mux Control
The AD7761 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can
be converted to verify the correct operation of the ADC channel. This register controls the voltage that is applied to each of the ADC
channels for the diagnostic. There are three input voltage options that the user can select. The voltage selected is mapped to the channels based
on the mode (Channel Mode A or Channel Mode B) they belong to, which is set according to the channel mode select register (Register 0x03).
Set Bits[7:0] to 1 in the ADC diagnostic receive select register, then select the voltage check desired for the channels on Channel Mode A
and the channels on Channel Mode B through Bits[2:0] and Bits[6:4], respectively.

Table 56. Bit Descriptions for Diagnostic Mux Control

Bits Bit Name Settings Description Reset Access
[6:4] GRPB_SEL Mux B. 0x0 RW
000 Off.
011 Positive full-scale ADC check. A voltage close to positive full scale is applied internally to
the ADC channel.
100 Negative full-scale ADC check. A voltage close to negative (or minus) full scale is applied
internally to the ADC channel.
101 Zero-scale ADC check. A voltage close to 0 V is applied internally to the ADC channel.
[2:0] GRPA_SEL Mux A. 0x0 RW
000 Off.
011 Positive full-scale ADC check. A voltage close to positive full scale is applied internally to
the ADC channel.
100 Negative full-scale ADC check. A voltage close to negative (or minus) full scale is applied
internally to the ADC channel.
101 Zero-scale ADC check. A voltage close to 0 V is applied internally to the ADC channel.

Rev. A | Page 73 of 75
AD7761 Data Sheet
MODULATOR DELAY CONTROL REGISTER
Address: 0x58, Reset: 0x02, Name: Modulator Delay Control

Table 57. Bit Descriptions for Modulator Delay Control

Bits Bit Name Settings Description Reset Access
[3:2] CLK_MOD_DEL_EN Enable delayed modulator clock. 0x0 RW
00 Disabled delayed clock for all channels.
01 Enable delayed clock for Channel 0 to Channel 3 only on the AD7761.
10 Enable delayed clock for Channel 4 to Channel 7 only on the AD7761.
11 Enable delayed clock for all channels.
[1:0] Reserved 10 Not a user option. Must be set to 0x2. 0x2 RW

CHOPPING CONTROL REGISTER

Address: 0x59, Reset: 0x0A, Name: Chop Control

Table 58. Bit Descriptions for Chop Control

Bits Bit Name Settings Description Reset Access
[3:2] GRPA_CHOP Group A chopping 0x2 RW
01 Chop at fMOD/8
10 Chop at fMOD/32
[1:0] GRPB_CHOP Group B chopping 0x2 RW
01 Chop at fMOD/8
10 Chop at fMOD/32

Rev. A | Page 74 of 75
Data Sheet AD7761

OUTLINE DIMENSIONS
12.20
0.75 12.00 SQ
0.60 1.60 11.80
0.45 MAX
64 49
1 48

PIN 1

10.20
TOP VIEW 10.00 SQ
(PINS DOWN)
9.80
1.45
0.20
1.40
0.09
1.35
7°
3.5°
0.15 16 33
0°
0.05 SEATING 17 32
PLANE 0.08
COPLANARITY VIEW A 0.27
0.50
BSC 0.22
VIEW A LEAD PITCH 0.17
ROTATED 90° CCW

051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BCD

Figure 83. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7761BSTZ −40°C to +105°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
AD7761BSTZ-RL7 −40°C to +105°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
EVAL-AD7761FMCZ Evaluation Board
EVAL-SDP-CH1Z Controller Board
1
Z = RoHS Compliant Part.

©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D14285-0-9/17(A)

Rev. A | Page 75 of 75