M95M04-DR

Datasheet

4-Mbit serial SPI bus EEPROM

Features
• Compatible with the serial peripheral interface (SPI) bus
SO8N (MN) • Memory array
150 mil width
– 4 Mbit (512 Kbytes) of EEPROM
– Page size: 512 bytes
– Additional write lockable page (identification page)
• Write time
– Byte write within 5 ms
– Page write within 5 ms
TSSOP8 (DW) • Write protect
169 mil width – quarter array
– half array
– whole memory array
• Max clock frequency:
– 10 MHz for VCC ≥ 2.5 V
WLCSP (2.809 × 1.863 mm)
– 5 MHz for VCC ≥ 1.8 V
• Single supply voltage: 1.8 V to 5.5 V
• Operating temperature range: from -40 °C up to +85 °C
• Enhanced ESD protection (up to 4 kV in human body model)
• More than 4 million write cycles
Product status link • More than 40-year data retention
M95M04-DR • Packages
– SO8N (ECOPACK2)
– TSSOP8 (ECOPACK2)
Product label
– WLCSP (ECOPACK2)

DS12179 - Rev 3 - March 2023 www.st.com

For further information contact your local STMicroelectronics sales office.
 M95M04-DR
Description

1 Description

The M95M04-DR device is electrically erasable programmable memory (EEPROM) organized as 524288 x 8 bits,
accessed through the SPI bus.
The M95M04-DR can operate with a supply range from 1.8 to 5.5 V, and is guaranteed over the -40 °C/+85 °C
temperature range.
The M95M04-DR offer an additional page, named the identification page (512 bytes). The identification page can
be used to store sensitive application parameters that can be (later) permanently locked in read-only mode.

Figure 1. Logic diagram

VCC

D
C
S M95xxx Q
W
HOLD

DT45413V2
VSS

The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is selected when Chip select
(S) is driven low. Communications with the device can be interrupted when the HOLD is driven low.

Table 1. Signal names

Signal name Function Direction

C Serial clock Input

D Serial data input Input
Q Serial data output Output
S Chip select Input
W Write protect Input
HOLD Hold Input
VCC Supply voltage -

VSS Ground -

DS12179 - Rev 3 page 2/44

 M95M04-DR
Description

Figure 2. 8-pin package connections (top view)

M95xxx
S 1 8 VCC

Q 2 7 HOLD

W 3 6 C

VSS 4 5 D

DT51579V2
1. See Section 10 Package information for package dimensions, and how to identify pin 1.

Figure 3. WLCSP connections

4 3 2 1 1 2 3 4

A A
B B

C C
D D

DT38243V2
Bump side view Top view (bumps underneath)

Table 2. Signals vs. bump position

Position A B C D

1 - - C -

2 VCC HOLD - D

3 S - - VSS

4 - Q W -

DS12179 - Rev 3 page 3/44

 M95M04-DR
Memory organization

2 Memory organization

The memory is organized as shown in the following figure.

Figure 4. Block diagram

S Sense amplifiers
Data register and ECC

Q Page latches X decoder

Y decoder
W
Array
I/Os Status
D register
Control Custom area*
C logic
HV generator
and sequencer
Address
HOLD

DT52059V2
register

* Identification page

DS12179 - Rev 3 page 4/44

 M95M04-DR
Signal description

3 Signal description

During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as
specified in Section 9 DC and AC parameters). These signals are described next.

3.1 Serial data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial
clock (C).

3.2 Serial data input (D)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data
to be written. Values are latched on the rising edge of serial clock (C).

3.3 Serial clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data
input (D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) change from the falling
edge of serial clock (C).

3.4 Chip select (S)

When this input signal is high, the device is deselected and serial data output (Q) is at high impedance. The
device is in the standby power mode, unless an internal write cycle is in progress. Driving chip select (S) low
selects the device, placing it in the active power mode.
After power-up, a falling edge on chip select (S) is required prior to the start of any instruction.

3.5 Hold (HOLD)

The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the
device.
During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock
(C) are "Don’t care".
To start the hold condition, the device must be selected, with chip select (S) driven low.

3.6 Write protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write
instructions (as specified by the values in the BP1 and BP0 bits of the Status register).
This pin must be driven either high or low, and must be stable during all Write instructions.

3.7 VCC supply voltage

VCC is the supply voltage.

3.8 VSS ground

VSS is the reference for all signals, including the VCC supply voltage.

DS12179 - Rev 3 page 5/44

 M95M04-DR
Connecting to the SPI bus

4 Connecting to the SPI bus

All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The serial
data input (D) is sampled on the first rising edge of the serial clock (C) after chip select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The serial data output (Q) is latched
on the first falling edge of the serial clock (C) after the instruction (such as the read from memory array and read
status register instructions) have been clocked into the device.

Figure 5. Bus master and memory devices on the SPI bus

VCC

SPI interface with SDO

(CPOL, CPHA) = SDI
(0, 0) or 1, 1) SCK

C Q D VCC C Q D VCC C Q D VCC

SPI bus master

SPI memory SPI memory SPI memory

R R R
device device device
CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD

(1) (1) (1) (1) (1) (1)

MS19755V3

DT19755V2
VSS

1. The write protect (W) and hold (HOLD) signals should be driven, high or low as appropriate.
Figure 5 shows an example of three memory devices connected to an SPI bus master. Only one memory device
is selected at a given time, so only one memory device drives the serial data output (Q) line at that time. The
other memory devices are in high impedance state. The pull-up resistor R ensures that a device is not selected if
the bus master leaves the S line in the high impedance state.
In applications where the bus master may leave all SPI bus lines in high impedance at the same time (for
example, if the Bus master is reset during the transmission of an instruction), it is recommended to connect the
clock line (C) to an external pull-down resistor so that, if all inputs/outputs become high impedance, the C line is
pulled low (while the S line is pulled high): this ensures that S and C do not become high at the same time, and
so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.

DS12179 - Rev 3 page 6/44

 M95M04-DR
SPI modes

4.1 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two
modes:
• CPOL = 0, CPHA = 0
• CPOL = 1, CPHA = 1
For these two modes, input data is latched in on the rising edge of serial clock (C), and output data is available
from the falling edge of serial clock (C).
The difference between the two modes, as shown in Figure 6, is the clock polarity when the bus master is in
stand-by mode and not transferring data:
• C remains at 0 for (CPOL = 0, CPHA = 0)
• C remains at 1 for (CPOL = 1, CPHA = 1)

Figure 6. SPI modes supported

CPOL CPHA
0 0 C

1 1 C
MS19755V3
D MSB

DT42674V2
Q MSB

DS12179 - Rev 3 page 7/44

 M95M04-DR
Operating features

5 Operating features

5.1 Supply voltage (VCC)

5.1.1 Operating supply voltage (VCC)

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified
[VCC(min), VCC(max)] range must be applied (see operating conditions in Section 9 DC and AC parameters).
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write
instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually in the range between 10 and 100 nF)
close to the VCC / VSS device pins.

5.1.2 Device reset

In order to prevent erroneous instruction decoding and inadvertent write operations during power-up, a power-on-
reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the
POR threshold voltage. This threshold is lower than the minimum VCC operating voltage (see operating conditions
in Section 9 DC and AC parameters).
At power-up, when VCC passes over the POR threshold, the device is reset and is in the following state:
• in Standby power mode,
• deselected,
• Status register values:
– the write enable latch (WEL) bit is reset to 0
– the write in progress (WIP) bit is reset to 0
– the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until VCC reaches a valid and stable level within
the specified [VCC(min), VCC(max)] range, as defined under Operating conditions in Section 9 DC and AC
parameters.

5.1.3 Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the chip select (S)
line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to
VCC via a suitable pull-up resistor (see Figure 5).
In addition, the chip select (S) input offers a built-in safety feature, as the S input is edge-sensitive as well as
level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected
on chip select (S). This ensures that chip select (S) must have been high, prior to going low to start the first
operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in
Section 9 DC and AC parameters.

DS12179 - Rev 3 page 8/44

 M95M04-DR
Active power and standby power modes

5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage
defined in Section 9 DC and AC parameters), the device must be:
• deselected (chip select S must be allowed to follow the voltage applied on VCC)
• in standby power mode (there must not be any internal write cycle in progress).

5.2 Active power and standby power modes

When chip select (S) is low, the device is selected, and in the active power mode. The device consumes ICC.
When chip select (S) is high, the device is deselected. If a write cycle is not currently in progress, the device then
goes into the standby power mode, and the device consumption drops to ICC1, as specified in DC characteristics
(see Section 9 DC and AC parameters).

5.3 Hold condition

The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking
sequence.
To enter the hold condition, the device must be selected, with chip select (S) low.
During the hold condition, the serial data output (Q) is high impedance, and the serial data input (D) and the serial
clock (C) are "Don’t care".
Normally, the device is kept selected for the whole duration of the Hold condition. Deselecting the device while it is
in the hold condition has the effect of resetting the state of the device: this mechanism can be used, if required, to
reset the ongoing processes.
Note: This resets the internal logic, except the WEL and WIP bits of the status register.
Note: In the specific case where the device has moved in a write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the write cycle of this decoded command.

Figure 7. Hold condition activation

HOLD
MS19755V3
DT47281V2
Hold Hold
condition condition

The hold condition starts when the hold (HOLD) signal is driven low when serial clock (C) is already low (as
shown in Figure 7).
Figure 7 also shows what happens if the rising and falling edges are not timed to coincide with serial clock (C)
being low.

DS12179 - Rev 3 page 9/44

 M95M04-DR
Status register

5.4 Status register

The status register contains a number of status and control bits that can be read or set (as appropriate) by
specific instructions. See Section 6.3 Read status register (RDSR) for a detailed description of the status register
bits.

5.5 Data protection and protocol control

The device features the following data protection mechanisms:
• Before accepting the execution of the write and write status register instructions, the device checks
whether the number of clock pulses comprised in the instructions is a multiple of eight.
• All instructions that modify data must be preceded by a write enable (WREN) instruction to set the write
enable latch (WEL) bit.
• The block protect (BP1, BP0) bits in the status register are used to configure part of the memory as
read-only.
• The write protect (W) signal is used to protect the block protect (BP1, BP0) bits in the status register.
For any instruction to be accepted, and executed, chip select (S) must be driven high after the rising edge of
serial clock (C) for the last bit of the instruction, and before the next rising edge of serial clock (C).
Two points to note in the previous sentence:
• The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth bit of a data byte,
depending on the instruction (except for read status register (RDSR) and read (READ) instructions).
• The “next rising edge of serial clock (C)” might (or might not) be the next bus transaction for some other
device on the SPI bus.

Table 3. Write-protected block size

Status register bits

Protected block Protected array addresses
BP1 BP0

0 0 None None
0 1 Upper quarter 60000h - 7FFFFh
1 0 Upper half 40000h - 7FFFFh
1 1 Whole memory 00000h - 7FFFFh

DS12179 - Rev 3 page 10/44

 M95M04-DR
Instructions

6 Instructions

Each command is composed of bytes (MSB bit transmitted first), initiated with the instruction byte, as summarized
in Table 4.
If an invalid instruction is sent (one not contained in Table 4), the device automatically enters in a wait state until
deselected.

Table 4. Instruction set

Instruction Description Instruction format

WREN Write enable 0000 0110

WRDI Write disable 0000 0100
RDSR Read status register 0000 0101
WRSR Write status register 0000 0001
READ Read from memory array 0000 0011
WRITE Write to memory array 0000 0010
RDID Read identification page 1000 0011
WRID Write identification page 1000 0010
RDLS Read identification page lock status 1000 0011
LID Lock identification page in react-only mode 1000 0010

For read and write commands to memory array and identification page the address is defined by three bytes as
explained in Table 5.

Table 5. Significant bits within the address bytes

Upper address byte Middle address byte Lower address byte

Instruction(1)(2)
b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

READ
X X X X X A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
or WRITE
RDID
X X X X X X X X X X X X X 0 X A8 A7 A6 A5 A4 A3 A2 A1 A0
or WRID
RDLS
X X X X X X X X X X X X X 1 X X X X X X X X X X
or LID

1. A: Significant address bit

2. X: Don't Care bit

DS12179 - Rev 3 page 11/44

 M95M04-DR
Write enable (WREN)

6.1 Write enable (WREN)

The write enable latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this
is to send a write enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, chip select (S) is driven low, and the bits of the
instruction byte are shifted in, on serial data input (D). The device then enters a wait state. It waits for the device
to be deselected by chip select (S) being driven high.

Figure 8. Write enable (WREN) sequence

0 1 2 3 4 5 6 7

C
Instruction

DT41478V2
High impedance
Q

DS12179 - Rev 3 page 12/44

 M95M04-DR
Write disable (WRDI)

6.2 Write disable (WRDI)

One way of resetting the write enable latch (WEL) bit is to send a write disable instruction to the device.
As shown in Figure 9, to send this instruction to the device, chip select (S) is driven low, and the bits of the
instruction byte are shifted in, on serial data input (D).
The device then enters a wait state. It waits for a the device to be deselected, by chip select (S) being driven high.
The write enable latch (WEL) bit, in fact, becomes reset by any of the following events:
• Power-up
• WRDI instruction execution
• WRSR instruction completion
• WRITE instruction completion.

Figure 9. Write disable (WRDI) sequence

0 1 2 3 4 5 6 7

C
Instruction

DT41478V2
High impedance
Q

DS12179 - Rev 3 page 13/44

 M95M04-DR
Read status register (RDSR)

6.3 Read status register (RDSR)

The read status register (RDSR) instruction is used to read the status register. The status register may be read at
any time, even while a write or write status register cycle is in progress. When one of these cycles is in progress,
it is recommended to check the write in progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status register continuously, as shown in Figure 10.

Figure 10. Read Status register (RDSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction

Status Register Out Status Register Out

High impedance
Q

DT47548V2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

The status and control bits of the status register are detailed in the following subsections.

6.3.1 WIP bit

The WIP bit (write in progress) is a read-only flag that indicates the ready/busy state of the device. When a write
command (WRITE, WRSR, WRID, LID) has been decoded and a write cycle (tW) is in progress, the device is
busy and the WIP bit is set to 1. When WIP = 0 the device is ready to decode a new command.
During a write cycle, reading continuously the WIP bit allows to detect when the device becomes ready (WIP = 0)
to decode a new command.

6.3.2 WEL bit

The WEL bit (write enable latch) bit is a flag that indicates the status of the internal write enable latch. When WEL
is set to 1, the write instructions (WRITE, WRSR, WRID, LID) are executed; when WEL is set to 0, any decoded
write instruction is not executed.
The WEL bit is set to 1 with the WREN instruction. The WEL bit is reset to 0 after the following events:
• Write disable (WRDI) instruction completion
• Write instructions (WRITE, WRSR, WRID, LID) completion including the write cycle time tW
• Power-up

6.3.3 BP1, BP0 bits

The block protect (BP1, BP0) bits are non volatile. They define the size of the area to be software-protected
against Write instructions. These bits are written with the write status register (WRSR) instruction. When one or
both of the block protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3) becomes
protected against write (WRITE) instructions. The block protect (BP1, BP0) bits can be written provided that the
hardware protected mode has not been set.

DS12179 - Rev 3 page 14/44

 M95M04-DR
Read status register (RDSR)

6.3.4 SRWD bit

The status register write disable (SRWD) bit is operated in conjunction with the write protect (W) signal. The
status register write disable (SRWD) bit and write protect (W) signal enable the device to be put in the hardware
protected mode (when the status register write disable (SRWD) bit is set to 1, and write protect (W) is driven low).
In this mode, the non-volatile bits of the status register (SRWD, BP1, BP0) become read-only bits and the write
status register (WRSR) instruction is no longer accepted for execution.

Table 6. Status register format

DS12179 - Rev 3 page 15/44

 M95M04-DR
Write status register (WRSR)

6.4 Write status register (WRSR)

The write dtatus register (WRSR) instruction is used to write new values to the status register. Before it can be
accepted, a write enable (WREN) instruction must have been previously executed.
The write Status register (WRSR) instruction is entered by driving chip select (S) low, followed by the instruction
code, the data byte on serial data input (D) and chip select (S) driven high. Chip select (S) must be driven high
after the rising edge of serial clock (C) that latches in the eighth bit of the data byte, and before the next rising
edge of serial clock (C). Otherwise, the write status register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 11.

Figure 11. Write status register (WRSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C

Instruction Status Register In

D 7 6 5 4 3 2 1 0

MSB

DT47556V2
High impedance
Q

Driving the chip select (S) signal high at a byte boundary of the input data triggers the self-timed write cycle that
takes tW to complete (as specified in AC tables in Section 9 DC and AC parameters).
While the write status register cycle is in progress, the status register may still be read to check the value of the
write in progress (WIP) bit: the WIP bit is 1 during the self-timed write cycle tW, and 0 when the write cycle is
complete. The WEL bit (Write enable latch) is also reset at the end of the write cycle tW.
The write status register (WRSR) instruction enables the user to change the values of the BP1, BP0 and SRWD
bits:
• The block protect (BP1, BP0) bits define the size of the area that is to be treated as read-only, as defined in
Table 3.
• The SRWD (status register write disable) bit, in accordance with the signal read on the write protect pin
(W), enables the user to set or reset the write protection mode of the status register itself, as defined in
Table 7. When in write-protected mode, the write status register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including
the tW write cycle.
The write status register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in the status register. Bits
b6, b5, b4 are always read as 0.

DS12179 - Rev 3 page 16/44

 M95M04-DR
Write status register (WRSR)

Table 7. Protection modes

Memory content
SRWD
W signal Mode Write protection of the Status register Protected
bit Unprotected area(1)
area(1)

1 0 Status register is writable (if the WREN

Software- instruction has set the WEL bit).
0 0 Write- Ready to accept
protected
The values in the BP1 and BP0 bits can be protected write instructions
(SPM)
1 1 changed.

Hardware- Status register is hardware write-protected.

Write- Ready to accept
0 1 protected The values in the BP1 and BP0 bits cannot be protected write instructions
(HPM) changed.

1. As defined by the values in the Block protect (BP1, BP0) bits of the Status register. See Table 3.

The protection features of the device are summarized in Table 7.

When the status register write disable (SRWD) bit in the status register is 0 (its initial delivery state), it is possible
to write to the status register (provided that the WEL bit has previously been set by a WREN instruction),
regardless of the logic level applied on the write protect (W) input pin.
When the status register write disable (SRWD) bit in the Status register is set to 1, two cases should be
considered, depending on the state of the write protect (W) input pin:
• If write protect (W) is driven high, it is possible to write to the status register (provided that the WEL bit has
previously been set by a WREN instruction).
• If write protect (W) is driven low, it is not possible to write to the status register even if the WEL bit has
previously been set by a WREN instruction. (attempts to write to the status register are rejected, and are
not accepted for execution). As a consequence, all the data bytes in the memory area, which are software-
protected (SPM) by the block protect (BP1, BP0) bits in the status register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the hardware-protected mode (HPM) can be entered by:
• either setting the SRWD bit after driving the write protect (W) input pin low,
• or driving the write protect (W) input pin low after setting the SRWD bit.
Once the hardware-protected mode (HPM) has been entered, the only way of exiting it is to pull high the write
protect (W) input pin.
If the write protect (W) input pin is permanently tied high, the hardware-protected mode (HPM) can never be
activated, and only the software-protected mode (SPM), using the block protect (BP1, BP0) bits in the status
register, can be used.

DS12179 - Rev 3 page 17/44

 M95M04-DR
Read from memory array (READ)

6.5 Read from memory array (READ)

As shown in Figure 12, to send this instruction to the device, chip select (S) is first driven low. The bits of the
instruction byte and address bytes are then shifted in, on serial data input (D). The address is loaded into an
internal address register, and the byte of data at that address is shifted out, on serial data output (Q).

Figure 12. Read from memory array (READ) sequence

DT13878aV2
If chip select (S) continues to be driven low, the internal address register is incremented automatically, and the
byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be
continued indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur
at any time during the cycle.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.

DS12179 - Rev 3 page 18/44

 M95M04-DR
Write to memory array (WRITE)

6.6 Write to memory array (WRITE)

As shown in Figure 13, to send this instruction to the device, chip select (S) is first driven low. The bits of the
instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D).
The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. The self-
timed write cycle, triggered by the chip select (S) rising edge, continues for a period tW (as specified in AC
characteristics in Section 9 DC and AC parameters), at the end of which the write in progress (WIP) bit is reset to
0.

Figure 13. Byte write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction 24-bit address Data byte

D 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0

DT30905V2
High impedance
Q

In the case of Figure 13, chip select (S) is driven high after the eighth bit of the data byte has been latched in,
indicating that the instruction is being used to write a single byte. However, if chip select (S) continues to be
driven low (as shown in Figure 14), the next byte of input data is shifted in, so that more than a single byte,
starting from the given address towards the end of the same page, can be written in a single internal write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented.
If more bytes are sent than fits up to the end of the page, a condition known as “roll-over” occurs. In case of
roll-over, the bytes exceeding the page size are overwritten from location 0 of the same page.
The instruction is not accepted, and is not executed, under the following conditions:
• if the write enable latch (WEL) bit has not been set to 1 (by executing a write enable instruction just before),
• if a write cycle is already in progress,
• if the device has not been deselected, by driving high chip select (S), at a byte boundary (after the eighth
bit, b0, of the last data byte that has been latched in),
• if the addressed page is in the region protected by the block protect (BP1 and BP0) bits.
Note: The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed
byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as
“1”.

DS12179 - Rev 3 page 19/44

 M95M04-DR
Write to memory array (WRITE)

Figure 14. Page write (WRITE) sequence

S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

C
Instruction 24-bit address Data byte 1

23 22 21
D 3 2 1 0 7 6 5 4 3 2 1 0

C
Data byte 2 Data byte 3 Data byte N

DT30906V2
D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0

DS12179 - Rev 3 page 20/44

 M95M04-DR
Read identification page

6.7 Read identification page

The identification page (512 bytes) is an additional page that can be written and (later) permanently locked in
Read-only mode.
This page is read with the read identification page instruction (see Table 4). The chip select signal (S) is first
driven low, the bits of the instruction byte and address bytes are then shifted in, on serial data input (D). Address
bit A10 must be 0, upper address bits are "Don't care", and the data byte pointed to by the lower address bits
[A8:A0] is shifted out on serial data output (Q). If chip select (S) continues to be low, the internal address register
is automatically incremented, and the byte of data at the new address is shifted out.
The number of bytes to read in the ID page must not exceed the page boundary, otherwise unexpected data are
read (e.g. when reading the ID page from location 200d, the number of bytes must be lower than or equal to
312d, as the ID page boundary is 512 bytes).
The read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur
at any time during the cycle. The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.

Figure 15. Read identification page sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction 24-bit address

D 23 22 21 3 2 1 0
MSB

Data Out 1 Data Out 2

High impedance

DT30907V2
Q 7 6 5 4 3 2 1 0 7
MSB

DS12179 - Rev 3 page 21/44

 M95M04-DR
Write identification page

6.8 Write identification page

The identification page (512 bytes) is an additional page that can be written and (later) permanently locked in
Read-only mode.
Writing this page is achieved with the write identification page instruction (see Table 4). The chip select signal (S)
is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in
on serial data input (D). Address bit A10 must be 0, upper address bits are "Don't care", the lower address bits
[A8:A0] define the byte address within the identification page. The instruction sequence is shown in Figure 16.

Figure 16. Write identification page sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C

Instruction 24-bit address Data byte

D 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0

DT30909V2
High impedance
Q

DS12179 - Rev 3 page 22/44

 M95M04-DR
Read lock status

6.9 Read lock status

The read lock status instruction (see Table 4) is used to check whether the identification page is locked or not in
Read-only mode. The read lock status sequence is defined with the chip select (S) first driven low. The bits of the
instruction byte and address bytes are then shifted in on serial data input (D). Address bit A10 must be 1, all other
address bits are "Don't Care". The lock bit is the LSB (least significant bit) of the byte read on serial data output
(Q). It is at “1” when the lock is active and at “0” when the lock is not active. If chip select (S) continues to be
driven low, the same data byte is shifted out. The read cycle is terminated by driving chip select (S) high.
The instruction sequence is shown in Figure 17.

Figure 17. Read lock status sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C

Instruction 24-bit address

D 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
High impedance

DT30910V2
Q 7 6 5 4 3 2 1 0 7
MSB
MS30910V1

DS12179 - Rev 3 page 23/44

 M95M04-DR
Lock ID

6.10 Lock ID
The lock ID instruction permanently locks the identification page in read-only mode. Before this instruction can be
accepted, a write enable (WREN) instruction must have been executed.
The lock ID instruction is issued by driving chip select (S) low, sending the instruction code, the address and a
data byte on serial data input (D), and driving chip select (S) high. In the address sent, A10 must be equal to 1,
all other address bits are "Don't Care". The data byte sent must have the b0 bit equal to 1 (b0=1) and the others
value of the bits b7 to b1 are "Don't Care". The data byte has the following format: xxxx xxx1 (where x = Don't
Care)".
Chip select (S) must be driven high after the rising edge of serial clock (C) that latches in the eighth bit of the data
byte, and before the next rising edge of serial clock (C). Otherwise, the lock ID instruction is not executed.
Driving chip select (S) high at a byte boundary of the input data triggers the self-timed write cycle whose duration
is tW (as specified in AC characteristics in Section 9 DC and AC parameters). The instruction sequence is shown
in Figure 18.
The instruction is discarded, and is not executed, under the following conditions:
• If a write cycle is already in progress
• If block protect bits (BP1,BP0) = (1,1)
• If a rising edge on chip select (S) happens outside of a byte boundary
• If the identification is already locked.

Figure 18. Lock ID sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C

Instruction 24-bit address Data byte

D 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0

DT30911V2
High impedance
Q

6.11 Error correction code (ECC x 4) and write cycling

M95M04-DR devices offer an error correction code (ECC), an internal logic function transparent for the SPI
communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes (A group of four bytes is located at
addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). Even if the ECC function is performed on groups
of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles
the three other bytes located in the same group. As a consequence, the maximum cycling budget is defined at
group level and the cycling can be distributed over the four bytes of the group: the sum of the cycles seen by
byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in Section 9.

DS12179 - Rev 3 page 24/44

 M95M04-DR
Power-up and delivery state

7 Power-up and delivery state

7.1 Power-up state

After power-up, the device is in the following state:
• standby power mode
• deselected (after power-up, a falling edge is required on chip select (S) before any instructions can be
started)
• not in the hold condition
• the write enable latch (WEL) is reset to 0
• write in progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the status register are unchanged from the previous power-down (they are
non-volatile bits).

7.2 Initial delivery state

The device is delivered with the memory array and identification page bits set to all 1s (each byte = FFh). The
status register write disable (SRWD) and block protect (BP1 and BP0) bits are initialized to 0.

DS12179 - Rev 3 page 25/44

 M95M04-DR
Maximum ratings

8 Maximum ratings

Stressing the device outside the ratings listed in Table 8 may cause permanent damage to the device. These
are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in
the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Table 8. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

TAMB Ambient operating temperature –40 130

TSTG Storage temperature –65 150 °C

TLEAD Lead temperature during soldering See note (1)

VO Output voltage –0.50 VCC + 0.6

VI Input voltage –0.50 6.5 V

VCC Supply voltage –0.50 6.5

IOL DC output current (Q = 0) - 5

mA
IOH DC output current (Q = 1) - 5

VESD Electrostatic discharge voltage (human body model)(2) - 4000 V

1. Compliant with JEDEC standard J-STD-020 (for small-body, Sn-Pb or Pb free assembly), the ST ECOPACK 7191395
specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July
2011).
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant
with ANSI/ESDA/JEDEC JS-001, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

DS12179 - Rev 3 page 26/44

 M95M04-DR
DC and AC parameters

9 DC and AC parameters

This section summarizes the operating conditions and the DC/AC characteristics.

Table 9. Operating conditions (range R)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.8 5.5 V

TA Ambient operating temperature –40 85 °C

Table 10. AC measurement conditions

Symbol Parameter Min. Max. Unit

CL Load capacitance - 30 pF

- Input rise and fall times - 25 ns

- Input pulse voltages 0.2 VCC to 0.8 VCC V

- Input and output timing reference voltages 0.3 VCC to 0.7 VCC V

Figure 19. AC measurement I/O waveform

Input and Output

Input Levels
Timing Reference Levels
0.8 ₓ VCC
0.7 ₓ VCC

DT00825cV2
0.3 ₓ VCC
0.2 ₓ VCC

DS12179 - Rev 3 page 27/44

 M95M04-DR
DC and AC parameters

Table 11. Cycling performance by groups of four bytes

Symb
Parameter Test condition Min. Max. Unit
ol

TA ≤ 25 °C, VCC(min) < VCC < VCC(max) - 4,000,000

Write cycle Write cycle
Ncycle
endurance(1) TA = 85 °C, VCC(min) < VCC < VCC(max) - 1,200,000
(2)

1. The write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where
N is an integer. The write cycle endurance is defined by characterization and qualification.
2. A write cycle is executed when either a page write, a byte write, a WRSR, a WRID or an LID instruction is decoded. When
using the byte write, the page write or the WRID instruction, refer also to Section 6.11 Error correction code (ECC x 4) and
write cycling.

Table 12. Memory cell data retention

Parameter Test conditions Min. Unit

Data retention(1) TA = 55 °C 40 Year

1. The data retention behaviour is checked in production, while the 40-year limit is defined from characterization and
qualification results.

Table 13. Capacitance

Symbol Parameter Test conditions(1) Min. Max. Unit

COUT Output capacitance (Q) VOUT = 0 V - 8 pF

Input capacitance (D) VIN = 0 V - 8 pF

CIN
Input capacitance (other pins) VIN = 0 V - 6 pF

1. Sampled only, not 100% tested, at TA = 25 °C and at a frequency of 5 MHz.

DS12179 - Rev 3 page 28/44

 M95M04-DR
DC and AC parameters

Table 14. DC characteristics

Symbol Parameter Test conditions Min Max Unit

ILI Input leakage current VIN = VSS or VCC - ±2

µA
ILO Output leakage current S= VCC, VOUT = VSS or VCC - ±2

C = 0.1 VCC / 0.9 VCC at 5 MHz, VCC = 1.8 V, Q = open - 1(1)

ICC Supply current (Read) C = 0.1 VCC / 0.9 VCC at 10 MHz, VCC = 3.3 V, Q = open - 2(2)
mA
C = 0.1 VCC / 0.9 VCC at 10 MHz, VCC = 5.5 V, Q = open - 3(3)

ICC0(4) Supply current (Write) During tW,S = VCC, - 2(5)

S= VCC, VIN = VSS or VCC, VCC = 1.8 V - 2

Supply current
ICC1 S= VCC, VIN = VSS or VCC, VCC = 3.3 V - 3 µA
(Standby power mode)
S= VCC, VIN = VSS or VCC, VCC = 5.5 V - 5

1.8 V ≤ VCC < 2.5 V - 0.45 0.25 VCC

VIL Input low voltage
2.5 V ≤ VCC < 5.5 V - 0.45 0.30 VCC

1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC + 1

VIH Input high voltage
2.5 V ≤ VCC < 5.5 V 0.70 VCC VCC + 1

IOL = 0.15 mA, VCC = 1.8 V - 0.3

V
VOL Output low voltage VCC = 2.5 V, IOL = 1.5 mA, or
- 0.4
VCC = 5.0 V, IOL = 2.0 mA

IOH = –0.1 mA, VCC = 1.8 V

VOH Output high voltage VCC = 2.5 V, IOH = -0.4 mA, or 0.80 VCC -
VCC = 5.0 V, IOH = -2.0 mA

1. 2 mA before year 2021 - week 07, DC107 on marking

2. 3 mA before year 2021 - week 07, DC107 on marking
3. 5 mA before year 2021 - week 07, DC107 on marking
4. Characterized only, not tested in production.
5. 3 mA before year 2021 - week 07, DC107 on marking

DS12179 - Rev 3 page 29/44

 M95M04-DR
DC and AC parameters

Table 15. AC characteristics

Test conditions specified in Table 9 and Table 10

VCC ≥ 1.8 V VCC ≥ 2.5 V

Symbol Alt. Parameter Unit
Min. Max. Min. Max.

fC fSCK Clock frequency DC 5 DC 10 MHz

tSLCH tCSS1 S active setup time 60 - 30 - ns

tSHCH tCSS2 S not active setup time 60 - 30 - ns

tSHSL tCS S Deselect time 60 - 40 - ns

tCHSH tCSH S active hold time 60 - 30 - ns

tCHSL - S not active hold time 60 - 30 - ns

tCH (1) tCLH Clock high time 90 - 40 - ns

tCL(1) tCLL Clock low time 90 - 40 - ns

tCLCH (2) tRC Clock rise time - 2 - 2 µs

tCHCL(2) tFC Clock fall time - 2 - 2 µs

tDVCH tDSU Data in setup time 20 - 10 - ns

tCHDX tDH Data in hold time 20 - 10 - ns

tHHCH - Clock low hold time after HOLD not active 60 - 30 - ns

tHLCH - Clock low hold time after HOLD active 60 - 30 - ns

tCLHL - Clock low set-up time before HOLD active 0 - 0 - ns

tCLHH - Clock low set-up time before HOLD not active 0 - 0 - ns

tSHQZ(2) tDIS Output disable time - 80 - 40 ns

tCLQV (3) tV Clock low to output valid - 80 - 40 ns

tCLQX tHO Output hold time 0 - 0 - ns

tQLQH (2) tRO Output rise time - 80 - 40 ns

tQHQL(2) tFO Output fall time - 80 - 40 ns

tHHQV tLZ HOLD high to output valid - 80 - 40 ns

tHLQZ (2) tHZ HOLD low to output high-Z - 80 - 40 ns

tW tWC Write time - 5(4) - 5(4) ms

1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Characterized only, not tested in production.
3. tCLQV must be compatible with tCL (clock low time): if tSU is the Read setup time of the SPI bus master, then tCL must be
equal to or greater than tCLQV + tSU.
4. Write time for LID instruction is 10 ms.

DS12179 - Rev 3 page 30/44

 M95M04-DR
DC and AC parameters

Figure 20. Serial input timing

tSHSL

tCHSL tSLCH tCH tCHSH tSHCH

tDVCH tCHCL tCL tCLCH

tCHDX
D
MSB IN LSB IN

DT01447dV2
High impedance
Q

Figure 21. Hold timing

S
tHLCH

tCLHL tHHCH

C
tCLHH

tHLQZ tHHQV

DT01448cV2
HOLD

Figure 22. Serial output timing

S
tCH tSHSL
C

tCLQV tCLCH tCHCL tCL tSHQZ

tCLQX

tQLQH
DT01449gV2

tQHQL

ADDR
D LSB IN

DS12179 - Rev 3 page 31/44

 M95M04-DR
Package information

10 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

10.1 SO8N package information

This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package.

Figure 23. SO8N – Outline

h x 45˚

A2 A
c
b ccc
e

0.25 mm
D SEATING GAUGE PLANE
PLANE
C k
8

O7_SO8_ME_V2
E1 E
1 L
A1
L1

1. Drawing is not to scale.

DS12179 - Rev 3 page 32/44

 M95M04-DR
SO8N package information

Table 16. SO8N – Mechanical data

millimeters inches (1)

Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.750 - - 0.0689
A1 0.100 - 0.250 0.0039 - 0.0098
A2 1.250 - - 0.0492 - -
b 0.280 - 0.480 0.0110 - 0.0189
c 0.170 - 0.230 0.0067 - 0.0091

D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969

E 5.800 6.000 6.200 0.2283 0.2362 0.2441

E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575

e - 1.270 - - 0.0500 -
h 0.250 - 0.500 0.0098 - 0.0197
k 0° - 8° 0° - 8°
L 0.400 - 1.270 0.0157 - 0.0500
L1 - 1.040 - - 0.0409 -
ccc - - 0.100 - - 0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per
side.

Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the
outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash,
but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash,
protusions or gate burrs is bottom side.

Figure 24. SO8N - Footprint example

0.6 (x8)
3.9
6.7

O7_SO8N_FP_V2

1.27

1. Dimensions are expressed in millimeters.

DS12179 - Rev 3 page 33/44

 M95M04-DR
WLCSP8 package information

10.2 WLCSP8 package information

This WLCSP is a 8-ball, 2,809 x 1,863 mm, wafer level chip scale package.

Figure 25. WLCSP8 - Outline with BSC

e3
Orientation aaa

bbb Z
(2X) e4 Orientation
reference
E reference DETAIL A
X H
Y

e2

BACKSIDE PROTECTION
D e1 e

b
A1

aaa G A3
(2X) F A

A2
TOP VIEW BOTTOM VIEW SIDE VIEW

A1

E1_WLCSP8_4MF9V_ME_V1
eee Z

b Z
ccc ZXY
ddd Z SEATING PLANE

DETAIL A

1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.

DS12179 - Rev 3 page 34/44

 M95M04-DR
WLCSP8 package information

Table 17. WLCSP8 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.540 0.580 0.0197 0.0213 0.0228

A1 - 0.190 - - 0.0075 -
A2 - 0.325 - - 0.0128 -
A3 - 0.025 - - 0.0010 -

b(2) - 0.270 - - 0.0106 -

D - 2.809 2.829 - 0.1106 0.1114

E - 1.863 1.883 - 0.0733 0.0741
e - 1.100 - - 0.0433 -
e1 - 2.100 - - 0.0827 -
e2 - 0.500 - - 0.0197 -
e3 - 1.000 - - 0.0394 -
e4 - 1.400 - - 0.0551 -
F - 0.232 - - 0.0091 -
G - 0.355 - - 0.0140 -
H - 0.200 - - 0.0079 -
aaa - 0.110 - - 0.0043 -
bbb - 0.110 - - 0.0043 -
ccc - 0.110 - - 0.0043 -
ddd - 0.060 - - 0.0024 -
eee - 0.060 - - 0.0024 -

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

Figure 26. WLCSP8 - Footprint example

1.000

1.400
0.200

0.500
E1_WLCSP8_4MF9V_FP_V1

1.100 2.100

0.270

1. Dimensions are expressed in millimeters.

DS12179 - Rev 3 page 35/44

 M95M04-DR
TSSOP8 package information

10.3 TSSOP8 package information

This TSSOP is an 8-lead, 3 x 6.4 mm, 0.65 mm pitch, thin shrink small outline package.

Figure 27. TSSOP8 – Outline

8 5

k
E1 E
A1 L

L1
1 4

6P_TSSOP8_ME_V3
A A2
c
b e

1. Drawing is not to scale.

Table 18. TSSOP8 – Mechanical data

millimeters inches (1)

Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079

D(2) 2.900 3.000 3.100 0.1142 0.1181 0.1220

e - 0.650 - - 0.0256 -
E 6.200 6.400 6.600 0.2441 0.2520 0.2598

E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -
k 0° - 8° 0° - 8°
aaa - - 0.100 - - 0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per
side.

DS12179 - Rev 3 page 36/44

 M95M04-DR
TSSOP8 package information

Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the
outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash,
but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash,
protusions or gate burrs is bottom side.

Figure 28. TSSOP8 – Footprint example

1.55
0.40

0.65

2.35

6P_TSSOP8_FP_V2
5.80
7.35

1. Dimensions are expressed in millimeters.

DS12179 - Rev 3 page 37/44

 M95M04-DR
Ordering information

11 Ordering information

Table 19. Ordering information scheme

Example: M95 M04- D R MN 6 T P /V

Device type
M95 = SPI serial access EEPROM
Device function
M04‑- = 4096 Kbit
Device family
D = with additional identification page
Operating voltage
R = VCC = 1.8 V to 5.5 V

Package(1)
MN = SO8N (150 mil width)
DW = TSSOP8 (169 mil width)
CS = WLCSP
Device grade
6 = Industrial: device tested with standard test flow over -40 to 85 °C
Option
T = Tape and reel packing
blank = tube packing
Planting technology
P = RoHS compliant and halogen-free (ECOPACK2)
Process
/V = Manufacturing technology code

1. All packages are ECOPACK2 (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants).

Note: Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and
therefore not approved for use in production. ST is not responsible for any consequences resulting from such
use. In no event will ST be liable for the customer using any of these engineering samples in production. ST
Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

DS12179 - Rev 3 page 38/44

 M95M04-DR

Revision history
Table 20. Document revision history

Date Revision Changes

24-Oct-2019 1 Initial release.

Updated:
• Features, Section 6.10 Lock ID
• Titles in Figure 25. WLCSP8 - Outline with BSC, Table 17. WLCSP8 - Mechanical data and
22-Feb-2021 2 Figure 26. WLCSP8 - Footprint example
• Table 14. DC characteristics, Table 15. AC characteristics
added sentence at the top of Section 10.2 WLCSP8 package information, note 2,3 and 5 in Table 14. DC
characteristics
Updated: Figure 4. Block diagram, note 4 of Table 14. DC characteristics, note 2 of Table 15. AC characteristics,
31-Mar-2023 3 Section 10.1 SO8N package information, Section 10.3 TSSOP8 package information, Figure 26. WLCSP8 -
Footprint example

DS12179 - Rev 3 page 39/44

 M95M04-DR
Contents

Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Serial clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.4 Chip select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.6 Write protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.8 VSS ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Operating features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
5.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.1 Operating supply voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.3 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.4 Write status register (WRSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.5 Read from memory array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.6 Write to memory array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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 M95M04-DR
Contents

6.7 Read identification page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.8 Write identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.9 Read lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.10 Lock ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.11 Error correction code (ECC x 4) and write cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2 WLCSP8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

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 M95M04-DR
List of figures

List of figures
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. WLCSP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Write enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Write disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Read Status register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Write status register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Read from memory array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Byte write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Page write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. Read identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Read lock status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21. Hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 22. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 23. SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 24. SO8N - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 25. WLCSP8 - Outline with BSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 26. WLCSP8 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 27. TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 28. TSSOP8 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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 M95M04-DR
List of tables

List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Signals vs. bump position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 3. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Significant bits within the address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Protection modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Operating conditions (range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. SO8N – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. WLCSP8 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. TSSOP8 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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 M95M04-DR

IMPORTANT NOTICE – READ CAREFULLY

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
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DS12179 - Rev 3 page 44/44