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Verilog Basic Syntax and Examples

This document discusses the basics of the Verilog hardware description language including modules, ports, signals, comments, values, constants, operators, instantiating modules, and concurrency. It provides examples of module definitions, port connections, and other language constructs.

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ALISHBA AZAM
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
11 views

Verilog Basic Syntax and Examples

This document discusses the basics of the Verilog hardware description language including modules, ports, signals, comments, values, constants, operators, instantiating modules, and concurrency. It provides examples of module definitions, port connections, and other language constructs.

Uploaded by

ALISHBA AZAM
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 42

VERILOG 2:

LANGUAGE BASICS
Verilog module

• Modules are basic building blocks. These are two example


module definitions which you should use:
in1 in2
// Safer traditional method
module abc (in1, in2, out);
input in1;
input in2;
output out; abc
<body of module>
endmodule

or out
// Shorter, info not repeated
module abc (
input in1,
input in2,
output out // no comma on last signal
);
<body of module>
endmodule

Others exist, but use only one of these two forms in this class
© B. Baas 35
Verilog Comments and Values
• Comments
– Single line
assign b = c; // A comment
– Multiple lines
/* This module filters a series of images at a
rate of “f” frames per second */
• Values of a single wire or register (not buses)
– 0 and 1 // Binary zero and one
– x or X // Unknown value due to things such as uninitialized state or
// two drivers driving the same net
– z or Z // High impedance, e.g., a node not driven by any circuit.
// This is identical to the “z” state of a tri-state output driver.
– others // Don’t worry about others

© B. Baas 36
Verilog Constants
• Can be specified in a number of formats; use only these four in this class:
– binary
– hexadecimal
– octal
– decimal
• Syntax: [size.in.bits]’[first.letter.of.base.of.representation][value]
• Underscore characters (“_”) are ignored and can greatly help readability
• Make sure to specify enough digits to cover the full range of the constant. Although
Quartus will probably not complain, other CAD tools may do something you are not
expecting especially with more complex number formats.
• Examples:
Value in binary Comment
• 1’b0 0
• 1’b1 1
• 4’b0101 0101
• 5’h0B 01011 // two hex digits for 5 bits, range of [0, +31]
• 16’h3F09 0011111100001001 // four hex digits for 16 bits
• 12’b0000_1010_0101 000010100101 // underscores are ignored
• 8’d003 00000011 // three base 10 digits for 8 bits
© B. Baas // which has range of [0, +255] 37
Constants With
parameter and `define
• There are two main methods to simplify constants by using
readable text to represent a number
– parameter
• Local to a module
• Usage:
parameter HALT = 4’b0101;
…
if (inst == HALT) begin
• Definitely use this for state names in state machines in this class
– `define macro
• Global text macro substitution using a compiler directive
• Usage:
`define HALT 4’b0101
…
if (inst == `HALT) begin // requires “back tick” “grave accent”
• Best when helpful to put all definitions in a global file; probably do not
use in this class

© B. Baas 38
Verilog Operators
• Operators: bit-wise
– negation ~
– AND &
– OR |
– XOR ^
– Shift a left by b bits a << b
– Shift a right by b bits a >> b
• Operators: logical (e.g., test for if-then-else)
– negation !
– AND &&
– OR ||
• Basic arithmetic
– addition +
– subtraction −
– multiplication *
– division /
– modulus %

© B. Baas 39
Verilog Operators

• Equality, inequalities, and relational operators—all


return a 1-bit true or false result
– equal ==
– not equal !=
– less than <
– greater than >
– less than or equal <=
• Not to be confused with the non-blocking assignment which
is used with flip-flops
– greater than or equal >=

© B. Baas 40
Verilog Operators

• Concatenation x = {a,b,c}
– Each input may be a wire or a reg
– The output may be a wire or a reg
– Example: if g, h, j, l, m are all 6 bits wide, then
all = {g,h,j,k,m}
is 30 bits wide g

j
{} all
– Example: to replicate the sign bit of a k
4-bit value a two times and assign it to b:
reg [5:0] b; m
b = {a[3], a[3], a};
If a were 1010, then b would be 111010
© B. Baas 41
* 3 Ways to Specify Hardware *
• There are three primary means to specify hardware circuits:
1) Instantiate another module
2) wires, assign statements
3) registers, always blocks
• Example instantiating modules inside a main module
module abc (in1, in2, out);
input in1;
input in2;
output out; module
name square_root
assign... sqr2

always... abc
instance
always... square_root
names
sqr1
square_root sqr1 (clk, reset, in1, out1);

square_root sqr2 (clk, reset, in2, out2);

endmodule module
name
© B. Baas 42
Concurrency

• All circuits operate


independently and
concurrently 101100…
– Different from most (wire)
programming paradigms
• This is natural if we
remember “hardware 010101…
verilog” describes (wire)
real circuit hardware:
transistors and wires
111001…
(reg)
© B. Baas 43
Declaring and Referencing Signals

• Single-bit wire and reg signals


– wire reset;
– reg start;
• Multiple-bit signals
– By convention, write [(MSB-1):0]
• Multiple-bit wire and reg signals
– wire [7:0] phase; // 8-bit signal
– reg [31:0] elevation; // 32-bit signal
• To reference part of a multi-bit signal
– phase[0] // LSB of phase
– elevation[7:0] // lowest byte

© B. Baas 44
Verilog Instantiation Syntax
• Ports of an instantiated module can be connected to signals referenced in
the module’s declaration assuming
they are in the same order but this module abc (in1, in2, out);
is dangerous so don’t do it. Instead input in1;
write out both the port name and input in2;
output out;
the connected signal as shown below. ...
endmodule

• // Don’t use this method! It works but typos can be difficult to catch
abc instance1 (phase3, angle, magnitude3); // phase3 connected to in1, etc.
• // This is good. Ports are in the same order as in the module declaration
abc instance2 (
.in1 (phase1),
.in2 (angle),
.out (magnitude1) ); // no comma on last port
• // This is good. Ports are not in the same order as in the module declaration
abc instance3 (
.in2 (angle), // in2 comes before in1 here but everything
.in1 (phase2), // still works ok
.out (magnitude2) );
© B. Baas 45
Verilog Instantiation Example

• In this example, two copies of the module “abc” are instantiated


in the higher-level module. As described in a later slide, only
wires can connect to the outputs of modules.

wire phase; // must be a wire module abc (in1, in2, out);


wire mag1; // must be a wire input in1;
// a, b, c may be wires, regs, input in2;
// or inputs of the module output out;
...
abc proc1 ( endmodule
.in1 (a),
.in2 (b),
.out (phase) );
phase
a in1 out in1 out mag1
abc proc2 ( b in2 c in2
.in1 (phase),
.in2 (c), proc1 proc2
.out (mag1) ); (abc) (abc)

© B. Baas 46
Describing Hardware
module definition
module module_name (port_name_list);
• As previously stated, there are three
main ways to describe hardware
wire
circuits which produce a “signal”, module
“electrical node”, “word”, (whatever
instance
you like to call it) inside a module
definition:
– Instantiate a module which has
wires connected to its outputs
wire
– The assign command which defines assign
a wire statement
– The always command which defines
a reg
• All of these must be declared at the
module definition level—not inside reg
always
each other (e.g., a module instance
can not be declared inside an always block
block)
© B. Baas endmodule 47
Module Inputs and Outputs
module definition
• There are three main module module_name (port_name_list);
possible inputs to a
module instance:
– A wire
– A reg wire
– An input into the wire
reg module
module (behaves just
like a wire) instance
• The output of a module input
instance is always a
wire, at least for this
endmodule
class
– This is perhaps the most
tricky case

© B. Baas 48
Module Outputs
module definition
module module_name (port_name_list);
• All of these signal
types may be used as module wire wire
outputs in a module instance
definition:
– wire
– reg assign wire wire
– Another possibility statement
which is typically
uncommon is for an
input to pass directly reg wire
to a module output always
port block

input (output) wire


© B. Baas 49
endmodule
2) wire, assign
• Picture “always active” hardwired logic
• For now, declare all wires
wire out;
// a and b can be wires or regs or module inputs

a
out
b

© B. Baas 50
2) wire, assign
• Example:
wire out;
assign out = a & b;

a
& out
b

© B. Baas 51
2) wire, assign

• Example: multibit operands


wire [3:0] c, d; // c and d are both 4 bits
wire [4:0] sum; // sum is 5 bits so no overflow
assign sum = {c[3],c} + {d[3],d}; // sign extend inputs
// for 2’s complement

c
+ sum
d

© B. Baas 52
3) reg, always

• Picture a much more general way of assigning “wires” or


“signals” or “buses”
• “if/then/else” and “case” statements are permitted
• You could, but don’t use “for loops” in hardware blocks (use in
testing blocks is ok)
• Sequential execution
– statements execute in order to specify a circuit
• Syntax:
always @(sensitivity list) begin
statements
end
• Operation:
statements are executed when any signal in sensitivity list
changes
© B. Baas 53
3) reg, always

• Including all inputs in the sensitivity list can be tedious and prone
to errors especially as the number of statements in the always
block grows
always @(sensitivity list) begin
statements
end
• Verilog 1364-2001 allows the use of the
always @(*)
or
always @*
construct which tells the simulator to include all inputs in the
sensitivity list automatically. This can be very handy but is not
supported by all modern CAD tools.
• Ok to use for this class
– If you discover any issues, email the instructor and your TA
© B. Baas 54
3) reg, always
• Example: there is no difference whatsoever in this
AND gate from the AND gate built using assign
reg out;
always @(a or b) begin
out = a & b;
end

a
& out
b

© B. Baas 55
If-Then-Else Statement
• The general syntax is as follows:
if (condition)
statement
else
statement

• Or, taking advantage of the fact that a begin–end block acts as a


single statement:
if (condition) begin
statement;
statement;
...
end
else begin
statement;
statement;
...
© B. Baas end 56
If-Then-Else Statement

• Nesting an if block within another yields “else-if” blocks:

if (condition1) begin
statement;
statement;
...
end
else if (condition2) begin
statement;
statement;
...
end
else begin
statement;
statement;
...
end

© B. Baas 57
assign statement inputs
module definition
• In the same way, there are
module module_name (port_name_list);
three main possible “inputs”
to an assign statement:
– A wire
– A reg
– An input into the module wire
• Example: assign wire
input a;
reg
statement
wire b;
reg c; input
wire x;
assign x = a & b | c; endmodule

© B. Baas 58
always block inputs
module definition
• In the same way, there are
module module_name (port_name_list);
three main possible “inputs”
to an always block:
– A wire
– A reg
– An input into the module wire
(technically always reg
still a wire) reg
block
• Example:
input a; input
wire b;
reg c;
endmodule
reg x;
always @(*) begin
x = a & b | c;
end

© B. Baas 59
Special Block Style: initial

• This block executes only once at the beginning of the


simulation. It is the normal way to write testbench
code.
initial begin
...
end
– Example: circuit that generates a reset signal at the beginning
of a simulation
• For our usage, initial blocks are used in only two cases
1) Test bench code
2) Hardware code only to specify the contents of a ROM
memory (for EEC 180 FPGAs)

© B. Baas 60
Special Block Style: always begin

• This block executes repeatedly; it begins another


execution cycle as soon as it finishes. Therefore it must
contain some delay. This is a good construct for a clock
oscillator.
always begin
...
end
– Example: clock signal generator
– Can view as an always @(sensitivity list) construct
where the sensitivity list is always activated immediately
• Verilog suitable for always blocks is also suitable for
initial blocks

© B. Baas 61
Example: 2:1 Multiplexer

• Example #1
reg out;
always @(a or b or s) begin
if (s == 1'b0) begin
out = a;
end
a 0
else begin out
out = b; b 1
end
end s

© B. Baas 62
Example: 2:1 Multiplexer

• Example #1
• Normally always include begin and end statements even though
they are not needed when there is only one statement in the
particular block. Text struck out below could be taken out but
always add it anyway in this class.
reg out;
always @(a or b or s) begin
a 0
out
if (s == 1'b0) begin b 1
out = a;
end s
else begin
out = b;
end
end
© B. Baas 63
Example: 2:1 Multiplexer

• Example #2
• May be clearer in some cases, e.g., s==1’b0 sets off auto airbag
reg out;
always @(a or b or s) begin
out = b;
if (s == 1'b0) begin
a 0
out = a; out
end b 1
end
s

© B. Baas 64
Example: 2:1 Multiplexer

• Example #3
• May be clearer in some cases
reg out;
always @(a or b or s) begin
out = a;
if (s == 1'b1) begin
a 0
out = b; out
end b 1
end
s

© B. Baas 65
Example: 2:1 Multiplexer

• Example #4
• Simpler but less clear way of writing if/then/else called
"inline if" or "conditional operator" which is also found in
some programming languages

reg out;
always @(a or b or s) begin a 0
out = s ? b : a;
out
b 1
end
s

© B. Baas 66
Example: 2:1 Multiplexer

• Example #5
• The inline conditional operator can also be used to define wires

wire out;
assign out = s ? b : a;

a 0
out
b 1

© B. Baas 67
Case Statement
• The general syntax is as follows:
• case_expression case (case_expression)
value1: statement
– normally a multi-bit bus of wire or reg
value2: statement
• valuei targets value3: statement
– normally 0, 1, or ...
a wildcard character (for casez and casex) valueN: statement
• statement default: statement
endcase
1) An arbitrary-length block of verilog
code beginning with “begin” and
ending with “end”
begin
a = b + c;
....
end
2) A single verilog statement
• If multiple valuei targets match the case_expression, only the first one
that matches is taken

© B. Baas 68
Case Statement: default

• The default case is optional


• It may be beneficial to set the output to a
special value such as “x” even if you expect
the default case will never be reached case (wire or reg)
value1: statement
– For example:
default: begin
value2: statement
out = 4’bxxxx; value3: statement
end ...
– Setting unused values to “x” makes them valueN: statement
“don’t care states” which should allow the default: statement
synthesis tool to simplify logic endcase
– Setting unused input values to an easily-
recognizable value (such as x’s) could make
mistakes easier to spot during debugging
– Setting the output to “x” may cause
warnings with some CAD tools

© B. Baas 69
casez and casex

• case
− Normal case statement
• casez
− Allows use of wildcard “?” character for don’t cares in the
target values
casez(in)
4’b1???: out = r;
4’b01??: out = s;
4’b0000: out = t;
default: out = 4’bxxxx;
endcase
• casex
– Do not use it for this class. It can use “z” or “x” logic
– Recommendation: probably never use it for hardware

© B. Baas 70
Example: 4:1 Multiplexer

• Example: 4:1 multiplexer


reg out; // must be a reg to be set in an always block!

always @(a or b or c or d or s1 or s0) begin


case ({s1,s0}) // concatenate two select signals
2’b00: begin
out = a;
end
2’b01: begin a 00
out = b;
end
2’b10: begin b 01
out = c; out
end
2’b11: begin c 10
out = d;
end d 11
default: begin // does nothing
out = 1’bx;
end s1,s0
endcase
end // end of always block
© B. Baas 71
Example: 4:1 Mux with zero on
two inputs
• Example #1

reg out; // must be a reg to be set in an always block!

always @(c or d or s1 or s0) begin


case ({s1,s0})
2’b00: begin
out = c;
end c 00
2’b01: begin
out = 1’b0; 01
end 0
2’b10: begin out
end
out = 1’b0; 0 10
2’b11: begin 11
out = d; d
end
default: begin
out = 1’b0; // zero s1,s0
end
endcase
© B. Baasend // end of always block 72
Example: 4:1 Mux with zero on
two inputs
• Example #2
• Here the case’s default section is used

reg out; // must be a reg to be set in an always block!

always @(c or d or s1 or s0) begin


case ({s1,s0})
2’b00: begin c 00
out = c;
end 01
0
2’b11: begin
out
out = d; 0 10
end
d 11
default: begin
out = 1’b0;
end s1,s0
endcase
end // end of always block
© B. Baas 73
Example: 4:1 Mux with zero on
two inputs
• Example #3
• Here out is set to a default value before the case block

reg out; // must be a reg to be set in an always block!

always @(c or d or s1 or s0) begin


out = 1’b0; // set out to a “default” value
case ({s1,s0}) c 00
2’b00: begin
out = c; 0 01
end out
0 10
2’b11: begin
out = d; d 11
end
endcase
end // end of always block
s1,s0

© B. Baas 74
Example: 4:1 Mux with zero on
two inputs
• Example #4
• Here if statements are used. Clearly there are many solutions.

reg out; // must be a reg to be set in an always block!

always @(c or d or s1 or s0) begin


out = 1’b0; // set “default”
if ({s1,s0} == 2’b00) begin c 00
out = c;
end 0 01
out
if (s1==1’b1 && s0==1’b1) begin
out = d;
0 10
end 11
end // end of always block d

s1,s0

© B. Baas 75

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