Digital Logic Design By Alishba Azam Malik

Lab 09
Implementation of Multiplexer / Demultiplexer , Data flow
Level Programming in Verilog

OBJECTIVES

 Design and of both Multiplexor and De-Multiplexer

 Designing Large block using smaller block of Multiplexer

COMPONENTS REQUIRED

 Heath Kit Digital Trainer

 7411, 3 I/P AND gate
 7432 , OR gate
 7404 hex inverter
 Spartan 3e Starter Board

INTRODUCTION

Multiplexer:
Multiplexer (MUX), sometimes called data selector is a combinational logic circuit that selects
on of 2n inputs and route it to the output. Multiplexer means transmitting large number of
information units over smaller number of channels or lines. In a digital Multiplexer, the selection
of a particular line from 2 n inputs is controlled by n select lines of multiplexer. Fig shows the
block diagram and truth table for a 4x1 MUX.

Fig: Block Diagram and truth table of 4x1 MUX

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Large Multiplexers can be implemented using smaller blocks of multiplexors. For example,
consider an 8x1 MUX, this can be implemented using 2 4x1 MUXES and 1 2x1 MUX as shown
in figure.

Fig: Implementation of 8x1 MUX using 4x1 and 2x1 MUX

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Demultiplexer:
The Demultiplexer is combinational logic circuit that performs the reverse operation of
Multiplexer. It has only one input line and select lines. For n select lines, it has 2 n output lines.
Select lines rout the input to the output line. By applying logic 1 to the input, circuits act like
typical decoder. Block diagram of 1x4 Demultiplexer and its truth table is shown in figure.

Fig: Block Diagram and Truth table for 1x4 Demultiplexer

Lab Activity: A Simple Program of dataflow level Implementation of MUX

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Data Flow Level :

Dataflow modeling describes hardware in terms of the flow of data from input to output.The
dataflow modeling style is mainly used to describe combinational circuits. For example, to
describe an AND gate using dataflow, the code will look something like this:

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In the above code, we executed the functionality of the AND gate with the help of the AND (&)
operator. That is what dataflow modeling is about. It utilizes operators that act on operands
and gives the desired relationship between output and input.
Nets:

 Driven by the output of some device.

 declared as an input or inout port.
 on the left-hand side of a continuous assignment.

Continuous Assignment

The continuous assignment statement is the main construct of dataflow modeling and is used
to drive (assign) value to the net. It starts with the keyword assign.

There are some characteristics we should keep in mind while we use dataflow modeling. They
are:

 Continuous assignments are always active. That is the LHS net value changes as soon as
the value of any operand in the RHS changes.
 The LHS of an assignment should be either scalar or vector nets or a concatenation of
both. Registers are not applicable on the LHS.
 The RHS of the assignment can be register, net, or function calls of scalar or vector type.
 Delays can be specified.

Regular Assignment Delay

We assign a delay value in the continuous assignment statement. The delay value is specified
after the keyword assign. For example,
assign #10 out = a & b;

To get a clear understanding of how it works, let’s see how the simulated waveform looks like
for the following code:
module and_gate(a,b,out)

input a,b;

output out;

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assign #10 out = a & b;

endmodule

Simulation Waveform

Note the following changes in waveform:

1. a and b goes low at 5 ns, out goes low 10 time units later. That is 15 ns.
2. a and b is high at 20 ns, out goes high 10 time units later. That is 30 ns
3. a goes low at 40 ns, out goes low 10 time units later. That is 50 ns.
4. a goes high at 65 ns but becomes low at 70 ns. Therefore, at the time of re-computation
(i.e., 75 ns), a and b are low, out will be low. Thus, a pulse of width less than the
specified delay is not propagated to the output. This property is called inertial delay.

Verilog Code for 1-4 DEMUX Dataflow Modelling

module demux_1_to_4(

input d,

input s0,

input s1,

output y0,

output y1,

output y2,

output y3

);

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assign s1n = ~ s1;

assign s0n = ~ s0;

assign y0 = d& s0n & s1n;

assign y1 = d & s0 & s1n;

assign y2 = d & s0n & s1;

assign y3 = d & s0 & s1;

endmodule

//Testbench code for 1-4 DEMUX Dataflow Modelling

initial begin

// Initialize Inputs

d = 1;

s0 = 0;

s1 = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

#100;d = 1;s0 = 1;s1 = 0;

#100;d = 1;s0 = 0;s1 = 1;

#100;d = 1;s0 = 1;s1 = 1;

end

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Review Questions:

1. Design and implement a 4x1 Multiplexer

2. Design a 4x1 multiplexor using the smaller blocks of multiplexers. Draw the circuit
diagram and verify its table. Match result of question 1 & 2 and show the result on kit.
3. How decoder differs from a demultiplexer, explain.
4. Design 3x8 Decoder using case statement in Verilog and implement on FPGA.
5. Design multiplexor on gate level , data flow level and conditional operator using Verilog
and implement its schematic on FPGA.

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